CN116880908B - Instruction processing method and device, electronic equipment and readable storage medium - Google Patents
Instruction processing method and device, electronic equipment and readable storage medium Download PDFInfo
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- CN116880908B CN116880908B CN202311152758.2A CN202311152758A CN116880908B CN 116880908 B CN116880908 B CN 116880908B CN 202311152758 A CN202311152758 A CN 202311152758A CN 116880908 B CN116880908 B CN 116880908B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The embodiment of the invention provides an instruction processing method, an instruction processing device, electronic equipment and a readable storage medium, and relates to the technical field of computers, wherein the method comprises the following steps: acquiring an instruction to be processed and decoding information of the instruction to be processed; executing a renaming task, renaming the instruction to be processed according to the decoding information, and determining the source physical register number and the destination physical register number of the instruction to be processed; executing a dispatch task, and sending the instruction to be processed to a dispatch queue corresponding to the instruction type of the re-sequencing buffer and the instruction to be processed; reading a source physical register number and a destination physical register number of an instruction to be processed from a register in the next clock cycle, and adding the source physical register number and the destination physical register number into a reorder buffer and dispatch queue; wherein the renaming task and the dispatching task are executed in the same clock cycle. The invention reduces the pipeline depth of the processor.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to an instruction processing method, an apparatus, an electronic device, and a readable storage medium.
Background
In an out-of-order processor architecture, instructions may be sequentially decoded, renamed, dispatched, issued, executed, written back, committed, etc. In the related art, the renaming stage and the dispatch stage are two independent stages, and the instruction renames first and then enters the dispatch stage in the next clock cycle. The separate two stages increase the pipeline depth of the processor and reduce the performance of the processor.
Disclosure of Invention
The embodiment of the invention provides an instruction processing method, an instruction processing device, electronic equipment and a readable storage medium, which can solve the problems that the renaming and the dispatch of instructions are divided into two independent stages in the related technology, the depth of a pipeline of a processor is increased, and the performance of the processor is reduced.
In order to solve the above problems, an embodiment of the present invention discloses an instruction processing method, which includes:
acquiring an instruction to be processed and decoding information of the instruction to be processed;
executing a renaming task, renaming the to-be-processed instruction according to the decoding information, and determining a source physical register number and a destination physical register number of the to-be-processed instruction;
executing a dispatch task, and sending the to-be-processed instruction to a dispatch queue corresponding to a re-sequencing buffer and the instruction type of the to-be-processed instruction;
Storing first information of the to-be-processed instruction in a temporary storage; the first information comprises a source physical register number and a destination physical register number of the to-be-processed instruction;
reading a source physical register number and a destination physical register number of the to-be-processed instruction from the register in the next clock cycle, and adding the source physical register number and the destination physical register number into the re-sequencing buffer and the dispatch queue;
wherein the renaming task and the dispatching task are executed in the same clock cycle.
In another aspect, an embodiment of the present invention discloses an instruction processing apparatus, including:
the data acquisition module is used for acquiring the instruction to be processed and the decoding information of the instruction to be processed;
the renaming module is used for executing a renaming task, renaming the to-be-processed instruction according to the decoding information and determining the source physical register number and the destination physical register number of the to-be-processed instruction;
the dispatch module is used for executing a dispatch task and sending the to-be-processed instruction to a re-sequencing buffer and a dispatch queue corresponding to the instruction type of the to-be-processed instruction;
The storage module is used for storing the first information of the to-be-processed instruction in a temporary storage; the first information comprises a source physical register number and a destination physical register number of the to-be-processed instruction;
a register number adding module, configured to read, from the register, a source physical register number and a destination physical register number of the instruction to be processed in a next clock cycle, and add the source physical register number and the destination physical register number to the reorder buffer and the dispatch queue;
wherein the renaming task and the dispatching task are executed in the same clock cycle.
In still another aspect, the embodiment of the invention also discloses an electronic device, which comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used for storing executable instructions which enable the processor to execute the instruction processing method.
The embodiment of the invention also discloses a readable storage medium, which enables the electronic equipment to execute the instruction processing method when the instructions in the readable storage medium are executed by the processor of the electronic equipment.
The embodiment of the invention has the following advantages:
the embodiment of the invention provides an instruction processing method, which fuses a renaming stage and a dispatching stage in an out-of-order processing architecture, executes renaming tasks and dispatching tasks in the same clock cycle, reduces the depth of a pipeline of a processor and is beneficial to improving the performance of the processor. In addition, the source physical register number and the destination physical register number are added to the reorder buffer and dispatch queue in the next clock cycle, so that the problem that the source physical register number and the destination physical register number cannot enter the reorder buffer and dispatch queue due to too long delay in the renaming process can be avoided, and the long time sequence delay of the processor is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of steps of an embodiment of an instruction processing method of the present invention;
FIG. 2 is a schematic diagram of an instruction processing apparatus according to the present invention;
fig. 3 is a block diagram of an electronic device according to an example of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present invention may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, the term "and/or" as used in the specification and claims to describe an association of associated objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The term "plurality" in embodiments of the present invention means two or more, and other adjectives are similar.
Method embodiment
Referring to fig. 1, there is shown a flowchart of steps of an embodiment of an instruction processing method of the present invention, the method may specifically include the steps of:
step 101, acquiring an instruction to be processed and decoding information of the instruction to be processed;
102, executing a renaming task, renaming the to-be-processed instruction according to the decoding information, and determining a source physical register number and a destination physical register number of the to-be-processed instruction;
step 103, executing a dispatch task, and sending the to-be-processed instruction to a dispatch queue corresponding to a re-sequencing buffer and the instruction type of the to-be-processed instruction;
step 104, storing the first information of the to-be-processed instruction in a temporary storage; the first information comprises a source physical register number and a destination physical register number of the to-be-processed instruction;
step 105, in the next clock cycle, reading the source physical register number and the destination physical register number of the to-be-processed instruction from the temporary memory, and adding the source physical register number and the destination physical register number to the reorder buffer and the dispatch queue.
Wherein the renaming task and the dispatching task are executed in the same clock cycle.
The logical register is a register number encoded in an instruction, and generally has a small number. The physical registers are the actual register files in the processor, typically in large numbers.
The Re-Order Buffer (ROB) functions to sequence the instructions so that the results of normal execution of the program can be preserved. During dispatch, the instruction is allocated an entry of the ROB, and some information to be saved is stored in the ROB, such as rename information of the instruction, instruction type, etc.
The dispatch queue is an instruction queue for receiving and buffering instructions of the dispatch stage to increase the instruction capacity of the processor.
The register management method provided by the embodiment of the invention can be applied to a processor. In an out-of-order processor architecture, instructions may undergo stages of decode, rename, dispatch, issue, execute, write back, commit, etc. in sequence. In the instruction processing method provided by the embodiment of the invention, the renaming stage and the dispatching stage are fused, and the tasks corresponding to the renaming stage and the dispatching stage are processed in the same clock cycle. In the embodiment of the invention, after fusion processing, the instruction is subjected to stages of decoding, renaming, dispatch, transmitting, executing, writing back, submitting and the like in sequence. The renaming and dispatching stage mainly processes two tasks: renaming tasks and dispatching tasks, which are in most cases non-interfering.
The decoding information of the instruction to be processed is information obtained by decoding the instruction to be processed by the processor, and may include, but is not limited to: source logical register number, destination logical register number, whether the source operand type is a register type, whether the instruction writes to a register, instruction type, etc.
The processor manages and maintains the mapping between the logical registers and the physical registers by executing renaming tasks, eliminates dependencies among instructions by renaming the logical registers, and completes out-of-order scheduling. Specifically, the processor uses the source logical register number of the instruction to be processed to query the rename table to obtain the source physical register number to obtain the source operand from the source physical register. At the same time, the free register list is queried, the free physical register number is obtained as the target physical register number, and the table entry corresponding to the target logical register number in the rename table is updated. The renaming table is used for recording the mapping relation between the logical register number and the physical register number. The free physical register list is used for recording free physical registers, and if an instruction needs a new physical register, the number of the free physical register can be obtained from the free physical register list.
It should be noted that, there may be a plurality of renamed instructions in a clock cycle, and there is a sequential relationship between the instructions, so for the instruction that is not the first renamed instruction, the physical register number corresponding to the source logical register number needs to be determined in combination with the physical register number corresponding to the destination logical register number preceding the instruction in the clock cycle.
The processor dispatches the instructions to a dispatch queue corresponding to the re-order buffer and the instruction type by executing the dispatch tasks. It should be noted that, according to instruction types, the dispatch queues can be divided into three types: fixed point dispatch queues, floating point dispatch queues, and memory access dispatch queues.
In the related art, the instruction and the information of the instruction, such as the instruction type, the source physical register number, the destination physical register number, whether to write the register, etc., enter the re-sequencing buffer and the dispatch queue during the dispatch stage. In the embodiment of the invention, the renaming stage and the dispatch stage are fused, when the dispatch task is executed, the instruction and other information of the instruction, such as the instruction type, whether to write a register and the like, can enter the re-sequencing buffer and dispatch queue, and the source physical register number and the destination physical register number of the instruction enter the re-sequencing buffer and dispatch queue again in the next clock cycle.
Specifically, in the embodiment of the present invention, renaming tasks and assigning tasks are performed in the same clock cycle, respectively first: determining a source physical register number and a destination physical register number of an instruction to be processed through renaming; and sending the to-be-processed instruction to a dispatch queue corresponding to the re-sequencing buffer and the instruction type through dispatch. The source physical register number and the destination physical register number of the instruction to be processed are stored in a register, rather than being sent with the instruction to a reorder buffer and dispatch queue. The register is a storage device for temporarily storing a source physical register number and a destination physical register number of an instruction.
In the next clock cycle, the processor reads the source physical register number and the destination physical register number of the to-be-processed instruction from the register, and adds the source physical register number and the destination physical register number to a dispatch queue corresponding to the reorder buffer and the instruction type of the to-be-processed instruction. For example, the processor may add the source physical register number and the destination physical register number of the instruction to be processed to a dispatch queue corresponding to the reorder buffer and the instruction type of the instruction to be processed, according to the instruction identification. The instruction identifier is an instruction unique identity identifier and is used for distinguishing different instructions, for example, the instruction identifier can be an instruction index value.
Thereafter, the instruction enters the issue phase. In the instruction issue phase, the primary module involved is the issue queue. The processor mainly performs operations such as enqueuing, selecting, reading data, dequeuing and the like on the instruction in the transmitting stage, and meanwhile, the transmitting queue also needs to be responsible for operations such as monitoring the writing back of the instruction and waking up the waiting instruction. It will be appreciated that, during the launch phase, the processor reads the source data in the source physical register through the source physical register number of the instruction, so that during the execution phase, the instruction is executed according to the read source data, for example, a fixed point operation, a floating point operation, a memory access operation, etc., and finally the instruction result is written to the location corresponding to the destination physical register number of the instruction.
According to the instruction processing method provided by the embodiment of the invention, the renaming stage and the dispatching stage in the out-of-order processing architecture are fused, and the renaming task and the dispatching task are executed in the same clock cycle, so that the pipeline depth of the processor is reduced, and the performance of the processor is improved. In addition, the source physical register number and the destination physical register number are added to the reorder buffer and dispatch queue in the next clock cycle, so that the problem that the source physical register number and the destination physical register number cannot enter the reorder buffer and dispatch queue due to too long delay in the renaming process can be avoided, and the long time sequence delay of the processor is reduced.
In an alternative embodiment of the invention, the method further comprises:
step S11, obtaining a dequeue instruction in the dispatch queue;
step S12, if the dequeue instruction is an enqueue instruction in the last clock period of the dispatch queue, acquiring a source physical register number and a destination physical register number of the dequeue instruction from the temporary register;
step S13, if the dequeue instruction is not the enqueue instruction in the last clock period of the dispatch queue, acquiring a source physical register number and a destination physical register number of the dequeue instruction from the dispatch queue;
and step S14, the dequeue instruction, the source physical register number and the destination physical register number are sent to a transmission queue.
An instruction may dequeue immediately on the next clock cycle into the dispatch queue, at which point the source physical register number and destination physical register number of the instruction in the dispatch queue are invalid (or empty). Because in the embodiment of the invention, after the processor sends the to-be-processed instruction to the dispatch queue corresponding to the instruction type of the to-be-processed instruction, the source physical register number and the destination physical register number of the to-be-processed instruction are added to the reorder buffer and the dispatch queue in the next clock cycle.
Therefore, in the embodiment of the present invention, the dequeue instruction in the dispatch queue is determined, and whether the dequeue instruction is dequeued immediately is determined. Specifically, if the dequeued instruction in the dispatch queue is an enqueue instruction in the last clock cycle of the dispatch queue, it can be determined that the dequeued instruction belongs to an immediate dequeue, and then the source physical register number and the destination physical register number of the dequeued instruction are directly obtained from the temporary memory. If the dequeued instruction in the dispatch queue is not an enqueue instruction in the last clock cycle of the dispatch queue, the dequeued instruction can be determined not to belong to the immediate dequeued condition, and the source physical register number and the destination physical register number of the instruction in the dispatch queue are valid at this time, and the source physical register number and the destination physical register number of the dequeued instruction can be directly obtained from the dispatch queue. The dequeue instruction, the source physical register number and the destination physical register number of the dequeue instruction, which enters the transmit phase, is then sent to the transmit queue.
According to the embodiment of the invention, the dequeue instruction in the dispatch queue is judged, and the source physical register number and the destination physical register number are acquired from the temporary storage aiming at the immediate dequeue instruction, so that the effectiveness of the source physical register number and the destination physical register number sent to the emission queue is ensured.
In an alternative embodiment of the invention, the method further comprises:
step S21, if the dequeue instruction is an enqueue instruction in the last clock cycle of the dispatch queue, reading an entry corresponding to the dequeue instruction in a score board in the next clock cycle;
step S22, in the transmitting stage, if the scoreboard indicates that the data in the physical register of the dequeue instruction is already in place, the data is read from the physical register.
Wherein, the score board is used for recording whether the data in the physical register is in place.
When an instruction enqueues from a dispatch queue, the processor needs to access the scoreboard to set the entries of the corresponding physical registers (including the source physical register and the destination physical register) to an unseated state. In the embodiment of the present invention, since the physical register number will reenter the dispatch queue at the next clock cycle of the instruction entering the dispatch queue, in the embodiment of the present invention, the processor will update the scoreboard according to the physical register number at the next clock cycle of the instruction entering the dispatch queue, and set the entry corresponding to the physical register number to an unseated state. For example, the value of the entry of the corresponding physical register is set to a first preset value that is used to indicate that the data in the physical register is not in place. The first preset value may be "1", "0" or other values. When the value of an entry of a physical register in the scoreboard is a second preset value, the second preset value may be any value other than the first preset value, indicating that the data in the physical register is already in place.
When an instruction dequeues from the dispatch queue, the scoreboard needs to be read to determine if the data in the physical register is in place.
In an embodiment of the present invention, if the dequeued instruction in the dispatch queue is an immediate dequeued condition, the enqueued instruction that has just entered the dispatch queue in the last clock cycle needs to be considered. Specifically, if the dequeued instruction of the dispatch queue is an enqueue instruction of the dispatch queue in the last clock cycle, that is, if the dequeued instruction is an immediate dequeued instruction, then the entry corresponding to the dequeued instruction in the scoreboard is read again in the next clock cycle.
During the issue phase, if the scoreboard indicates that the data in the physical register of the instruction is already in place, the data may be read from the physical register. Illustratively, the processor reads source data in the source physical register by the source physical register number of the instruction, reads target data in the target register by the target physical register number, so that in the execution phase, the instruction is executed according to the read source data and target data, for example, a fixed point operation, a floating point operation, a memory operation, etc.
Optionally, the first information further includes a first parameter and an address of the to-be-processed instruction in the dispatch queue, where the first parameter is used to indicate whether the instruction is valid; the method further comprises the steps of:
Step S31, obtaining first information of enqueuing instructions of the dispatch queue in the last clock period from the temporary storage;
step S32, comparing the address of the enqueuing instruction in the dispatch queue with the address of the dequeuing instruction in the dispatch queue under the condition that the first parameter of the enqueuing instruction indicates that the enqueuing instruction is valid;
step S33, determining that the enqueuing instruction is the enqueuing instruction in the last clock cycle of the dispatch queue when the address of the enqueuing instruction in the dispatch queue is the same as the address of the dequeue instruction in the dispatch queue.
The first information recorded in the register may include, in addition to a source physical register number and a destination physical register number of the instruction, a first parameter of the instruction, and an address of the instruction in the dispatch queue, where the first parameter is used to indicate whether the instruction is valid. For example, when the value of the first parameter is a third preset value, the instruction is indicated as a valid instruction, and the third preset value may be "1" or "0" or other values. When the value of the first parameter is a fourth preset value, the instruction is indicated to be an invalid instruction, and the fourth preset value can be any value except the third preset value. It will be appreciated that if the first parameter of an instruction in the register indicates that the instruction is an invalid instruction, it may be determined that the register entry of the instruction in the register is invalid, i.e. the first information of the instruction recorded in the register is invalid.
In an embodiment of the present invention, whether the dequeued instruction is immediately dequeued may be determined by comparing whether the address of the dequeued instruction in the dispatch queue is the same as the address of the enqueued instruction in the last clock cycle in the dispatch queue.
Specifically, first information of each enqueued instruction in the last clock cycle of the dispatch queue is obtained from the register, and whether each enqueued instruction is a valid instruction is judged according to the first parameter. For a valid enqueue instruction, a further comparison is made as to whether the address of the enqueue instruction in the dispatch queue is the same as the address of the dequeue instruction in the dispatch queue. If the dequeued instruction in the dispatch queue is the same address as any valid enqueue instruction in the last clock cycle of the dispatch queue, then it may be determined that the dequeued instruction is an enqueue instruction in the last clock cycle of the dispatch queue, i.e., the dequeued instruction is in the immediate dequeue.
For example, assume that the enqueued instruction in the last clock cycle of the dispatch queue has instructions A1, A2, and A3. And determining that the instructions A1 to A3 are valid instructions according to the first parameters of each enqueuing instruction. The address of the enqueuing instruction A1 in the dispatch queue is adr1, the address of the enqueuing instruction A2 in the dispatch queue is adr2, and the address of the enqueuing instruction A3 in the dispatch queue is adr3. At the current clock cycle, there is a dequeue instruction B in the dispatch queue, which addresses adr2. Obviously, dequeue instruction B is the same address as enqueue instruction A2 in the dispatch queue, so it can be determined that dequeue instruction B is an enqueue instruction for the dispatch queue in the last clock cycle, i.e., dequeue instruction B is immediately dequeued.
Optionally, the method further comprises:
step S41, determining that the enqueuing instruction is not the enqueuing instruction in the last clock period of the dispatch queue under the condition that the first parameter of the enqueuing instruction indicates that the enqueuing instruction is invalid; or,
step S42, determining that the enqueuing instruction is not the enqueuing instruction in the last clock cycle of the dispatch queue if the address of the enqueuing instruction in the dispatch queue is not the same as the address of the dequeue instruction in the dispatch queue.
In the embodiment of the present invention, if the first parameter of the enqueuing instruction in the last clock cycle of the dispatch queue indicates that the enqueuing instruction is invalid, or the address of the dequeue instruction in the dispatch queue is different from the addresses of all enqueuing instructions in the last clock cycle of the dispatch queue, it may be determined that the dequeue instruction is not the enqueuing instruction in the last clock cycle of the dispatch queue, that is, the dequeue instruction does not belong to the immediate dequeue case.
In an alternative embodiment of the present invention, the first information further includes an address of the pending instruction in the reorder buffer, and an address of the pending instruction in the dispatch queue. Step 105, in the next clock cycle, reads the source physical register number and the destination physical register number of the pending instruction from the register, and adds the source physical register number and the destination physical register number to the reorder buffer and the dispatch queue, including:
Step S51, reading first information of the to-be-processed instruction from the temporary storage in the next clock period;
step S52, adding the source physical register number and the destination physical register number of the to-be-processed instruction into the re-sequencing buffer according to the address of the to-be-processed instruction in the re-sequencing buffer;
step S53, adding the source physical register number and the destination physical register number of the to-be-processed instruction to the dispatch queue according to the address of the to-be-processed instruction in the dispatch queue.
In the embodiment of the present invention, the first information recorded in the register may include, in addition to the source physical register number and the destination physical register number of the instruction, an address of the instruction in the reorder buffer, and an address of the instruction in the dispatch queue.
The processor may read the first information of the pending instruction from the register a next clock cycle after execution of the rename task and the dispatch task, and then add the source physical register number and the destination physical register number to the reorder buffer and the dispatch queue in response to the address of the pending instruction in the reorder buffer and the address of the pending instruction in the dispatch queue.
In an alternative embodiment of the present invention, the decoding information includes a source logical register number, a destination logical register number, a second parameter, a third parameter, and an instruction type; the second parameter is used for indicating whether the source operand type of the to-be-processed instruction is a register type; the third parameter is used for indicating whether the pending instruction writes a register.
Step 102 of executing a renaming task, renaming the to-be-processed instruction according to the decoding information, determining a source physical register number and a destination physical register number of the to-be-processed instruction, including:
step S61, inquiring a renaming table according to the source logic register number to determine a source physical register number corresponding to the source logic register number when the second parameter indicates that the source operand type of the instruction to be processed is a register type;
step S62, when the third parameter indicates that the to-be-processed instruction needs to write a register, determining a destination physical register number corresponding to the destination logical register number according to the idle register list, and updating an entry corresponding to the destination logical register number in the rename table according to the destination physical register number.
The renaming task is used for managing and maintaining mapping between the logic register and the physical register, and through renaming the logic register, eliminating dependence among instructions is achieved, and out-of-order scheduling is completed.
If the second parameter in the decoding information of the instruction to be processed indicates that the source operand type of the instruction to be processed is a register type, the processor is required to query the renaming table according to the source logic register number in the decoding information, and determine the source physical register number corresponding to the source logic register. If the third parameter in the decoding information indicates that the to-be-processed instruction needs to write the logic register, the processor is required to access the idle register list, acquire the idle physical register number, determine the idle physical register number as the destination physical register number of the to-be-processed instruction, and update the entry corresponding to the destination logic register number of the to-be-processed instruction in the renaming table.
It should be noted that, there may be a plurality of renamed instructions in a clock cycle, and there is a sequential relationship between the instructions, so for the instruction that is not the first renamed instruction, the physical register number corresponding to the source logical register number needs to be determined in combination with the physical register number corresponding to the destination logical register number preceding the instruction in the clock cycle.
In summary, the embodiment of the invention provides an instruction processing method, which fuses a renaming stage and a dispatch stage in an out-of-order processing architecture, executes renaming tasks and dispatch tasks in the same clock cycle, reduces the depth of a pipeline of a processor, and is beneficial to improving the performance of the processor. In addition, the source physical register number and the destination physical register number are added to the reorder buffer and dispatch queue in the next clock cycle, so that the problem that the source physical register number and the destination physical register number cannot enter the reorder buffer and dispatch queue due to too long delay in the renaming process can be avoided, and the long time sequence delay of the processor is reduced.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
Device embodiment
Referring to fig. 2, there is shown a block diagram of an instruction processing apparatus of the present invention, which may specifically include:
a data acquisition module 201, configured to acquire an instruction to be processed and decoding information of the instruction to be processed;
a renaming module 202, configured to execute a renaming task, rename the to-be-processed instruction according to the decoding information, and determine a source physical register number and a destination physical register number of the to-be-processed instruction;
the dispatch module 203 is configured to execute a dispatch task, and send the instruction to be processed to a dispatch queue corresponding to a resequencing buffer and an instruction type of the instruction to be processed;
a storage module 204, configured to store first information of the instruction to be processed in a register; the first information comprises a source physical register number and a destination physical register number of the to-be-processed instruction;
a register number adding module 205, configured to read, from the register, a source physical register number and a destination physical register number of the instruction to be processed in a next clock cycle, and add the source physical register number and the destination physical register number to the reorder buffer and the dispatch queue;
Wherein the renaming task and the dispatching task are executed in the same clock cycle.
Optionally, the apparatus further comprises:
a dequeue instruction acquisition module for acquiring dequeue instructions in the dispatch queue;
the first obtaining module is used for obtaining a source physical register number and a destination physical register number of the dequeue instruction from the temporary storage if the dequeue instruction is an enqueue instruction in the last clock cycle of the dispatch queue;
the second obtaining module is used for obtaining a source physical register number and a destination physical register number of the dequeue instruction from the dispatch queue if the dequeue instruction is not the enqueue instruction in the last clock cycle of the dispatch queue;
and the sending module is used for sending the dequeue instruction, the source physical register number and the destination physical register number to a transmission queue.
Optionally, the apparatus further comprises:
the scoring board reading module is used for reading an entry corresponding to the dequeuing instruction in the scoring board in the next clock cycle if the dequeuing instruction is the enqueuing instruction in the last clock cycle of the dispatch queue; the score board is used for recording whether the data in the physical register are in place or not;
And the data reading module is used for reading the data from the physical register of the dequeue instruction if the scoreboard indicates that the data is in place in the physical register in the transmitting stage.
Optionally, the first information further includes a first parameter and an address of the to-be-processed instruction in the dispatch queue, where the first parameter is used to indicate whether the instruction is valid; the apparatus further comprises:
the first information acquisition module is used for acquiring first information of an enqueuing instruction of the dispatch queue in the last clock period from the temporary storage;
an address comparison module for comparing an address of the enqueue instruction in the dispatch queue with an address of the dequeue instruction in the dispatch queue if a first parameter of the enqueue instruction indicates that the enqueue instruction is valid;
and the first determining module is used for determining that the enqueuing instruction is the enqueuing instruction in the last clock cycle of the dispatch queue under the condition that the address of the enqueuing instruction in the dispatch queue is the same as the address of the dequeue instruction in the dispatch queue.
Optionally, the apparatus further comprises:
a second determining module, configured to determine that the enqueue instruction is not an enqueue instruction in a last clock cycle of the dispatch queue if the first parameter of the enqueue instruction indicates that the enqueue instruction is invalid; or,
And a third determining module, configured to determine that the enqueuing instruction is not an enqueuing instruction in a last clock cycle of the dispatch queue if the address of the enqueuing instruction in the dispatch queue is different from the address of the dequeue instruction in the dispatch queue.
Optionally, the first information further includes an address of the to-be-processed instruction in the reorder buffer, and an address of the to-be-processed instruction in the dispatch queue; the register number adding module includes:
the information reading sub-module is used for reading the first information of the to-be-processed instruction from the temporary storage in the next clock period;
a first adding sub-module, configured to add a source physical register number and a destination physical register number of the to-be-processed instruction to the reorder buffer according to an address of the to-be-processed instruction in the reorder buffer;
and the second adding submodule is used for adding the source physical register number and the destination physical register number of the to-be-processed instruction into the dispatch queue according to the address of the to-be-processed instruction in the dispatch queue.
Optionally, the decoding information includes a source logical register number, a destination logical register number, a second parameter, a third parameter, and an instruction type; the second parameter is used for indicating whether the source operand type of the to-be-processed instruction is a register type; the third parameter is used for indicating whether the to-be-processed instruction writes into a register; the renaming module comprises:
A source physical register determining submodule, configured to query a rename table according to the source logical register number to determine a source physical register number corresponding to the source logical register number when the second parameter indicates that the source operand type of the instruction to be processed is a register type;
and the destination physical register determining submodule is used for determining a destination physical register number corresponding to the destination logical register number according to the idle register list and updating an entry corresponding to the destination logical register number in the renaming table according to the destination physical register number under the condition that the third parameter indicates that the to-be-processed instruction needs to write a register.
The embodiment of the invention provides an instruction processing device, which fuses a renaming stage and a dispatching stage in an out-of-order processing architecture, executes renaming tasks and dispatching tasks in the same clock cycle, reduces the depth of a pipeline of a processor and is beneficial to improving the performance of the processor. In addition, the source physical register number and the destination physical register number are added to the reorder buffer and dispatch queue in the next clock cycle, so that the problem that the source physical register number and the destination physical register number cannot enter the reorder buffer and dispatch queue due to too long delay in the renaming process can be avoided, and the long time sequence delay of the processor is reduced.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The specific manner in which the various modules perform the operations in relation to the processor of the above-described embodiments have been described in detail in relation to the embodiments of the method and will not be described in detail herein.
Referring to fig. 3, a block diagram of an electronic device for instruction processing according to an embodiment of the present invention is provided. As shown in fig. 3, the electronic device includes: the device comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used for storing executable instructions that cause the processor to execute the instruction processing method of the foregoing embodiment.
The processor may be a CPU (Central Processing Unit ), general purpose processor, DSP (Digital Signal Processor ), ASIC (Application Specific Integrated Circuit, application specific integrated circuit), FPGA (Field Programmble Gate Array, field programmable gate array) or other editable device, transistor logic device, hardware components, or any combination thereof. The processor may also be a combination that performs the function of a computation, e.g., a combination comprising one or more microprocessors, a combination of a DSP and a microprocessor, etc.
The communication bus may include a path to transfer information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect, peripheral component interconnect standard) bus or an EISA (Extended Industry Standard Architecture ) bus, or the like. The communication bus may be classified into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one line is shown in fig. 3, but not only one bus or one type of bus.
The memory may be a ROM (Read Only memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only, electrically erasable programmable Read Only memory), a CD-ROM (Compact Disa Read Only, compact disc Read Only), a magnetic tape, a floppy disk, an optical data storage device, and the like.
Embodiments of the present invention also provide a non-transitory computer-readable storage medium, which when executed by a processor of an electronic device (server or terminal), enables the processor to perform the instruction processing method shown in fig. 1.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The foregoing has described in detail the methods, apparatuses, electronic devices and readable storage medium for processing instructions provided by the present invention, and specific examples have been applied to illustrate the principles and embodiments of the present invention, and the above examples are only used to help understand the methods and core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (15)
1. A method of instruction processing, the method comprising:
acquiring an instruction to be processed and decoding information of the instruction to be processed;
executing a renaming task, renaming the to-be-processed instruction according to the decoding information, and determining a source physical register number and a destination physical register number of the to-be-processed instruction;
executing a dispatch task, and sending the to-be-processed instruction to a dispatch queue corresponding to a re-sequencing buffer and the instruction type of the to-be-processed instruction;
storing first information of the to-be-processed instruction in a temporary storage; the first information comprises a source physical register number and a destination physical register number of the to-be-processed instruction;
reading a source physical register number and a destination physical register number of the to-be-processed instruction from the register in the next clock cycle, and adding the source physical register number and the destination physical register number into the re-sequencing buffer and the dispatch queue;
wherein the renaming task and the dispatching task are executed in the same clock cycle.
2. The method according to claim 1, wherein the method further comprises:
Obtaining dequeue instructions in the dispatch queue;
if the dequeue instruction is an enqueue instruction in the last clock cycle of the dispatch queue, acquiring a source physical register number and a destination physical register number of the dequeue instruction from the register;
if the dequeue instruction is not the enqueue instruction in the last clock cycle of the dispatch queue, acquiring a source physical register number and a destination physical register number of the dequeue instruction from the dispatch queue;
and sending the dequeue instruction, the source physical register number and the destination physical register number to a transmission queue.
3. The method according to claim 2, wherein the method further comprises:
if the dequeue instruction is an enqueue instruction in the last clock cycle of the dispatch queue, reading an entry corresponding to the dequeue instruction in a score board in the next clock cycle; the score board is used for recording whether the data in the physical register are in place or not;
in the transmit phase, if the scoreboard indicates that the data in the physical register of the dequeue instruction is already in place, the data is read from the physical register.
4. The method of claim 2, wherein the first information further comprises a first parameter and an address of the pending instruction in the dispatch queue, the first parameter indicating whether the instruction is valid; the method further comprises the steps of:
obtaining first information of enqueuing instructions in the last clock cycle of the dispatch queue from the register;
comparing an address of the enqueue instruction in the dispatch queue with an address of the dequeue instruction in the dispatch queue if a first parameter of the enqueue instruction indicates that the enqueue instruction is valid;
and determining that the enqueuing instruction is the enqueuing instruction in the last clock cycle of the dispatch queue under the condition that the address of the enqueuing instruction in the dispatch queue is the same as the address of the dequeue instruction in the dispatch queue.
5. The method according to claim 4, wherein the method further comprises:
determining that the enqueue instruction is not an enqueue instruction within a last clock cycle of the dispatch queue if a first parameter of the enqueue instruction indicates that the enqueue instruction is invalid; or,
In the event that the address of the enqueue instruction in the dispatch queue is not the same as the address of the dequeue instruction in the dispatch queue, determining that the dequeue instruction is not an enqueue instruction in the last clock cycle of the dispatch queue.
6. The method of claim 1, wherein the first information further comprises an address of the pending instruction in the reorder buffer and an address of the pending instruction in the dispatch queue;
the reading the source physical register number and the destination physical register number of the to-be-processed instruction from the temporary memory and adding the source physical register number and the destination physical register number to the reorder buffer and the dispatch queue in the next clock cycle includes:
reading first information of the to-be-processed instruction from the register in the next clock cycle;
adding a source physical register number and a destination physical register number of the to-be-processed instruction into the re-sequencing buffer according to the address of the to-be-processed instruction in the re-sequencing buffer;
and adding the source physical register number and the destination physical register number of the to-be-processed instruction into the dispatch queue according to the address of the to-be-processed instruction in the dispatch queue.
7. The method of claim 1, wherein the decode information comprises a source logical register number, a destination logical register number, a second parameter, a third parameter, and an instruction type; the second parameter is used for indicating whether the source operand type of the to-be-processed instruction is a register type; the third parameter is used for indicating whether the to-be-processed instruction writes into a register;
the renaming task is executed, renaming processing is carried out on the to-be-processed instruction according to the decoding information, and the source physical register number and the destination physical register number of the to-be-processed instruction are determined, including:
querying a rename table according to the source logic register number under the condition that the second parameter indicates that the source operand type of the to-be-processed instruction is a register type, so as to determine a source physical register number corresponding to the source logic register number;
and under the condition that the third parameter indicates that the to-be-processed instruction needs to write a register, determining a destination physical register number corresponding to the destination logical register number according to an idle register list, and updating an entry corresponding to the destination logical register number in the renaming table according to the destination physical register number.
8. An instruction processing apparatus, the apparatus comprising:
the data acquisition module is used for acquiring the instruction to be processed and the decoding information of the instruction to be processed;
the renaming module is used for executing a renaming task, renaming the to-be-processed instruction according to the decoding information and determining the source physical register number and the destination physical register number of the to-be-processed instruction;
the dispatch module is used for executing a dispatch task and sending the to-be-processed instruction to a re-sequencing buffer and a dispatch queue corresponding to the instruction type of the to-be-processed instruction;
the storage module is used for storing the first information of the to-be-processed instruction in a temporary storage; the first information comprises a source physical register number and a destination physical register number of the to-be-processed instruction;
a register number adding module, configured to read, from the register, a source physical register number and a destination physical register number of the instruction to be processed in a next clock cycle, and add the source physical register number and the destination physical register number to the reorder buffer and the dispatch queue;
wherein the renaming task and the dispatching task are executed in the same clock cycle.
9. The apparatus of claim 8, wherein the apparatus further comprises:
a dequeue instruction acquisition module for acquiring dequeue instructions in the dispatch queue;
the first obtaining module is used for obtaining a source physical register number and a destination physical register number of the dequeue instruction from the temporary storage if the dequeue instruction is an enqueue instruction in the last clock cycle of the dispatch queue;
the second obtaining module is used for obtaining a source physical register number and a destination physical register number of the dequeue instruction from the dispatch queue if the dequeue instruction is not the enqueue instruction in the last clock cycle of the dispatch queue;
and the sending module is used for sending the dequeue instruction, the source physical register number and the destination physical register number to a transmission queue.
10. The apparatus of claim 9, wherein the apparatus further comprises:
the scoring board reading module is used for reading an entry corresponding to the dequeuing instruction in the scoring board in the next clock cycle if the dequeuing instruction is the enqueuing instruction in the last clock cycle of the dispatch queue; the score board is used for recording whether the data in the physical register are in place or not;
And the data reading module is used for reading the data from the physical register of the dequeue instruction if the scoreboard indicates that the data is in place in the physical register in the transmitting stage.
11. The apparatus of claim 9, wherein the first information further comprises a first parameter and an address of the pending instruction in the dispatch queue, the first parameter being used to indicate whether an instruction is valid; the apparatus further comprises:
the first information acquisition module is used for acquiring first information of an enqueuing instruction of the dispatch queue in the last clock period from the temporary storage;
an address comparison module for comparing an address of the enqueue instruction in the dispatch queue with an address of the dequeue instruction in the dispatch queue if a first parameter of the enqueue instruction indicates that the enqueue instruction is valid;
and the first determining module is used for determining that the enqueuing instruction is the enqueuing instruction in the last clock cycle of the dispatch queue under the condition that the address of the enqueuing instruction in the dispatch queue is the same as the address of the dequeue instruction in the dispatch queue.
12. The apparatus of claim 11, wherein the apparatus further comprises:
A second determining module, configured to determine that the enqueue instruction is not an enqueue instruction in a last clock cycle of the dispatch queue if the first parameter of the enqueue instruction indicates that the enqueue instruction is invalid; or,
and a third determining module, configured to determine that the enqueuing instruction is not an enqueuing instruction in a last clock cycle of the dispatch queue if the address of the enqueuing instruction in the dispatch queue is different from the address of the dequeue instruction in the dispatch queue.
13. The apparatus of claim 8, wherein the first information further comprises an address of the pending instruction in the reorder buffer and an address of the pending instruction in the dispatch queue; the register number adding module includes:
the information reading sub-module is used for reading the first information of the to-be-processed instruction from the temporary storage in the next clock period;
a first adding sub-module, configured to add a source physical register number and a destination physical register number of the to-be-processed instruction to the reorder buffer according to an address of the to-be-processed instruction in the reorder buffer;
And the second adding submodule is used for adding the source physical register number and the destination physical register number of the to-be-processed instruction into the dispatch queue according to the address of the to-be-processed instruction in the dispatch queue.
14. An electronic device, comprising a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; the memory is configured to store executable instructions that cause the processor to perform the instruction processing method according to any one of claims 1 to 7.
15. A readable storage medium, wherein instructions in the readable storage medium, when executed by a processor of an electronic device, enable the processor to perform the instruction processing method of any one of claims 1 to 7.
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