CN116112627B - Method and circuit for video frame rate self-adaptive transformation - Google Patents
Method and circuit for video frame rate self-adaptive transformation Download PDFInfo
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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Abstract
The invention discloses a video frame rate self-adaptive conversion method and circuit, which comprises an input frame rate counter, an input latch controller, a pre-processing unit, a frame buffer, a post-processing unit and an output control unit, wherein the output end of the input frame rate counter is connected with the input latch controller, and video image data streams are respectively sent to the input frame rate counter and the input latch controller. When the whole circuit is used, the output frame rate is configured according to the output end, and the system calculates the frame rate of the output video image and automatically adapts through the internal circuit; the problems of tearing effect, DSC decoding error and the like occurring in the process of caching other single frames are effectively solved while only one frame of image is cached; only the output frame rate is required to be configured, and the input frame rate of the input image with the input frame rate within a certain proportion range can be adjusted to the configured output frame rate for output; has the advantages of reducing hardware resource overhead and simplifying system software configuration.
Description
Technical Field
The invention belongs to the technical field of video images, and particularly relates to a method and a circuit for video frame rate self-adaptive transformation.
Background
In many application scenarios, because of the limitation of the bandwidth of the receiving end, the frame rate of the video image source end is different from the display (or processing) frame rate of the receiving end, and the frame dropping process needs to be performed at the receiving end. Such as a computer output image switching display, a game machine output image switching television, a mobile phone output image switching projector, etc.
For video images transmitted through the MIPI interface, there are mainly 4 existing frame dropping modes:
1. a common single-frame buffer frame dropping mode;
TE frame dropping mode;
3. a double-frame buffer frame dropping mode;
4. and a multi-frame processing frame dropping mode.
The following are introduced respectively:
1. common single-frame buffer frame dropping mode: the transmitting end transmits according to the frame rate of the transmitting end, the receiving end processes according to the frame rate of the receiving end, and no feedback or other interactive signals exist between the transmitting end and the receiving end except for video image data. The image receiving end only has a buffer area of one frame of image, the image is written into the buffer, and the image is read from the buffer. The method has the following defects:
(1) Because the input and output frame rates are inconsistent, when the read pointer of the image buffer memory catches up with the write pointer, or the write pointer catches up with the read pointer, a tearing effect can occur;
(2) For a DSC video image data stream transmitted by MIPI, since DSC is compressed and decompressed according to Slice of horizontal pixel×vertical pixel size, when read-write pointers are interleaved, a DSC decompression error occurs, resulting in processing (or display) abnormality.
Te de-framing mode: for images transmitted in MIPI Command mode, the frames may be dropped by TE. As shown in fig. 1, the image receiving end generates a pulse TE signal with the same frame rate period according to its own processing frame rate, and feeds back the signal to the image transmitting end. The image transmitting end transmits a frame of image after each acquisition of TE signal pulse edges. In this way, the system frame rate is reduced.
The method has the following defects:
(1) The TE frame dropping mode can only be aimed at the MIPI Command mode, but can not be used for the image transmitted in the MIPI Video mode;
(2) For mobile phones, if the TE mode is used strongly, because of the storage processing mechanism inside the mobile phone, when the mobile phone works in a high-swipe state, the mobile phone is stuck rather than in a normal state, especially when running a game App with a higher requirement on the image refresh rate, the stuck phenomenon is more obvious.
3. Double-frame buffer frame dropping mode: two image data frames are stored at the image receiving end, namely a buffer space A and a buffer space B. As shown in fig. 2, the receiving end alternately reads image data from the two buffer spaces and performs subsequent processing. Meanwhile, when the receiving end receives the video image from the transmitting end, the receiving end judges that the block of buffer space is currently being read, and then stores the whole frame of image into another block of buffer space.
The disadvantage of this approach is that 2 buffer spaces are required and the hardware resource consumption is large.
4. Frame processing frame dropping mode: at the image receiving end, a plurality of image data frames are stored and processed by an inter-frame processing algorithm.
The method has the following defects:
(1) The algorithm is complex;
(2) The consumption of hardware resources is large.
Therefore, it is necessary to invent a method and circuit for video frame rate adaptive conversion to solve the above problems.
Disclosure of Invention
In view of the above, the present invention provides a method and a circuit for adaptive video frame rate conversion, so as to solve the problems set forth in the background art.
In order to achieve the above purpose, the present invention provides the following technical solutions: the video frame rate self-adaptive conversion circuit comprises an input frame rate counter, an input latch controller, a pre-processing unit, a frame buffer, a post-processing unit and an output control unit, wherein the output end of the input frame rate counter is connected with the input latch controller, video image data streams are respectively sent to the input frame rate counter and the input latch controller, the output end of the input latch controller is connected with the input end of the pre-processing unit, the output end of the pre-processing unit is connected with the input end of the frame buffer, the output end of the frame buffer is connected with the input end of the post-processing unit, and the output control unit respectively transmits transmission signals to the input latch controller, the frame buffer and the post-processing unit according to the frame rate of a CPU.
Further, the input frame rate counter is responsible for detecting the frame rate of the currently received video image data stream, without any processing of the image data stream, and passing the detected input frame rate of the image data stream to the input latch controller.
Further, the input latch controller receives the input frame rate count information from the input frame rate counter and the video image data stream.
Further, the pre-processing unit receives the video image data stream transmitted from the input latch controller, performs necessary input processing on the video image data stream, including but not limited to scaling, denoising, white balancing, filtering, interpolation, and outputs the processed image data stream to the next stage, and frame buffering.
Further, the frame buffer stores the video image data stream sent from the pre-processing unit, and outputs the buffered video image data stream to the post-processing unit according to the transmission signal of the output control unit.
Further, the output control unit generates an output time sequence according to the frame rate and the line/field information configured by the CPU, and simultaneously generates a read enabling signal to be sent to a frame buffer, so that the frame buffer reads out video image data stream to a post-processing unit according to the read enabling signal; the output control unit also transmits the current output timing to the input latch controller in real time, and the input latch controller judges whether to lock or not through the output timing.
Further, the post-processing unit reads the video image data stream from the frame buffer according to the output timing provided by the output control unit, performs necessary output processing on the output video image data stream, and outputs the video image data stream.
The invention also provides a video frame rate self-adaptive transformation method, which comprises the following steps:
s1, a CPU configures the output frame rate of a system, and simultaneously configures the output resolution and row/field information, and an output control unit transmits the output frame rate to an input latch controller;
s2, the output control unit outputs an enabling signal to the frame buffer memory to start inputting the image data stream;
s3, counting the frame rate of the image data stream by an input frame rate counter, and calculating the current input frame rate according to the input field synchronous signals of two continuous frames; the larger the field synchronous signal interval time of two continuous frames is, the lower the frame rate is, otherwise, the higher the frame rate is; transmitting the image data stream with the input frame rate to an input latch controller, wherein the input latch controller calculates that the input-output frame rate ratio is 80:60, and the input-output frame rate ratio is less than 3:2;
s4, each time the field synchronizing signal of the input frame reaches the input latch controller, the input latch controller reads the current output field count Vcnt from the output control unit;
s5, if the output field count Vcnt in S4 is larger than V/2, the input latch controller locks the current input frame, and the whole frame of video image data stream is not released to the pre-processing unit; when the output field count Vcnt is V, the output field count Vcnt is cleared;
s6, if the output field count Vcnt in the step S4 is smaller than or equal to V/2, the input latch controller releases the whole frame of video image data stream of the current input frame to the pre-processing unit;
s7, repeatedly executing the steps S4 to S7.
Further, the method comprises the following steps:
a. the CPU configures the system output frame rate, and simultaneously configures the output resolution and the row/field information, and the output control unit transmits the output frame rate to the input latch controller;
b. the output control unit outputs an enabling signal to the frame buffer to start inputting the image data stream;
c. the input frame rate counter counts the frame rate of the image data stream, and calculates the current input frame rate according to the input field synchronous signals of two continuous frames; the larger the field synchronous signal interval time of two continuous frames is, the lower the frame rate is, otherwise, the higher the frame rate is; transmitting the image data stream with the input frame rate to an input latch controller, wherein the input latch controller calculates that the input-output frame rate ratio is 100:60, and the input-output frame rate ratio is between 3:2 and 2:1;
d. each time a field synchronizing signal of an input frame reaches an input latch controller, the input latch controller reads a current output field count Vcnt from an output control unit;
f. if the output field count Vcnt in d is larger than V/2, the input latch controller releases the whole frame of video image data stream of the current input frame to the pre-processing unit; when the output field count Vcnt is V, the output field count Vcnt is cleared;
j. if the output field count Vcnt in the step d is smaller than or equal to V/2, the input latch controller locks the current input frame, and the whole frame of video image data stream is not released to the pre-processing unit;
k. and repeatedly executing the steps d to k.
Further, the method comprises the following steps:
(1) The CPU configures the system output frame rate, and simultaneously configures the output resolution and the row/field information, and the output control unit transmits the output frame rate to the input latch controller;
(2) The output control unit outputs an enabling signal to the frame buffer to start inputting the image data stream;
(3) The input frame rate counter counts the frame rate of the image data stream, and calculates the current input frame rate according to the input field synchronous signals of two continuous frames; the larger the field synchronous signal interval time of two continuous frames is, the lower the frame rate is, otherwise, the higher the frame rate is; transmitting the image data stream with the input frame rate to an input latch controller, wherein the input latch controller calculates that the input/output frame rate ratio is 144:60, and the input/output frame rate ratio is more than 2:1;
(4) Each time a field synchronizing signal of an input frame reaches an input latch controller, the input latch controller reads a current output field count Vcnt from an output control unit;
(5) If the output field count Vcnt in the step (4) is larger than (X-Y) V/X, the input latch controller locks the current input frame, and the whole frame of video image data stream is not released to the pre-processing unit; when the output field count Vcnt is V, the output field count Vcnt is cleared; wherein, the input image resolution is X, and the output image resolution is Y;
(6) If the output field count Vcnt in (4) is less than or equal to (X-Y) V/X, the input latch controller releases the whole frame video image data stream of the current input frame into the pre-processing unit;
(7) Repeating steps (4) to (7).
The invention has the technical effects and advantages that:
1. when the whole circuit is used, the output frame rate is configured according to the output end, and the system calculates the frame rate of the output video image and automatically adapts through the internal circuit; the problems of tearing effect, DSC decoding error and the like occurring in the process of caching other single frames are effectively solved while only one frame of image is cached; only the output frame rate is required to be configured, and the input frame rate of the input image with the input frame rate within a certain proportion range can be adjusted to the configured output frame rate for output; has the advantages of reducing hardware resource overhead and simplifying system software configuration.
2. The video frame rate self-adaptive conversion circuit provided by the invention can be integrated in a chip supporting video image switching, so that the video frame rate self-adaptive conversion circuit has a self-adaptive frame rate adjusting function; the circuit is simple in configuration, only the image output frame rate is required to be configured, meanwhile, the circuit is simple in hardware structure, only a single frame buffer is required, hardware overhead is reduced, and chip area is saved; the invention also provides a video frame rate self-adaptive conversion method which can be applied to the chips integrated with the image frame rate automatic adjustment circuit provided by the invention, can also be applied to an image video channel adjustment board level solution, and has certain application universality.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a TE frame-down mode structure in the prior art;
FIG. 2 is a block diagram of a prior art dual frame buffer mode structure;
FIG. 3 is a block diagram of a video frame rate adaptive transform circuit according to an embodiment of the present invention;
FIG. 4 is a block diagram of a frame buffer architecture of an embodiment of the present invention;
FIG. 5 is a block diagram of a video frame rate adaptive transform system in accordance with an embodiment of the present invention;
fig. 6 is a flowchart of a video frame rate adaptive transform method according to an embodiment of the present invention.
Description of the embodiments
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides a video frame rate self-adaptive conversion circuit, as shown in figure 3, which comprises an input frame rate counter, an input latch controller, a pre-processing unit, a frame buffer, a post-processing unit and an output control unit, wherein the output end of the input frame rate counter is connected with the input latch controller, video image data streams are respectively sent to the input frame rate counter and the input latch controller, the output end of the input latch controller is connected with the input end of the pre-processing unit, the output end of the pre-processing unit is connected with the input end of the frame buffer, the output end of the frame buffer is connected with the input end of the post-processing unit, and the output control unit respectively transmits transmission signals to the input latch controller, the frame buffer and the post-processing unit according to the frame rate of a CPU.
When the whole circuit is used, the output frame rate is configured according to the output end, and the system calculates the frame rate of the output video image and automatically adapts through the internal circuit. The problems of tearing effect, DSC decoding error and the like in the process of caching other single frames are effectively solved while only one frame of image is cached. Only the output frame rate is required to be configured, and the input frame rate of the input image with the input frame rate within a certain proportion range can be adjusted to the configured output frame rate for output. Has the advantages of reducing hardware resource overhead and simplifying system software configuration.
As shown in fig. 3, the input frame rate counter is responsible for detecting the frame rate of the currently received video image data stream, without any processing of the image data stream, and passing the detected input frame rate of the image data stream to the input latch controller.
As shown in fig. 3, the input latch controller receives the input frame rate count information from the input frame rate counter and the video image data stream. The input frame rate counter transmits a video image data stream of one frame to the input latch controller, that is, when each frame starts, the input latch controller judges whether or not the current frame needs to be locked according to the output timing transmitted from the output control unit, according to the methods in embodiments 1 to 3. If locked, a full frame video image data stream is not passed to the pre-processing unit, otherwise the full frame video image data stream is passed to the pre-processing unit.
As shown in fig. 3, the pre-processing unit receives the video image data stream transmitted from the input latch controller, performs necessary input processing on the video image data stream, including but not limited to scaling, denoising, white balancing, filtering, interpolation, and outputs the processed image data stream to the next stage, frame buffering.
As shown in fig. 3, the frame buffer stores the video image data stream transmitted from the pre-processing unit, and outputs the buffered video image data stream to the post-processing unit according to the transmission signal of the output control unit. The frame buffer may exist in the form of an on-chip memory, or may exist outside the chip in the form of an off-chip memory chip such as SDRAM/DDR/PSRAM. Because the input latch controller and the output control unit can control the input and output frame rate, the frame buffer can not have the problems of DSC decompression error and the like due to tearing effect caused by read-write pointer conflict.
And judging the input/output frame rate by utilizing a frame lifting and frame dropping judging mode, determining the input/output frame rate under the comparison condition of the comparator, judging whether the latch carries out latch processing on the video image data stream according to the input/output frame rate ratio, and if so, obtaining the latched image data.
As shown in fig. 3, the output control unit generates output timing (signals such as line, field synchronization, video enable, etc.) according to the frame rate and line (H)/field (V) information configured by the CPU, and simultaneously generates a read enable signal to be sent to the frame buffer, so that the frame buffer reads out video image data stream according to the read enable signal to the post-processing unit; the output control unit also transmits the current output timing to the input latch controller in real time, and the input latch controller judges whether to lock or not through the output timing.
As shown in fig. 3, the post-processing unit reads the video image data stream from the frame buffer according to the output timing provided by the output control unit, performs necessary output processing on the output video image data stream, and outputs the video image data stream.
As shown in fig. 5, the image receiving module passes the received video image data stream (including but not limited to DP/HDMI/MIPI protocol, RAW/RGB/YUV/RGBG format) to the frame rate adaptive transform module of the present invention. After the frame rate conversion is completed, the image is output to an image sending module, and then the image is sent according to an image protocol and a format required by an application end.
Example 1: an input frame rate of 80Hz and an output frame rate of 60Hz are taken as an example for illustration.
The invention also provides a video frame rate self-adaptive transformation method, as shown in fig. 4 and 6, comprising the following steps:
s1, a CPU configures the output frame rate of a system, simultaneously configures output resolution, row (H)/field (V) information (H, HFP, HSYNC, HBP, V, VFP, VSYNC, VPB) and the like, and an output control unit transmits the output frame rate to an input latch controller;
s2, the output control unit outputs an enabling signal to the frame buffer memory to start inputting the image data stream;
s3, counting the frame rate of the image data stream by an input frame rate counter, and calculating the current input frame rate according to the input field synchronous signals of two continuous frames. The larger the field sync signal interval time of two consecutive frames is, the lower the frame rate is, and conversely, the higher the frame rate is. Transmitting the image data stream with the input frame rate to an input latch controller, wherein the input latch controller calculates that the input-output frame rate ratio is 80:60, and the input-output frame rate ratio is less than 3:2;
s4, each time the field synchronizing signal of the input frame reaches the input latch controller, the input latch controller reads the current output field count Vcnt from the output control unit;
s5, if the output field count Vcnt in S4 is larger than V/2, the input latch controller locks the current input frame, and the whole frame of video image data stream is not released to the pre-processing unit; when the output field count Vcnt is V, the output field count Vcnt is cleared;
s6, if the output field count Vcnt in the step S4 is smaller than or equal to V/2, the input latch controller releases the whole frame of video image data stream of the current input frame to the pre-processing unit;
s7, repeatedly executing the steps S4 to S7.
Example 2: an input frame rate of 100Hz and an output frame rate of 60Hz are taken as an example for illustration.
As shown in fig. 4 and 6, the method further comprises the steps of:
a. the CPU configures the system output frame rate, and simultaneously configures output resolution, row (H)/field (V) information (H, HFP, HSYNC, HBP, V, VFP, VSYNC, VPB) and the like, and the output control unit transmits the output frame rate to the input latch controller;
b. the output control unit outputs an enabling signal to the frame buffer to start inputting the image data stream;
c. the input frame rate counter counts the frame rate of the image data stream and calculates the current input frame rate from the input field sync signal of two consecutive frames. The larger the field sync signal interval time of two consecutive frames is, the lower the frame rate is, and conversely, the higher the frame rate is. Transmitting the image data stream with the input frame rate to an input latch controller, wherein the input latch controller calculates that the input-output frame rate ratio is 100:60, and the input-output frame rate ratio is between 3:2 and 2:1;
d. each time a field synchronizing signal of an input frame reaches an input latch controller, the input latch controller reads a current output field count Vcnt from an output control unit;
f. if the output field count Vcnt in d is larger than V/2, the input latch controller releases the whole frame of video image data stream of the current input frame to the pre-processing unit; when the output field count Vcnt is V, the output field count Vcnt is cleared;
j. if the output field count Vcnt in the step d is smaller than or equal to V/2, the input latch controller locks the current input frame, and the whole frame of video image data stream is not released to the pre-processing unit;
k. and repeatedly executing the steps d to k.
Example 3: an example of an input frame rate of 144Hz, an input image resolution of X, an output image resolution of Y, and an output frame rate of 60Hz will be described.
As shown in fig. 4 and 6, the method further comprises the steps of:
(1) The CPU configures the system output frame rate, and simultaneously configures output resolution, row (H)/field (V) information (H, HFP, HSYNC, HBP, V, VFP, VSYNC, VPB) and the like, and the output control unit transmits the output frame rate to the input latch controller;
(2) The output control unit outputs an enabling signal to the frame buffer to start inputting the image data stream;
(3) The input frame rate counter counts the frame rate of the image data stream, and calculates the current input frame rate based on the input field sync signal of two consecutive frames. The larger the field sync signal interval time of two consecutive frames is, the lower the frame rate is, and conversely, the higher the frame rate is. Transmitting the image data stream with the input frame rate to an input latch controller, wherein the input latch controller calculates that the input/output frame rate ratio is 144:60, and the input/output frame rate ratio is more than 2:1;
(4) Each time a field synchronizing signal of an input frame reaches an input latch controller, the input latch controller reads a current output field count Vcnt from an output control unit;
(5) If the output field count Vcnt in the step (4) is larger than (X-Y) V/X, the input latch controller locks the current input frame, and the whole frame of video image data stream is not released to the pre-processing unit; when the output field count Vcnt is V, the output field count Vcnt is cleared; wherein, the input image resolution is X, and the output image resolution is Y;
(6) If the output field count Vcnt in (4) is less than or equal to (X-Y) V/X, the input latch controller releases the whole frame video image data stream of the current input frame into the pre-processing unit;
(7) Repeating steps (4) to (7).
The video frame rate self-adaptive conversion circuit provided by the invention can be integrated in a chip supporting video image switching, so that the video frame rate self-adaptive conversion circuit has a self-adaptive frame rate adjusting function. The circuit is simple in configuration, only the image output frame rate is required to be configured, meanwhile, the circuit is simple in hardware structure, only a single frame buffer is required, hardware overhead is reduced, and chip area is saved. The invention provides a video frame rate self-adaptive conversion method which can be applied to chips integrated with the image frame rate automatic adjustment circuit provided by the invention, can also be applied to an image video channel adjustment board level solution, and has certain application universality.
Although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (4)
1. A video frame rate adaptive conversion circuit, characterized by: the video image data stream is respectively sent to the input frame rate counter and the input latch controller, the output end of the input latch controller is connected with the input end of the pre-processing unit, the output end of the pre-processing unit is connected with the input end of the frame buffer, the output end of the frame buffer is connected with the input end of the post-processing unit, and the output control unit respectively transmits transmission signals to the input latch controller, the frame buffer and the post-processing unit according to the frame rate of the CPU;
the input frame rate counter is responsible for detecting the frame rate of the currently received video image data stream, does not perform any processing on the image data stream, and transmits the detected input frame rate of the image data stream to the input latch controller;
the input latch controller receives input frame rate count information from an input frame rate counter and a video image data stream;
the pre-processing unit receives the video image data stream transmitted by the input latch controller, performs necessary input processing on the video image data stream, including but not limited to scaling, denoising, white balance, filtering and interpolation, and outputs the processed image data stream to the next stage and frame buffer;
the frame buffer stores the video image data stream sent by the pre-processing unit and outputs the buffered video image data stream to the post-processing unit according to the transmission signal of the output control unit;
the output control unit generates an output time sequence according to the frame rate and the row/field information configured by the CPU, and simultaneously generates a read enabling signal to be sent to the frame buffer, so that the frame buffer reads out video image data stream to the post-processing unit according to the read enabling signal; the output control unit also transmits the current output time sequence to the input latch controller in real time, and the input latch controller judges whether locking is carried out or not through the output time sequence;
the post-processing unit reads the video image data stream from the frame buffer according to the output time sequence provided by the output control unit, performs necessary output processing on the output video image data stream, and outputs the video image data stream.
2. A video frame rate self-adaptive transformation method is characterized in that: the method comprises the following steps:
s1, a CPU configures the output frame rate of a system, and simultaneously configures the output resolution and row/field information, an output control unit transmits the output frame rate to an input latch controller, wherein the field information of the output resolution is configured as V;
s2, the output control unit outputs an enabling signal to the frame buffer memory to start inputting the image data stream;
s3, counting the frame rate of the image data stream by an input frame rate counter, and calculating the current input frame rate according to the input field synchronous signals of two continuous frames; the larger the field synchronous signal interval time of two continuous frames is, the lower the frame rate is, otherwise, the higher the frame rate is; transmitting the image data stream with the input frame rate to an input latch controller, wherein the input latch controller calculates that the input-output frame rate ratio is 80:60, and the input-output frame rate ratio is less than 3:2;
s4, each time the field synchronizing signal of the input frame reaches the input latch controller, the input latch controller reads the current output field count Vcnt from the output control unit;
s5, if the output field count Vcnt in S4 is larger than V/2, the input latch controller locks the current input frame, and the whole frame of video image data stream is not released to the pre-processing unit; when the output field count Vcnt is V, the output field count Vcnt is cleared;
s6, if the output field count Vcnt in the step S4 is smaller than or equal to V/2, the input latch controller releases the whole frame of video image data stream of the current input frame to the pre-processing unit;
s7, repeatedly executing the steps S4 to S7.
3. The video frame rate adaptive transform method according to claim 2, characterized in that: the method further comprises the steps of:
a. the CPU configures the system output frame rate, and simultaneously configures the output resolution and the row/field information, and the output control unit transmits the output frame rate to the input latch controller;
b. the output control unit outputs an enabling signal to the frame buffer to start inputting the image data stream;
c. the input frame rate counter counts the frame rate of the image data stream, and calculates the current input frame rate according to the input field synchronous signals of two continuous frames; the larger the field synchronous signal interval time of two continuous frames is, the lower the frame rate is, otherwise, the higher the frame rate is; transmitting the image data stream with the input frame rate to an input latch controller, wherein the input latch controller calculates that the input-output frame rate ratio is 100:60, and the input-output frame rate ratio is between 3:2 and 2:1;
d. each time a field synchronizing signal of an input frame reaches an input latch controller, the input latch controller reads a current output field count Vcnt from an output control unit;
f. if the output field count Vcnt in d is larger than V/2, the input latch controller releases the whole frame of video image data stream of the current input frame to the pre-processing unit; when the output field count Vcnt is V, the output field count Vcnt is cleared;
j. if the output field count Vcnt in the step d is smaller than or equal to V/2, the input latch controller locks the current input frame, and the whole frame of video image data stream is not released to the pre-processing unit;
k. and repeatedly executing the steps d to k.
4. The video frame rate adaptive transform method according to claim 2, characterized in that: the method further comprises the steps of:
(1) The CPU configures the system output frame rate, and simultaneously configures the output resolution and the row/field information, and the output control unit transmits the output frame rate to the input latch controller;
(2) The output control unit outputs an enabling signal to the frame buffer to start inputting the image data stream;
(3) The input frame rate counter counts the frame rate of the image data stream, and calculates the current input frame rate according to the input field synchronous signals of two continuous frames; the larger the field synchronous signal interval time of two continuous frames is, the lower the frame rate is, otherwise, the higher the frame rate is; transmitting the image data stream with the input frame rate to an input latch controller, wherein the input latch controller calculates that the input/output frame rate ratio is 144:60, and the input/output frame rate ratio is more than 2:1;
(4) Each time a field synchronizing signal of an input frame reaches an input latch controller, the input latch controller reads a current output field count Vcnt from an output control unit;
(5) If the output field count Vcnt in the step (4) is larger than (X-Y) V/X, the input latch controller locks the current input frame, and the whole frame of video image data stream is not released to the pre-processing unit; when the output field count Vcnt is V, the output field count Vcnt is cleared; wherein, the input image resolution is X, and the output image resolution is Y;
(6) If the output field count Vcnt in (4) is less than or equal to (X-Y) V/X, the input latch controller releases the whole frame video image data stream of the current input frame into the pre-processing unit;
(7) Repeating steps (4) to (7).
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