CN115934436B - Optical communication bus test board card - Google Patents
Optical communication bus test board card Download PDFInfo
- Publication number
- CN115934436B CN115934436B CN202211437990.6A CN202211437990A CN115934436B CN 115934436 B CN115934436 B CN 115934436B CN 202211437990 A CN202211437990 A CN 202211437990A CN 115934436 B CN115934436 B CN 115934436B
- Authority
- CN
- China
- Prior art keywords
- bus
- module
- control module
- unit
- optical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Optical Communication System (AREA)
Abstract
The utility model provides an optical communication bus test board card, board card and host computer are connected, include: the main control module is used for configuring an operation program, is connected with the bus and is internally provided with a test IP core; the test IP core comprises a local register module, a control flow control module, a short message control module and a long message control module; the test IP core is connected with and controls the local register module, the control flow control module, the short message control module and the long message control module through the on-chip bus, and the long message control module is also directly connected with the bus. The technical scheme is applied to ground test equipment in the field of aerospace industry, meets various requirements of communication among subsystems, single equipment and inter-equipment boards, can meet double redundancy of high reliability, low error rate and data communication links, meets high broadband and double redundancy, is applicable to miniaturization, and can perform functional test on data of an optical bus in a high-speed input broadband command and response message format in the aspect of equipment guarantee.
Description
Technical Field
The disclosure relates to the technical field of ground test equipment in the aerospace industry, in particular to an optical communication bus test board card.
Background
The optical communication bus in the aerospace industry can meet various requirements of communication among subsystems, single-machine equipment and inter-equipment board cards, the high-speed transmission bandwidth of the optical communication bus supports the bandwidth access of 0.6Gbps to 3.125Gbps, and the requirements of the aerospace industry on high reliability, low error rate and double redundancy of a data communication link are generally met.
Therefore, how to perform functional testing on such an optical communication bus in command and message response message format in terms of equipment assurance meets the critical issues of high bandwidth, dual redundancy, and miniaturization. The inventors have developed improvements based on the existing deficiencies.
Disclosure of Invention
In view of this, the present disclosure is directed to an optical communication bus test board for ground test in the aerospace industry.
Based on the above-mentioned purpose, this disclosure provides an optical communication bus test board card, the board card is connected with the host computer, its characterized in that includes:
the system comprises an FPGA main control module for configuring an operation program, wherein the FPGA main control module is connected with a PXIe bus, and a test IP core is arranged in the FPGA main control module;
the test IP core comprises a local register module, a control flow control module, a short message control module and a long message control module;
the PXIe bus is converted into an AXI bus and an AXI-stream bus, and the AXI-stream bus performs data interaction with an upper computer;
the AXI bus is connected with and controls a local register module, a control flow control module, a short message control module and a long message control module through an on-chip bus, and the long message control module is also directly connected with the AXI-stream bus;
the register module is configured to be directly connected with the PXIe bus backboard and used for processing a bus triggering function of the PXIe bus backboard;
the short message control module is configured to be connected with the local register module and comprises a plurality of sending units and receiving units which can mutually transmit, and is used for carrying out data interaction of short messages with the tested object;
the long message control module is configured to: the system comprises a sending path and a receiving path, wherein the sending path is used for sending by entering through the AXI-stream bus, and the receiving path is used for receiving by entering through the AXI-stream bus.
In some optional embodiments, the FPGA master control module further includes a clock unit, a program configuration unit, a bus communication unit, a cache communication unit, an optical module communication unit, and a peripheral circuit;
the program configuration unit is used for loading an operating program;
the bus communication unit is connected with the PXIe bus in polarity through an X4 form;
the cache communication unit is used for carrying out information interaction with the memory;
the optical module communication unit is used for carrying out information interaction with the two optical modules.
In some optional embodiments, the FPGA module is internally provided with 6 optical bus test IP cores, and each optical bus test IP core is connected with one link of the two optical modules.
In some optional embodiments, the local register module includes a bus trigger unit, an interrupt request control unit, and a reset request control unit connected by an on-chip bus controller, for processing a local reset request, a terminal request, and an initialization control of a plurality of optical module redundancy controllers;
the local register module is also used for processing a bus triggering function of the PXIe bus backboard, and the PXIe bus backboard is directly connected with the PCIe core controller and is connected with the on-chip bus through an AXI bus interface of the PCIe core.
In some optional embodiments, the generating and receiving paths of the long message control module each include a FIFO buffer unit, a data dividing unit, and a buffer; when the long message control module receives signals, the signals enter the AXI-stream bus through the buffer, the data dividing unit and the FIFO buffer unit; when the long message control module sends signals, the signals enter the buffer, the data segmentation unit and the FIFO buffer unit from the AXI-stream bus.
In some alternative embodiments, the buffer, the data splitting unit and the FIFO buffer unit are further connected to a local register module and an interrupt request control unit for controlling the respective modules and interrupt requests.
In some optional embodiments, the system further comprises a data buffer module serving as an off-chip buffer component of the system, the data buffer module is connected with the FPGA main control module, the FPGA is provided with a DDR controller, and at least two sets of DDR buffer arrays are controlled by two independent sets of address data buses.
In some alternative embodiments, the interface circuit of the optoelectronic module includes 4 transmit interfaces and 4 receive interfaces.
In some alternative embodiments, the interface circuit of the PXIe backplane selects a 4-channel PXIe bus interface.
From the above, it can be seen that the optical communication bus test board card provided by the present disclosure can be applied to ground test equipment in the aerospace industry field, and can meet various requirements of communication among subsystems, single-machine equipment and inter-equipment boards, and can meet dual redundancy of high reliability, low error rate and data communication links, meet dual redundancy, and is applicable to miniaturization, and can perform functional test of data on an optical bus with high-speed input broadband command and response message format in the aspect of equipment guarantee.
Drawings
In order to more clearly illustrate the technical solutions of the present disclosure or related art, the drawings required for the embodiments or related art description will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of an optical communication bus test board card according to an embodiment of the disclosure;
FIG. 2 is a block diagram of an optical communication bus test board card according to an embodiment of the present disclosure;
FIG. 3 is a block diagram of the structure of an FPGA module of an embodiment of the present disclosure;
FIG. 4 is a block diagram of an optical communication test IP core according to an embodiment of the present disclosure;
FIG. 5 is a block diagram of the local register module of an embodiment of the present disclosure;
fig. 6 is a block diagram of a short message control module according to an embodiment of the disclosure;
fig. 7 is a block diagram of a long message control module according to an embodiment of the disclosure;
fig. 8 is a block diagram of a power module according to an embodiment of the present disclosure.
Detailed Description
For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same.
It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
Before describing the optical communication bus monitoring record board card provided by the invention, the application background and the invention conception of the invention are described first, the application is applied to ground test equipment in the field of aerospace industry, the optical communication bus in the aerospace industry can meet various requirements of communication among subsystems, single equipment and board cards in the equipment, the high-speed transmission bandwidth supports the bandwidth access of 0.6 Gbps-3.125 Gbps, and the requirements of high reliability, low error rate and dual redundancy of data communication links in the aerospace industry are generally met. Thus, how to functionally test such optical buses in command and message response message format in terms of equipment assurance, and meeting high bandwidth, dual redundancy, and miniaturization becomes a critical issue.
Therefore, the inventor is an original object of the invention to provide an optical communication bus test board card for ground test in the aerospace industry based on an accurate test of data on an optical bus capable of inputting broadband command and response message formats at high speed in terms of equipment guarantee.
Referring to fig. 1, the embodiment discloses an optical communication bus test board, which is connected with an upper computer and comprises an FPGA main control module for configuring an operation program, wherein the FPGA main control module is connected with a PXIe bus, and a test IP core is arranged in the FPGA main control module;
the test IP core comprises a local register module, a control flow control module, a short message control module and a long message control module; the PXIe bus is converted into an AXI bus and an AXI-stream bus, and the AXI-stream bus performs data interaction with an upper computer; the AXI bus is connected with and controls a local register module, a control flow control module, a short message control module and a long message control module through an APB bus bridge, and the long message control module is also directly connected with the AXI-stream bus.
The register module is configured to be directly connected with the PXIe bus backboard and used for processing a bus triggering function of the PXIe bus backboard; the short message control module is configured to be connected with the local register module and comprises a plurality of sending units and receiving units which can mutually transmit, and is used for carrying out data interaction of short messages with the tested object; the long message control module is configured to: the system comprises a sending path and a receiving path, wherein the sending path is used for sending by entering through the AXI-stream bus, and the receiving path is used for receiving by entering through the AXI-stream bus.
The integrated circuit board further comprises a 6-path dual-redundancy optical interface, namely TX1-A/TX 1-B-TX 6-A/TX6-B, and comprises an FPGA controller module, a clock module, a DDR3 module, a SPIFASH module, a power module and the like, wherein the integrated circuit board is further combined with the integrated circuit board shown in FIG. 2. In use, there are two modes:
mode 1: the monitored equipment is communicated and interacted through the control IP core arranged in the board FPGA controller, and meanwhile, the data transmitted and received by the local card and the opposite party in the bus are monitored, so that the device is mainly used for point-to-point test monitoring.
Mode 2: the board card is connected into the exchanger, the monitored equipment is not subjected to data interaction when in use, and the data receiving and transmitting on the bus are monitored only in the network domain, so that the board card is used for networking monitoring test.
In some optional embodiments, the FPGA master control module further includes a clock unit, a program configuration unit, a bus communication unit, a cache communication unit, an optical module communication unit, and a peripheral circuit;
the bus communication unit is connected with the PXIe bus in polarity through an on-chip bus form;
the cache communication unit is used for carrying out information interaction with the memory;
the optical module communication unit is used for carrying out information interaction with the optical module.
Further, 6 paths of optical bus test IP cores are arranged in the FPGA module, and each path of optical bus test IP core is connected with one link in the two optical modules.
Further referring to fig. 3, in some alternative embodiments, the FPGA master control module is composed of an FPGA, a clock, a program configuration FLASH, a PXI communication interface, a DDR3 SDRAM cache interface, and other peripheral circuits.
The FPGAUK module is mainly used for loading and running programs from program configuration SPI-FLASH, the PXIe interface is connected with the bus polarity in an X4 mode and is used for the module to communicate with the PXIe bus, the DDR cache interface is used for the module to interact with the DDR3 memory, and the GLINK communication interface is used for carrying out data receiving and transmitting communication with the optical module A and the optical module B (AB redundancy). The module is internally provided with 6 paths of optical bus test IP cores. Each path of optical bus test IP core is connected with one path of link in the optical module A and one path of link in the optical module B.
Further referring to fig. 4, the optical communication test IP core module abstracts the functional test of the instruction+response type optical communication into three test control modules, which are respectively a control flow control module, a short message control module and a long message control module, and are respectively designed by adopting hardware description languages. In the figure, the PXIe bus is converted into an AXI bus and an AXI-Stream bus through a bridge module, the AXI bus is converted into a low-speed bus with address and data separated through an on-chip bus, and a local register control module, a control flow control module, a short message control module and a long message control module are respectively controlled through the on-chip bus. The long message control module needs to transmit high-speed data, and is directly connected with the AXI-Stream bus.
In some optional embodiments, the local register module includes a bus trigger unit, an interrupt request control unit, and a reset request control unit connected by an on-chip bus controller, for processing a local reset request, a terminal request, and an initialization control of a plurality of optical module redundancy controllers; the local register module is also used for processing a bus triggering function of the PXIe bus backboard, and the PXIe bus backboard is directly connected with the PCIe core controller and is connected with the on-chip bus through an AXI bus interface of the PCIe core.
Further as shown in fig. 5, in the local register module, a local reset request, an interrupt request, and an initialization control of the optical module a/B redundancy controller are processed. And, the local register module handles the bus trigger function of the PXIe bus backplane.
Further, in the local register module, the PXIe backboard is directly connected with a bus trigger submodule of the local register control module, and is used for realizing a backboard synchronous trigger controller. The PXIe backboard signal is directly connected with the PCIe core controller, the internal bus is connected with the internal bus through an AXI bus interface of the PCIe core, and the setting of a bus trigger register in the local register module, the setting of an interrupt request controller register and the setting of a reset request control register are controlled through the internal bus.
Referring to fig. 6, in some alternative embodiments, the short message control module includes at least 15 FIFO sending units and 15 FIFO receiving units, and further includes a gating unit, a mapping table unit, a framing sending unit, and a deframed sending unit;
the gating unit comprises a sending gating and receiving gating, the mapping table comprises a sending mapping table and a receiving mapping table, the interactive data is transmitted from the FIFO sending unit to the sending gating and sending mapping table, then is transmitted to the receiving gating and receiving mapping table through the framing sending unit and the de-framing sending unit, and finally is transmitted to the FIFO receiving unit; the receiving gating, receiving mapping table and frame transmitting unit are connected with the register control unit.
In order to cover the range of the short message sub-address, a gating module and a mapping table module are designed to gate and map the sending and receiving FIFO modules, and the sending/receiving FIFO gating module determines which of the FIFOs are used as sending sub-address buffers and the other are used as receiving sub-address buffers. The sending/receiving FIFO mapping table module can perform sub-address mapping on the alternative FIFO, and the mapped FIFO is directly connected with the framing/de-framing sending module of the short message and is used for a buffer area for sending and receiving data of a communication test on a tested object. The short message control module is used for carrying out data interaction of short messages with the tested equipment.
In some optional embodiments, the generating and receiving paths of the long message control module each include a FIFO buffer unit, a data dividing unit, and a buffer;
when the long message control module receives signals, the signals enter the AXI-stream bus through the buffer, the data dividing unit and the FIFO buffer unit;
when the long message control module sends signals, the signals enter the buffer, the data segmentation unit and the FIFO buffer unit from the AXI-stream bus.
The buffer, the data dividing unit and the FIFO buffer unit are also connected to a local register module and an interrupt request control unit for controlling the respective modules and interrupt requests.
Referring to fig. 7, when the long message control module sends, the AXI-Stream bus passes through the FIFO buffer 1, the data splitting module 1, and the DDR3 buffer. Upon reception, the AXI-Stream bus is reached from the DDR3 buffer, the data splitting module 2, the FIFO buffer 2. And the AXI-Stream bus performs data interaction with the upper computer through DMA. The register and interrupt request controller is used for controlling each module and interrupt request.
In some alternative embodiments, the control flow control module is configured for data interaction of control flow with the monitored device; the short message control module is connected with the local register module and comprises a plurality of sending units and receiving units which can mutually transmit, and the sending units and the receiving units are used for carrying out data interaction of short messages with monitored equipment; the monitoring control module comprises a receiving path, wherein the receiving path comprises a first buffer, a data dividing unit and a second buffer, is sequentially connected to the AXI bus and is used for monitoring data receiving and transmitting of other modules on the AXI bus.
In some optional embodiments, the FPGA master control module further includes a data cache module, a power module, a clock module, and an optoelectronic module.
In some optional embodiments, the FPGA master control module further includes a data cache module, a power module, a clock module, and a photovoltaic module; the data cache module is used as an off-chip cache component of the system, the data cache module is connected with the FPGA main control module, the FPGA is provided with a DDR controller, and at least two DDR cache arrays are controlled through two independent address data buses.
In some optional embodiments, the system further comprises a photoelectric module integrating 4 paths of parallel transceiving and a power module limiting working voltage, wherein the photoelectric module and the power module are connected with the FPGA main control module.
The photoelectric module is a middle-navigation photoelectric 4EONTR-85-5127X3M (01) 4-path parallel transceiving integrated photoelectric module. The emission wavelength of the module is 850nm, the SNAP12 packaging form is adopted, the electrical interface is MEG-ARRAY, and the optical port is MPO plug-in type. The power supply is +3.3V, four-way transmission and four-way reception are integrated, and the rate of each channel is 3.125Gbps.3.3V power supply, 3.125Gbps transmission rate per channel, 850nm emission wavelength, MPO optical interface, MEG-ARRAY electrical interface, and control end CMOS compatibility.
As shown in fig. 8, in this solution, PXIe chassis back board 12V is used as a board input power, and two LTM4644iy_rev_0dc/DC controllers of Linear Technology company are designed to supply power to each functional module according to the principles of high stability and low complexity. The chip 4-14V has wide voltage input range and outputs current 4A in each channel peak value. In order to improve the reliability of the system, the power-on sequence of the board card is 1.0V < - >1.2V < - >1.5V < - >1.8V < - >3.3V.
The main interface circuit design of the scheme adopts the circuit design that the PXIe Gen2 single-channel bandwidth is 5Gb/s, the scheme adopts the 4-channel PXIe bus interface, and the theoretical uplink and downlink data transmission bandwidth is 2Gb/s,
as an alternative embodiment, the design of the photoelectric conversion interface circuit, the optical ports defined by the pluggable MPO optical interface are sequentially from left to right: emission 1, emission 2, emission 3, emission 4, null, reception 4, reception 3, reception 2, reception 1.
The optical communication bus test board card provided by the embodiment of the disclosure can be applied to ground test equipment in the aerospace industry field, meets various requirements of communication among subsystems, single-machine equipment and inter-equipment board cards, can meet double redundancy of high reliability, low error rate and data communication links, meets high broadband and double redundancy, is applicable to miniaturization, and can perform functional test on optical buses for inputting broadband command and response message formats at high speed in the aspect of equipment guarantee.
It should be noted that the method of the embodiments of the present disclosure may be performed by a single device, such as a computer or a server. The method of the embodiment can also be applied to a distributed scene, and is completed by mutually matching a plurality of devices. In the case of such a distributed scenario, one of the devices may perform only one or more steps of the methods of embodiments of the present disclosure, the devices interacting with each other to accomplish the methods.
It should be noted that the foregoing describes some embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the disclosure, including the claims, is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined under the idea of the present disclosure, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in details for the sake of brevity.
Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure the embodiments of the present disclosure. Furthermore, the devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present disclosure, and this also accounts for the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform on which the embodiments of the present disclosure are to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that embodiments of the disclosure can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
The disclosed embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Accordingly, any omissions, modifications, equivalents, improvements, and the like, which are within the spirit and principles of the embodiments of the disclosure, are intended to be included within the scope of the disclosure.
Claims (6)
1. An optical communication bus test board card, the board card is connected with an upper computer, the optical communication bus test board card is characterized by comprising:
the system comprises an FPGA main control module for configuring an operation program, wherein the FPGA main control module is connected with a PXIe bus, and a test IP core is arranged in the FPGA main control module; the FPGA main control module further comprises a clock unit, a program configuration unit, a bus communication unit, a cache communication unit, an optical module communication unit and a peripheral circuit, wherein the program configuration unit is used for loading and running programs; the bus communication unit is connected with the PXIe bus in polarity through an on-chip bus form; the cache communication unit is used for carrying out information interaction with the memory; the optical module communication unit is used for carrying out information interaction with the optical module; each path of the optical bus test IP core is connected with one link of the two optical modules;
the test IP core comprises a local register module, a control flow control module, a short message control module and a long message control module;
the PXIe bus is converted into an AXI bus and an AXI-stream bus, and the AXI-stream bus performs data interaction with an upper computer;
the AXI bus is connected with and controls a local register module, a control flow control module, a short message control module and a long message control module through an on-chip bus, and the long message control module is also directly connected with the AXI-stream bus.
2. The optical communication bus test board of claim 1, wherein the local register module comprises a bus trigger unit, an interrupt request control unit and a reset request control unit connected by an on-chip bus controller, for processing a local reset request, a terminal request, and an initialization control of a plurality of optical module redundancy controllers;
the local register module is also used for processing a bus triggering function of the PXIe bus backboard, and the PXIe bus backboard is directly connected with the PCIe core controller and is connected with the on-chip bus through an AXI bus interface of the PCIe core.
3. The optical communication bus test board according to claim 1, wherein the transmission and reception paths of the long message control module each include a FIFO buffer unit, a data dividing unit, and a buffer;
when the long message control module receives signals, the signals enter the AXI-stream bus through the buffer, the data dividing unit and the FIFO buffer unit;
when the long message control module sends signals, the signals enter the buffer, the data segmentation unit and the FIFO buffer unit from the AXI-stream bus.
4. The optical communication bus test board according to claim 3, wherein the buffer, the data dividing unit and the FIFO buffer unit are further connected to a local register module and an interrupt request control unit for controlling the respective modules and interrupt requests.
5. The optical communication bus snoop record board of claim 1, further comprising a data buffer module, a power module, a clock module, and an optoelectronic module.
6. The optical communication bus listening recording board of claim 1 wherein the interface circuitry of the PXIe backplane is a multi-channel PXIe bus interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211437990.6A CN115934436B (en) | 2022-11-15 | 2022-11-15 | Optical communication bus test board card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211437990.6A CN115934436B (en) | 2022-11-15 | 2022-11-15 | Optical communication bus test board card |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115934436A CN115934436A (en) | 2023-04-07 |
| CN115934436B true CN115934436B (en) | 2023-07-18 |
Family
ID=86699967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211437990.6A Active CN115934436B (en) | 2022-11-15 | 2022-11-15 | Optical communication bus test board card |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115934436B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115955273B (en) * | 2022-11-15 | 2024-09-24 | 航天新长征大道科技有限公司 | Optical communication bus monitoring recording board card |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104618208A (en) * | 2015-01-26 | 2015-05-13 | 国电南瑞科技股份有限公司 | Elastic data interaction comprehensive bus system |
| CN106612141B (en) * | 2016-12-20 | 2019-04-12 | 北京旋极信息技术股份有限公司 | A kind of fiber channel protocol common simulation test card and its data interactive method |
| CN112231264A (en) * | 2019-07-15 | 2021-01-15 | 唐健 | Embedded PXIe bus controller |
| CN114168520B (en) * | 2021-12-13 | 2023-08-25 | 航天新长征大道科技有限公司 | Optical fiber communication bus device, equipment and system |
-
2022
- 2022-11-15 CN CN202211437990.6A patent/CN115934436B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN115934436A (en) | 2023-04-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114168520B (en) | Optical fiber communication bus device, equipment and system | |
| CN113391589B (en) | Unified access and protocol conversion integrated circuit board for heterogeneous equipment of unmanned aerial vehicle | |
| CN113609045B (en) | Intelligent network card BMC communication structure and method | |
| CN111901164B (en) | Adaptive control method, device, equipment and system of OCP NIC network card | |
| US6898766B2 (en) | Simplifying integrated circuits with a common communications bus | |
| CN110727637B (en) | FPGA chip and electronic equipment | |
| CN115934436B (en) | Optical communication bus test board card | |
| TW202005485A (en) | Switch board for expanding peripheral component interconnect express compatibility | |
| CN111694781A (en) | ARM main control board based on data acquisition system | |
| CN212135411U (en) | IO module and OCP keysets | |
| TW201838391A (en) | Interface circuit, signal transmission system and signal transmission method thereof | |
| CN109213717B (en) | Double-bridge-plate framework of domestic Feiteng processor | |
| CN115955273B (en) | Optical communication bus monitoring recording board card | |
| CN117194309A (en) | Controller for inter-chip interconnection, chip, processing system and electronic device | |
| CN206363303U (en) | A kind of CPU module based on VPX structures | |
| CN102902647B (en) | Be arranged on I2C from the asic chip of machine printed circuit board (PCB) and printed circuit board (PCB) | |
| CN113970896A (en) | Control device based on FPGA chip and electronic equipment | |
| CN113391570A (en) | Low-cost low-complexity multi-channel DA synchronous control method | |
| CN218181515U (en) | Calculation board card and computer equipment | |
| CN115102620B (en) | Optical fiber 1553B bus communication device | |
| CN109600234A (en) | The signal processing method of the double-deck FC card PCB construction and bilayer FC card | |
| CN114520919B (en) | High-speed video signal processing system and method | |
| CN216286659U (en) | High-speed data processing equipment based on homemade VPX framework | |
| CN211375365U (en) | 1553B bus function testing device of USB interface | |
| CN110765057A (en) | Port multiplexing system based on SPI communication |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |