CN115101023A

CN115101023A - Array substrate, display panel and display device

Info

Publication number: CN115101023A
Application number: CN202210772097.2A
Authority: CN
Inventors: 吴剑龙
Original assignee: Xiamen Tianma Display Technology Co Ltd
Current assignee: Xiamen Tianma Display Technology Co Ltd
Priority date: 2022-06-30
Filing date: 2022-06-30
Publication date: 2022-09-23

Abstract

The invention provides an array substrate, a display panel and a display device.A shift register comprises a plurality of thin film transistors, each thin film transistor comprises a set thin film transistor, and each set thin film transistor comprises a semiconductor layer, a grid electrode, a source electrode, a drain electrode and a shielding metal layer; the shielding metal layer is overlapped with the semiconductor layer in a direction perpendicular to the substrate; the first constant voltage line provides a first constant voltage with a voltage value less than 0V, and the second constant voltage line provides a second constant voltage with a voltage value greater than 0V; setting the thin film transistor as an N-type transistor, wherein the shielding metal layer is electrically connected with the first constant voltage line; or, the thin film transistor is set to be a P-type transistor, and the shielding metal layer is electrically connected to the second constant voltage line. The invention provides an array substrate, a display panel and a display device, wherein the offset threshold voltage is corrected to a normal range through a shielding metal layer, abnormal opening of a set thin film transistor is avoided, and therefore the working stability of the array substrate is improved.

Description

Array substrate, display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

With the development of science and technology and the progress of society, people have increasingly relied on information communication and transmission, and display devices as main carriers and material bases for information exchange and transmission are now hot spots researched by many scientists.

A thin film transistor (i.e., TFT) is widely used as a switching element in a display panel (e.g., a liquid crystal panel or an organic light emitting display panel). Therefore, the array substrate formed with the thin film transistors is a basic element of a display panel configured for a display device.

However, in the display driving circuit of the array substrate, there is a risk that the thin film transistor is abnormally turned on.

Disclosure of Invention

The invention provides an array substrate, a display panel and a display device, wherein the offset threshold voltage is corrected to a normal range through a shielding metal layer, abnormal opening of a set thin film transistor is avoided, and therefore the working stability of the array substrate is improved.

In a first aspect, an embodiment of the present invention provides an array substrate, including a display area and a non-display area, where the non-display area is located at a periphery of the display area;

a substrate;

a display driving circuit, located in a non-display region on one side of the substrate, including a plurality of cascaded shift registers, a first constant voltage line, and a second constant voltage line;

the shift register comprises a plurality of thin film transistors, the thin film transistors comprise setting thin film transistors, and the setting thin film transistors comprise semiconductor layers, grid electrodes, source electrodes, drain electrodes and shielding metal layers; the shielding metal layer is overlapped with the semiconductor layer in a direction perpendicular to the substrate;

the first constant voltage line supplies a first constant voltage having a voltage value less than 0V, and the second constant voltage line supplies a second constant voltage having a voltage value greater than 0V;

the setting thin film transistor is an N-type transistor, and the shielding metal layer is electrically connected with the first constant voltage line; or, the set thin film transistor is a P-type transistor, and the shielding metal layer is electrically connected to the second constant voltage line.

In a second aspect, an embodiment of the present invention provides a display panel, including the array substrate of the first aspect.

In a third aspect, an embodiment of the present invention provides a display device, including the display panel of the second aspect.

An embodiment of the present invention provides an array substrate, which includes a display driving circuit, where the display driving circuit includes a shift register, a first constant voltage line, and a second constant voltage line. At least a part of the thin film transistors in the shift register are set thin film transistors. The thin film transistor is configured to include a shield metal layer overlapping the semiconductor layer. For the N-type transistor, the shielding metal layer and the first constant voltage line, and for the P-type transistor, the shielding metal layer and the second constant voltage line are used, so that the offset threshold voltage is corrected to a normal range through the shielding metal layer, abnormal opening of the thin film transistor is avoided, and the working stability of the array substrate is improved.

Drawings

Fig. 1 is a schematic top view of an array substrate according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a display driving circuit according to an embodiment of the present invention;

fig. 3 is a schematic cross-sectional view of a shift register according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another display driving circuit according to an embodiment of the present invention;

fig. 5 is a schematic circuit diagram of a shift register according to an embodiment of the present invention;

fig. 6 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 7 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 8 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 9 is a schematic circuit diagram of another shift register according to an embodiment of the present invention,

fig. 10 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 11 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 12 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

FIG. 13 is a schematic cross-sectional view of another shift register according to an embodiment of the present invention;

fig. 14 is a schematic cross-sectional view of a display panel according to an embodiment of the invention;

fig. 15 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Research shows that the threshold voltage of the thin film transistor in the off state for a long time can deviate, so that abnormal opening is caused. For an N-type transistor, the threshold voltage is biased negative, for example, the original 2V threshold voltage is changed to 1.5V, so that the abnormal turn-on is easy. For a P-type transistor, the threshold voltage is biased to be positive, for example, the original-2V threshold voltage is changed to-1.5V, so that abnormal turn-on is easy.

Fig. 1 is a schematic top view of an array substrate according to an embodiment of the present invention, fig. 2 is a schematic structural diagram of a display driving circuit according to an embodiment of the present invention, fig. 3 is a schematic cross-sectional diagram of a shift register according to an embodiment of the present invention, fig. 4 is a schematic structural diagram of another display driving circuit according to an embodiment of the present invention, referring to fig. 1 to fig. 4, the array substrate includes a display area 01 and a non-display area 02, and the non-display area 02 is located at a periphery of the display area 01.

The array substrate includes a substrate 43 and a display driving circuit 10. The display driver circuit 10 is located in the non-display area 02 on the substrate 43 side. The display driving circuit 10 is used to provide a switching control signal to the pixel unit 20 in the display area 01. The pixel unit 20 may include a pixel driving circuit and a light emitting unit, and the display driving circuit 10 is configured to provide a switch control signal to the pixel driving circuit, so that the pixel driving circuit drives the light emitting unit to emit light under the control of a preset timing sequence. The switching control signal may include, for example, a scan signal (i.e., a scan signal), a light emission control signal (i.e., an emit signal), and the like.

The display driving circuit 10 includes a plurality of cascaded shift registers 40, a first constant voltage line 11, and a second constant voltage line 12. The shift register 40 includes a plurality of thin film transistors 41 (in fig. 2 and 3, one thin film transistor 41 in the shift register 40 is illustrated). The thin film transistor 41 includes a setting thin film transistor 410, that is, at least a part of the thin film transistors 41 in the shift register 40 is the setting thin film transistor 410. In one embodiment, the tfts 41 in the shift register 40 are all set tfts 410. In another embodiment, a part of the tfts 41 in the shift register 40 are set tfts 410, and another part of the tfts 41 in the shift register 40 are not set tfts 410.

The thin film transistor 410 is configured to include a semiconductor layer 411, a gate electrode 412, a source electrode 413, a drain electrode 414, and a shield metal layer 415. The shielding metal layer 415 overlaps the semiconductor layer 411 in a direction perpendicular to the substrate 43. The voltage on the shield metal layer 415 affects the width of the conductive channel in the semiconductor layer 411 and thus the threshold voltage of the thin film transistor 410. The threshold voltage is a voltage for turning on or off the thin film transistor 41 (including setting the thin film transistor 410).

As shown in fig. 2, the thin film transistor 410 is set to be an N-type transistor, and the shield metal layer 415 is electrically connected to the first constant voltage line 11. The first constant voltage line 11 supplies a first constant voltage having a voltage value less than 0V. The shield metal layer 415 having the first constant voltage is provided to set the threshold voltage of the thin film transistor 410 to be positive. For example, in the tft 410 with a threshold voltage that is negatively biased, the original 2V threshold voltage is negatively biased to 1.5V, and the shielding metal layer 415 is smaller than the first constant voltage of 0V, so that 1.5V is pulled to 2V, that is, the normal threshold voltage is corrected, thereby avoiding abnormal turn-on of the tft 410.

As shown in fig. 4, the thin film transistor 410 is set to be a P-type transistor, and the shield metal layer 415 is electrically connected to the second constant voltage line 12. The second constant voltage line 12 supplies a second constant voltage having a voltage value greater than 0V. The shield metal layer 415 having the second constant voltage is provided to pull down the threshold voltage of the thin film transistor 410. For example, in the tft 410 with a forward shift of the threshold voltage, the original-2V threshold voltage is shifted forward to-1.5V, and the-1.5V is pulled to-2V due to the shielding metal layer 415 being greater than the second constant voltage of 0V, i.e., corrected to the normal threshold voltage, thereby avoiding the abnormal turn-on of the tft 410.

An embodiment of the present invention provides an array substrate, where the array substrate includes a display driving circuit 10, and the display driving circuit 10 includes a shift register 40, a first constant voltage line 11, and a second constant voltage line 12. At least some of the tfts 41 in the shift register 40 are set tfts 410. The setting thin film transistor 410 includes a shielding metal layer 415 overlapping the semiconductor layer 411. For an N-type transistor, the shielding metal layer 415 and the first constant voltage line 11, and for a P-type transistor, the shielding metal layer 415 and the second constant voltage line 12 correct the shifted threshold voltage to a normal range through the shielding metal layer 415, thereby avoiding setting abnormal turn-on of the thin film transistor 410, and improving the working stability of the array substrate.

It should be further noted that, since the display driving circuit 10 in the non-display area 02 is used for providing the switch control signal, the off time of the display driving circuit 10 in the off state for a long time is much longer than the enable level time of the switch control signal. For example, much longer than the on-time of the scan signal. In the embodiment of the present invention, the shielding metal layer 415 is provided, and a voltage is provided to the shielding metal layer 415, which is suitable for the display driving circuit 10 in the non-display area 02.

It should be further noted that, the shielding metal layer 415 is electrically connected to the first constant voltage line 11 or the second constant voltage line 12, and the shielding metal layer 415 receives the first constant voltage or the second constant voltage, so that the voltage value on the shielding metal layer 415 is not changed, and the threshold voltage of the thin film transistor 410 is not changed, which is beneficial to improving the circuit stability of the shift register 40, improving the circuit stability of the display driving circuit 10, and improving the working stability of the array substrate.

The present invention further takes P-type transistors as an example to describe the arrangement of the thin film transistors 410 in the shift register 40, but not limited thereto, at least one of the thin film transistors 410 in the shift register 40 may also be an N-type transistor. For a P-type transistor, the turn-off voltage is high and the turn-on voltage is low. For an N-type transistor, the turn-off voltage is low and the turn-on voltage is high.

Fig. 5 is a schematic circuit diagram of a shift register according to an embodiment of the present invention, and referring to fig. 5, the shift register 40 includes a pull-down unit 51. The pull-down unit 51 is electrically connected to the first voltage terminal VGL, the first node N1 and the cascade signal output terminal OUT, and the pull-down unit 51 is configured to transmit a signal input from the first voltage terminal VGL to the cascade signal output terminal OUT under the control of the first node N1. The first voltage terminal VGL provides a low level constant voltage. The first node N1 serves as a control node of the pull-down unit 51, and controls the pull-down unit 51 to be in an off state for a long time. The time for which the pull-down unit 51 is turned on is less than the time for which the pull-down unit 51 is turned off. The pull-down unit 51 is turned on for a short time, the pull-down unit 51 is turned off for a long time, and the thin film transistors 41 in the pull-down unit 51 are in an off state for a long time, thereby setting at least one thin film transistor 41 in the pull-down unit 51 as the set thin film transistor 410.

Fig. 6 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and referring to fig. 6, the pull-down unit 51 includes a tenth transistor M10. A first terminal of the tenth transistor M10 is electrically connected to the first voltage terminal CGL, a second terminal of the tenth transistor M10 is electrically connected to the cascade signal output terminal OUT, and a gate of the tenth transistor M10 is electrically connected to the first node N1. The first node N1 controls the tenth transistor M10 to be in an off state for a long time, thereby setting the tenth transistor M10 to be the setting thin film transistor 410.

Fig. 7 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and referring to fig. 7, the shift register includes a pull-up unit 52 and a pull-up control unit 53. The pull-up unit 52 is electrically connected to the second voltage terminal VGH, the second node N2 and the cascade signal output terminal OUT, and the pull-up unit 52 is configured to transmit a signal input from the second voltage terminal VGH to the cascade signal output terminal OUT under the control of the second node N2. The second voltage terminal VGH provides a high level constant voltage. The pull-up control unit 53 is electrically connected to the second voltage terminal VGH, the first clock signal input terminal CK, the second clock signal input terminal XCK, the first node N1, and the second node N2. The pull-up control unit 53 is configured to transmit the signal of the second voltage terminal VGH or the second clock signal input terminal XCK to the second node N2 under the control of the first node N1 and the second clock signal input terminal XCK. Since the first node N1 serves as a control node of the pull-up control unit 53 and the thin film transistors in the pull-up control unit 53 are in an off state for a long time, at least one thin film transistor 41 in the pull-up control unit 53 is set as the setting thin film transistor 410.

Alternatively, referring to fig. 7, the pull-up control unit 53 includes a sixth transistor M6, a first terminal of the sixth transistor M6 is electrically connected to the second voltage terminal VGH, a second terminal of the sixth transistor M6 is electrically connected to the second node N2, and a gate of the sixth transistor M6 is electrically connected to the first node N1. The first node N1 controls the sixth transistor M6 to be in an off state for a long time, thereby setting the sixth transistor M6 as the setting thin film transistor 410.

Fig. 8 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and referring to fig. 8, the pull-up control unit 53 includes a second transistor M2, a third transistor M3, and a seventh transistor M7. A first terminal of the second transistor M2 is electrically connected to the first clock signal input terminal CK, a second terminal of the second transistor M2 is electrically connected to the gate of the third transistor M3, and a gate of the second transistor M2 is electrically connected to the third node N3. The third node N3 has the same voltage timing as the first node N1, that is, the third node N3 and the first node N1 generate a rising edge and a falling edge at the same time, and generate the same voltage variation trend at the same time. In other embodiments, the gate of the second transistor M2 may also be connected to the first node N1. A first terminal of the third transistor M3 is electrically connected to a first terminal of the seventh transistor M7, and a second terminal of the third transistor M3 is electrically connected to the second clock signal input terminal XCK. A gate of the seventh transistor M7 is electrically connected to the second clock signal input terminal XCK, and a second terminal of the seventh transistor M7 is electrically connected to the second node N2. The first node N1 or the third node N3 controls the second transistor M2 to be in an off state for a long time, thereby setting the second transistor M2 to be the setting thin film transistor 410.

Exemplarily, referring to fig. 8, the gate of the third transistor M3 and the second terminal of the second transistor M2 are electrically connected to the fourth node N4. The pull-up control unit 53 includes a third capacitor C3 and a fourth capacitor C4. A first plate of the third capacitor C3 is electrically connected to the fourth node N4, and a second plate of the third capacitor C3 is electrically connected to the first terminal of the third transistor M3. A first plate of the fourth capacitor C4 is electrically connected to the third node N3, and a second plate of the fourth capacitor C4 is electrically connected to the second voltage terminal VGH.

Fig. 9 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and referring to fig. 9, the pull-up control unit 53 further includes a thirteenth transistor M13. The first end of the thirteenth transistor M13 is electrically connected to the second voltage terminal VGH, the second end of the thirteenth transistor M13 is electrically connected to the first node N1, the gate of the thirteenth transistor M13 is electrically connected to the power-on signal Control terminal Control, the power-on signal Control terminal Control turns on the thirteenth transistor M13 during the power-on period, and transmits the high-level constant voltage provided by the second voltage terminal VGH to the first node N1, so as to turn off the tenth transistor M10, prevent the false power-on of the tenth transistor M10 during the power-on period, and prevent the phenomenon of power-on flicker. The thirteenth transistor M13 is turned on only in the power-on stage and is in an off state in a normal operation state of the display device, thereby setting the thirteenth transistor M13 as the setting thin film transistor 410.

Fig. 10 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and referring to fig. 10, the shift register 40 includes a pull-down control unit 54. The pull-down control unit 54 is electrically connected to the first voltage terminal VGL, the second voltage terminal VGH, the first clock signal input terminal CK, the second clock signal input terminal XCK, the cascade signal input terminal IN, and the first node N1. The pull-down control unit 54 is configured to transmit the signal of the second voltage terminal VGH or the cascade signal input terminal IN to the first node N1 under the control of the first clock signal input terminal CK and the second clock signal input terminal XCK. Wherein the second voltage terminal VGH provides a high level constant voltage.

Exemplarily, referring to fig. 10, the pull-up unit 52 includes a ninth transistor M9 and a first capacitor C1. A first terminal of the ninth transistor M9 is electrically connected to the second voltage terminal VGH, a second terminal of the ninth transistor M9 is electrically connected to the cascade signal output terminal OUT, and a gate of the ninth transistor M9 is electrically connected to the second node N2. The first plate of the first capacitor C1 is electrically connected to the second voltage terminal VGH, and the second plate of the first capacitor C1 is electrically connected to the second node N2.

Exemplarily, referring to fig. 10, the pull-down control unit 54 includes a first transistor M1, a fourth transistor M4, a fifth transistor M5, an eighth transistor M8, an eleventh transistor M11, and a second capacitor C2. A first terminal of the eighth transistor M8 is electrically connected to the second voltage terminal VGH, a second terminal of the eighth transistor M8 is electrically connected to the first terminal of the first transistor M1, and a gate of the eighth transistor M8 is electrically connected to the fourth node N4. A second terminal of the first transistor M1 is electrically connected to the first node N1, and a gate of the first transistor M1 is electrically connected to the second clock signal input terminal XCK. A first terminal of the eleventh transistor M11 is electrically connected to the third node N3, a second terminal of the eleventh transistor M11 is electrically connected to the cascade signal input terminal IN, and a gate of the eleventh transistor M11 is electrically connected to the first clock signal input terminal CK. A first terminal of the fifth transistor M5 is electrically connected to the first voltage terminal VGL, a second terminal of the fifth transistor M5 is electrically connected to the fourth node N4, and a control terminal of the fifth transistor M5 is electrically connected to the first clock signal input terminal CK. A first terminal of the fourth transistor M4 is electrically connected to the first node N1, a second terminal of the fourth transistor M4 is electrically connected to the cascade signal input terminal IN, and a gate of the fourth transistor M4 is electrically connected to the first clock signal input terminal CK. The first plate of the second capacitor C2 is electrically connected to the second clock signal input XCK, and the second plate of the second capacitor C2 is electrically connected to the first node N1.

Exemplarily, referring to fig. 10, the fourth transistor M4 and the gate of the eleventh transistor M11 are both electrically connected to the first clock signal input terminal CK, and are turned on simultaneously or turned off simultaneously under the control of the first clock signal input terminal CK. When the fourth transistor M4 and the eleventh transistor M11 are turned on, the signal at the cascade signal input terminal IN is transmitted to the first node N1 and the third node N3, respectively, so that the first node N1 and the third node N3 have the same voltage timing.

Referring to fig. 11, the pull-down control unit 54 is electrically connected to the first voltage terminal VGL, the second voltage terminal VGH, the first clock signal input terminal CK, the second clock signal input terminal XCK, the cascade signal input terminal IN, and the first node N1. The pull-down control unit 54 is configured to transmit the signal of the second voltage terminal VGH or the cascade signal input terminal IN to the first node N1 under the control of the first clock signal input terminal CK and the second clock signal input terminal XCK. Wherein the second voltage terminal VGH provides a high level constant voltage. The pull-down control unit 54 is electrically connected to the first node N1, thereby setting at least one thin film transistor 41 in the pull-down control unit 54 to be the set thin film transistor 410.

Fig. 12 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and referring to fig. 12, the pull-down control unit 54 includes a first transistor M1, a fourth transistor M4, a fifth transistor M5, an eighth transistor M8, and a second capacitor C2. A first terminal of the first transistor M1 is electrically connected to the first plate of the second capacitor C2, a second terminal of the first transistor M1 is electrically connected to the second clock signal input terminal XCK, and a gate of the first transistor M1 is electrically connected to the first node N1. A first terminal of the fourth transistor M4 is electrically connected to the first node N1, a second terminal of the fourth transistor M4 is electrically connected to the cascade signal input terminal IN, and a gate of the fourth transistor M4 is electrically connected to the first clock signal input terminal CK. A first terminal of the fifth transistor M5 is electrically connected to the first voltage terminal VGL, a second terminal of the fifth transistor M5 is electrically connected to the fourth node N4, and a control terminal of the fifth transistor M5 is electrically connected to the first clock signal input terminal CK. A first terminal of the eighth transistor M8 is electrically connected to the second voltage terminal VGH, and a second terminal of the eighth transistor M8 is electrically connected to the first terminal of the first transistor M1. The second plate of the second capacitor C2 is electrically connected to the first node N1. The first node N1 controls the first transistor M1 to be in an off state for a long time, thereby setting the first transistor M1 to be the setting thin film transistor 410.

Exemplarily, referring to fig. 12, the pull-up control unit 53 includes an eleventh transistor M11 and a twelfth transistor M12, the eleventh transistor M11 and the twelfth transistor M12 are both electrically connected to the first voltage terminal VGL, and are always turned on under the control of the first voltage terminal VGL since the eleventh transistor M11 and the twelfth transistor M12 are both P-type transistors, whereby the voltage of the first node N1 is equal to the voltage of the fifth node N5, and the voltage of the fourth node N4 is equal to the voltage of the sixth node N6.

Alternatively, referring to fig. 2, the first voltage terminal VGL is electrically connected to the first constant voltage line 11, and the low-level constant voltage is equal to the first constant voltage. That is, the first voltage terminal VGL and the shield metal layer 415 are supplied with voltages using the first constant voltage line 11. The number of signal lines is reduced by using the original wiring in the display driver circuit 10 to supply the voltage to the shield metal layer 415.

Alternatively, referring to fig. 4, the second voltage terminal VGH is electrically connected to the second constant voltage line 12, and the high-level constant voltage is equal to the second constant voltage. That is, the second voltage terminal VGH and the shield metal layer 415 are supplied with voltages using the second constant voltage line 12. The number of signal lines is reduced by using the original wiring in the display driving circuit 10 to supply the voltage to the shield metal layer 415.

Alternatively, referring to fig. 3, in the setting thin film transistor 410, a semiconductor layer 411 is positioned between the gate electrode 412 and the shield metal layer 415. Shield metal layer 415 is used to mitigate threshold voltage deviations resulting from long-term voltage application on gate 412.

Exemplarily, referring to fig. 3, the shift register 40 further includes at least one capacitor 42, and the capacitor 42 may be, for example, a first capacitor C1, a second capacitor C2, a third capacitor C3, or a fourth capacitor C4. The first plate 421 of the capacitor 42 is at the same level as the gate 412, and the second plate 422 of the capacitor 42 is located on the side of the first plate 421 away from the substrate 43.

Fig. 13 is a schematic cross-sectional view of another shift register according to an embodiment of the invention, referring to fig. 13, in which a gate 412 is located between a semiconductor layer 411 and a substrate 43, and a shielding metal layer 415 is on the same layer as a second plate 422 of a capacitor 42. Therefore, the same material can be used and the shielding metal layer 415 and the second plate 422 of the capacitor 42 can be formed simultaneously in the same process, thereby saving the process. In other embodiments, the shielding metal layer 415 may be on the same layer as the source 413 and the drain 414, and the shielding metal layer 415 and the source 413 and the drain 414 may be formed simultaneously in the same process.

Alternatively, the first constant voltage line 11 and/or the second constant voltage line 12 are on the same layer as the shield metal layer 415, so that the first constant voltage line 11 and/or the second constant voltage line 12 and the shield metal layer 415 may be formed simultaneously using the same material and in the same process, thereby saving process steps. On the other hand, the first constant voltage line 11 and the shield metal layer 415 are on the same layer, which facilitates electrical connection between the first constant voltage line 11 and the shield metal layer 415. The second constant voltage line 12 and the shield metal layer 415 are on the same layer, which facilitates electrical connection between the second constant voltage line 12 and the shield metal layer 415.

Fig. 14 is a schematic cross-sectional view of a display panel according to an embodiment of the invention, and referring to fig. 14, the display panel includes the array substrate in the embodiment. The display panel may be one of an organic light emitting display panel, a liquid crystal display panel, a quantum dot display panel, or a micro light emitting diode display panel.

Alternatively, referring to fig. 14, the display panel further includes a pixel driving circuit 61 located in the display region 01, an anode 621, and a via metal layer 63. The via metal layer 63 is located between the pixel driving circuit 61 and the anode 621, one end of the via metal layer 63 is electrically connected to the pixel driving circuit 61, and the other end of the via metal layer 63 is electrically connected to the anode 621. The gate 412 is located between the semiconductor layer 411 and the substrate 43, and the shielding metal layer 415 and the via metal layer 63 are on the same layer, so that the same material can be used, and the shielding metal layer 415 and the via metal layer 63 are formed simultaneously in the same process, thereby saving the process. In other embodiments, the shielding metal layer 415 is the same layer as the anode 621, so that the shielding metal layer 415 and the anode 621 can be formed simultaneously in the same process using the same material.

Exemplarily, referring to fig. 14, the display panel may be an organic light emitting display panel including the light emitting unit 62. The light emitting unit 62 includes an anode 621, a light emitting functional layer 622, and a cathode 623. The light emitting functional layer 622 is located between the anode 621 and the cathode 623, electrons and holes are injected into the light emitting functional layer 622 from the cathode 623 and the anode 621 respectively and are recombined to generate excitons, energy is transferred to light emitting molecules of the light emitting functional layer 622, and excited electrons are transited from a ground state to an excited state, and the energy of the excited state releases energy by means of radiative transition, so that light is generated.

Fig. 15 is a schematic view of a display device according to an embodiment of the present invention, and referring to fig. 15, the display device includes the display panel in the above embodiment. The display device may be one of a mobile phone, a computer, electronic paper, a vehicle-mounted display, a wearable device, and the like.

It is to be noted that the foregoing description is only exemplary of the invention and that the principles of the technology may be employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in some detail by the above embodiments, the invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the invention, and the scope of the invention is determined by the scope of the appended claims.

Claims

1. The array substrate is characterized by comprising a display area and a non-display area, wherein the non-display area is positioned at the periphery of the display area;

a substrate;

the first constant voltage line provides a first constant voltage with a voltage value less than 0V, and the second constant voltage line provides a second constant voltage with a voltage value greater than 0V;

2. The array substrate of claim 1, wherein the shift register comprises:

the pull-down unit is electrically connected with a first voltage end, a first node and a cascade signal output end and is used for transmitting a signal input by the first voltage end to the cascade signal output end under the control of the first node; the first voltage end provides a low-level constant voltage;

at least one of the thin film transistors in the pull-down unit is the setting thin film transistor.

3. The array substrate of claim 2, wherein the pull-down unit comprises a tenth transistor, a first terminal of the tenth transistor is electrically connected to the first voltage terminal, a second terminal of the tenth transistor is electrically connected to the cascade signal output terminal, and a gate of the tenth transistor is electrically connected to the first node;

the tenth transistor is the setting thin film transistor.

4. The array substrate of claim 1, wherein the shift register comprises:

the pull-up unit is electrically connected with a second voltage end, a second node and a cascade signal output end and is used for transmitting a signal input by the second voltage end to the cascade signal output end under the control of the second node; the second voltage end provides a high-level constant voltage;

the pull-up control unit is electrically connected with the second voltage end, the first clock signal input end, the second clock signal input end, the first node and the second node, and is used for transmitting a signal of the second voltage end or the second clock signal input end to the second node under the control of the first node and the second clock signal input end;

at least one of the thin film transistors in the pull-up control unit is the setting thin film transistor.

5. The array substrate of claim 4, wherein the pull-up control unit comprises a sixth transistor, a first terminal of the sixth transistor is electrically connected to the second voltage terminal, a second terminal of the sixth transistor is electrically connected to the second node, and a gate of the sixth transistor is electrically connected to the first node;

the sixth transistor is the setting thin film transistor.

6. The array substrate of claim 4, wherein the pull-up control unit comprises a second transistor, a third transistor and a seventh transistor;

a first end of the second transistor is electrically connected to the first clock signal input end, a second end of the second transistor is electrically connected to a gate of the third transistor, and the gate of the second transistor is electrically connected to the first node or a third node; the third node and the first node have the same voltage timing sequence;

a first end of the third transistor is electrically connected with a first end of the seventh transistor, and a second end of the third transistor is electrically connected with the second clock signal input end;

a gate of the seventh transistor is electrically connected to the second clock signal input terminal, and a second terminal of the seventh transistor is electrically connected to the second node;

the second transistor is the set thin film transistor.

7. The array substrate of claim 6, wherein the pull-up control unit further comprises a thirteenth transistor, a first terminal of the thirteenth transistor is electrically connected to the second voltage terminal, a second terminal of the thirteenth transistor is electrically connected to the first node, a gate of the thirteenth transistor is electrically connected to a power-on signal control terminal, and the power-on signal control terminal turns on the thirteenth transistor during a power-on period;

the thirteenth transistor is the setting thin film transistor.

8. The array substrate of claim 2, wherein the shift register comprises:

a pull-down control unit electrically connected to the first voltage terminal, the second voltage terminal, the first clock signal input terminal, the second clock signal input terminal, the cascade signal input terminal, and the first node, and configured to transmit a signal of the second voltage terminal or the cascade signal input terminal to the first node under the control of the first clock signal input terminal and the second clock signal input terminal; the second voltage end provides a high-level constant voltage;

at least one of the thin film transistors in the pull-down control unit is the setting thin film transistor.

9. The array substrate of claim 8, wherein the pull-down control unit comprises a first transistor, a fourth transistor, a fifth transistor, an eighth transistor and a second capacitor, wherein a first terminal of the first transistor is electrically connected to a first plate of the second capacitor, a second terminal of the first transistor is electrically connected to the second clock signal input terminal, and a gate of the first transistor is electrically connected to the first node;

a first end of the fourth transistor is electrically connected with the first node, a second end of the fourth transistor is electrically connected with the cascade signal input end, and a grid electrode of the fourth transistor is electrically connected with the first clock signal input end;

a first end of the fifth transistor is electrically connected with the first voltage end, a second end of the fifth transistor is electrically connected with a gate of the eighth transistor, and a control end of the fifth transistor is electrically connected with the first clock signal input end;

a first end of the eighth transistor is electrically connected with the second voltage end, and a second end of the eighth transistor is electrically connected with the first end of the first transistor;

a second plate of the second capacitor is electrically connected with the first node;

the first transistor is the setting thin film transistor.

10. The array substrate of claim 2, wherein the low level constant voltage is equal to the first constant voltage.

11. The array substrate according to claim 4 or 8, wherein the high level constant voltage is equal to the second constant voltage.

12. The array substrate of claim 1, wherein in the set TFT, the semiconductor layer is located between the gate electrode and the shielding metal layer.

13. The array substrate of claim 1, wherein the shift register further comprises at least one capacitor, a first plate of the capacitor is in the same layer as the gate, and a second plate of the capacitor is located on a side of the first plate away from the substrate;

the gate is located between the semiconductor layer and the substrate, and the shielding metal layer is on the same layer as the source and the drain, or the shielding metal layer is on the same layer as the second plate.

14. The array substrate of claim 1, wherein the first constant voltage line and/or the second constant voltage line is on a same layer as the shield metal layer.

15. A display panel comprising the array substrate according to any one of claims 1 to 14.

16. The display panel according to claim 15, further comprising a pixel driving circuit, an anode, and a via metal layer in the display region;

the switching metal layer is positioned between the pixel driving circuit and the anode, one end of the switching metal layer is electrically connected with the pixel driving circuit, and the other end of the switching metal layer is electrically connected with the anode;

the grid electrode is positioned between the semiconductor layer and the substrate, and the shielding metal layer and the transfer metal layer are on the same layer, or the shielding metal layer and the anode are on the same layer.

17. A display device characterized by comprising the display panel of claim 15 or 16.