CN114692554B - Conductive pad layout method, system, medium and equipment of quantum bit layout - Google Patents
Conductive pad layout method, system, medium and equipment of quantum bit layout Download PDFInfo
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Abstract
The invention discloses a conducting disc layout method, a conducting disc layout system, a conducting disc layout medium and conducting disc layout equipment for a quantum bit layout. The quantum bit layout comprises an electrode structure and a plurality of ion implantation layers positioned on the periphery of the electrode structure, the electrode structure comprises a plurality of first electrodes used for introducing carriers and a plurality of second electrodes used for regulating quantum bits, and the number of the first electrodes is equal to that of the ion implantation layers. The conductive pad layout method comprises the following steps: determining a limit frame between the electrode structure and the ion implantation layer; determining a plurality of first insertion points on the limiting frame according to the edge of each ion implantation layer nearest to the limiting frame; determining second insertion points at other positions except the first insertion points on the limiting frame, wherein the number of the second insertion points is equal to that of the second electrodes; a conductive pad for connecting the first electrodes is generated at each first insertion point and a conductive pad for connecting the second electrodes is generated at each second insertion point. The invention can automatically draw the conductive disc and can improve the efficiency and the accuracy of layout drawing.
Description
Technical Field
The invention relates to the field of circuit design, in particular to a conducting disc layout method, a conducting disc layout system, a conducting disc layout medium and conducting disc layout equipment for a quantum bit layout.
Background
The qubit is a key unit of the quantum chip, and the electrode on the qubit is very small in size, so that welding is difficult to realize in a process, and the electrode needs to be led out to a bonding pad with a larger size through a transmission line. The transmission line is usually a broken line, but since the transmission line is very thin, disconnection is easy to occur at the break point in the process preparation, and thus, a conductive disc needs to be manufactured at the break point to improve the conductive reliability at the break point of the transmission line.
However, the number of electrodes on the qubit is very large, each electrode is provided with a transmission line, and in the design of the qubit layout, the conductive plates are required to be added manually one by one, so that the layout drawing workload is very large, the layout drawing efficiency is very low, the drawing process cannot guarantee the accuracy, and the mistakes are easy to occur.
Disclosure of Invention
The invention aims to provide a conducting disc layout method, a system, a medium and equipment for a quantum bit layout, which are used for solving the problems of low manual drawing efficiency and easy error of a conducting disc in the prior art, and can automatically draw the conducting disc and improve the efficiency and the accuracy of layout drawing.
In order to solve the above technical problems, the present invention provides a conductive pad layout method of a qubit layout, where the qubit layout includes an electrode structure and a plurality of ion implantation layers located at the periphery of the electrode structure, the electrode structure includes a plurality of first electrodes for introducing carriers and a plurality of second electrodes for adjusting and controlling qubits, and the number of the first electrodes and the number of the ion implantation layers are equal, the conductive pad layout method includes:
Determining a limit frame between the electrode structure and the ion implantation layer;
Determining a plurality of first insertion points on the limiting frame according to the edge of each ion implantation layer nearest to the limiting frame;
determining second insertion points at other positions than the first insertion points on the limiting frame, wherein the number of the second insertion points is equal to that of the second electrodes;
Generating a conductive pad for connecting the first electrode at each of the first insertion points, generating a conductive pad for connecting the second electrode at each of the second insertion points,
Preferably, the limit frame is a rectangular frame.
Preferably, the step of determining a plurality of first insertion points on the limiting frame according to an edge of each of the ion implantation layers nearest to the limiting frame includes:
selecting any point on the edge of each ion implantation layer closest to the limiting frame as a datum point;
and searching a first intersection point between the perpendicular line from each datum point to the limiting frame and the limiting frame, and taking the intersection point as a first insertion point.
Preferably, the reference point is a midpoint on an edge of the ion implantation layer closest to the limiting frame.
Preferably, the second electrode comprises a first sub-electrode and a second sub-electrode, the first sub-electrode is positioned between two adjacent first electrodes, and the second sub-electrode is not positioned between any two adjacent first electrodes;
The step of determining a second insertion point at other positions than the first insertion point on the limit frame includes:
determining the first electrode with each first insertion point nearest to the first electrode;
determining the same number of second insertion points on a limiting frame section between the first insertion points corresponding to the current two adjacent first electrodes according to the number of first sub-electrodes between the current two adjacent first electrodes;
And determining the second insertion points corresponding to the second sub-electrodes on the limit frame section with the minimum number of the second insertion points corresponding to the first sub-electrodes.
Preferably, the connection line from the second insertion point corresponding to the first sub-electrode on each limiting frame section to the center point of the electrode structure carries out angle average division on the sector area formed by the first insertion point on the current limiting frame section and the center point of the electrode structure.
Preferably, the connection line from the second insertion point corresponding to the second sub-electrode on each limiting frame section to the center point of the electrode structure carries out angle average division on the sector area formed by the first insertion point on the current limiting frame section and the center point of the electrode structure.
Preferably, a connection line from the second insertion point corresponding to the second sub-electrode on each limiting frame section to the center point of the electrode structure is perpendicular to the current limiting frame section.
Preferably, the conductive disc is rectangular, and a center point of the conductive disc is the first insertion point or the second insertion point.
Preferably, the conductive pad layout method further includes:
Transmission lines are generated between each of the first electrodes and the corresponding conductive pad and between each of the second electrodes and the corresponding conductive pad.
Preferably, a transmission line connected to the conductive pad is connected to a center point of the conductive pad, a transmission line connected to the first electrode is connected to a center point of the first electrode, and a transmission line connected to the second electrode is connected to a center point of the second electrode.
Preferably, the transmission lines are straight lines, and the transmission lines located in the same wiring layer do not cross.
In order to solve the above technical problem, the present invention further provides a conductive pad layout system of a qubit layout, where the qubit layout includes an electrode structure and a plurality of ion implantation layers located at the periphery of the electrode structure, the electrode structure includes a plurality of first electrodes for introducing carriers and a plurality of second electrodes for adjusting and controlling qubits, and the number of the first electrodes and the number of the ion implantation layers are equal, and the conductive pad layout system includes:
The first determining module is used for determining a limit frame between the electrode structure and the ion implantation layer;
the second determining module is used for determining a plurality of first insertion points on the limiting frame according to the edge, closest to the limiting frame, of each ion implantation layer;
a third determining module, configured to determine a second insertion point at other positions than the first insertion point on the limiting frame, where the number of the second insertion points is equal to the number of the second electrodes;
And the pattern generation module is used for generating a conductive disc for connecting the first electrodes at each first insertion point and generating a conductive disc for connecting the second electrodes at each second insertion point.
Preferably, the pattern generation module is further configured to generate a transmission line between each of the first electrodes and the corresponding conductive pad and between each of the second electrodes and the corresponding conductive pad.
To solve the above technical problem, the present invention further provides a storage medium, in which a computer program is stored, the computer program being configured to execute the conductive pad layout method of any one of the above-mentioned qubit layouts when running.
To solve the above technical problem, the present invention further provides an electronic device, including a memory and a processor, where the memory stores a computer program, and the processor is configured to run the computer program to execute the conductive pad layout method of the qubit layout described in any one of the foregoing.
Compared with the prior art, the conducting disc layout method of the quantum bit layout is characterized in that for the quantum bit layout with the electrode structure and the ion implantation layers, a limiting frame is firstly determined between the electrode structure and the ion implantation layers, a first insertion point is determined on the limiting frame according to the edge of each ion implantation layer closest to the limiting frame, then a second insertion point is determined on the limiting frame, finally a conducting disc for connecting a first electrode is generated at each first insertion point, a conducting disc for connecting a second electrode is generated at each second insertion point, and drawing of the conducting disc is completed.
The conducting disc layout system, the storage medium and the electronic equipment of the quantum bit layout provided by the invention belong to the same conception as the conducting disc layout method of the quantum bit layout, so that the conducting disc layout system and the storage medium have the same beneficial effects and are not repeated herein.
Drawings
Fig. 1 is a schematic diagram of a qubit layout.
Fig. 2 is an enlarged schematic view of an electrode structure of the qubit layout of fig. 1.
Fig. 3 is a flow chart of a conductive pad layout method of a qubit layout according to a first embodiment of the present invention.
Fig. 4 is a schematic view of a limit frame determined by the conductive pad layout method shown in fig. 3.
Fig. 5 is a schematic view of a first insertion point and a second insertion point determined by the conductive pad layout method shown in fig. 3.
Fig. 6 is a schematic diagram of a conductive pad generated by the conductive pad layout method shown in fig. 3.
Fig. 7 is a schematic diagram of a transmission line connected to a first electrode and a second electrode generated by the conductive pad layout method shown in fig. 3.
Fig. 8 is a schematic flowchart of step S12 in a conductive pad layout method of a qubit layout according to a second embodiment of the present invention.
Fig. 9 is a schematic flowchart of step S13 in a conductive pad layout method of a qubit layout according to a second embodiment of the present invention.
Fig. 10 is a schematic block diagram of a conductive pad layout system of a qubit layout according to a third embodiment of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. Advantages and features of the invention will become more apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
The first embodiment of the invention provides a conducting disc layout method of a quantum bit layout. The quantum bit layout comprises an electrode structure and a plurality of ion implantation layers positioned on the periphery of the electrode structure, the electrode structure comprises a plurality of first electrodes used for introducing carriers and a plurality of second electrodes used for regulating quantum bits, and the number of the first electrodes is equal to that of the ion implantation layers. Referring to fig. 1 and 2, in one specific example, the qubit layout includes an electrode structure 1 and 6 ion implantation layers 2 located at the periphery of the electrode structure, where the electrode structure 1 includes 6 first electrodes 11 for introducing carriers and 21 second electrodes 12 for modulating the qubits. In fig. 2, the second electrodes 12 are formed differently from the shadow filling of the first electrodes 11. The ion implantation layer is of a polygonal structure, the shape of the ion implantation layer is formed by combining a conical-like shape and a rectangular shape, some ion implantation layers are 7-sided shapes, and some ion implantation layers are 8-sided shapes.
Referring to fig. 3, the conductive pad layout method of the present embodiment includes:
S11: a confinement frame is defined between the electrode structure and the ion implantation layer.
Wherein, referring to fig. 4 in combination, the spacing frame 3 is located between the electrode structure and the ion implantation layer. After the limiting frame 3 is determined, the electrode structure 1 is positioned in the limiting frame 3, and the ion implantation layer 2 is positioned outside the limiting frame 3. The limit frame 3 can be drawn manually by a user, can be provided by a qubit layout, and can be generated according to parameters input by the user. For example, the user inputs the coordinates of each vertex of the limit frame, and then sequentially connects each vertex in a preset order to determine the limit frame.
The limit frame may be any shape composed of line segments, and in general, the number of sides of the limit frame is as small as possible. In this embodiment, the limiting frame is a rectangular frame.
S12: and determining a plurality of first insertion points on the limiting frame according to the edge of each ion implantation layer nearest to the limiting frame.
The ion implantation layer must have a side nearest to the limiting frame no matter what shape the ion implantation layer is. Referring to fig. 5, the edge of each ion implantation layer closest to the limit frame is the edge with the shortest similar cone area, and 6 first insertion points a can be respectively determined on the limit frame according to the shortest edge of each ion implantation layer.
S13: and determining second insertion points at other positions except the first insertion points on the limiting frame, wherein the number of the second insertion points is equal to that of the second electrodes.
The limiting frame is divided into 6 limiting frame sections by 6 first insertion points A, and 21 second insertion points B can be determined on the 6 limiting frame sections according to a set rule. Referring to fig. 5 in combination, 21 second insertion points B are dispersed on different spacing frame segments, with the second insertion points B on each spacing frame segment being evenly distributed. In fig. 5, the points other than the first insertion point a are the second insertion points B.
S14: a conductive pad for connecting the first electrodes is generated at each first insertion point and a conductive pad for connecting the second electrodes is generated at each second insertion point.
Referring to fig. 6, the first insertion point a and the second insertion point B both generate the same conductive pad C, except that the conductive pad C generated at the first insertion point a needs to be connected to the first electrode 11, and the conductive pad C generated at the second insertion point B needs to be connected to the second electrode 12.
Since the transmission line needs to be drawn to connect the conductive pad with the first electrode and the second electrode, in order to improve the layout drawing efficiency, in this embodiment, the conductive pad layout method further includes:
S15: a transmission line is generated between each first electrode and the corresponding conductive pad and between each second electrode and the corresponding conductive pad.
In order to avoid the phenomenon that the transmission line and the conductive disc are disconnected in the subsequent chip process preparation process, in the embodiment, the transmission line connected with the conductive disc is connected with the center point of the conductive disc, the transmission line connected with the first electrode is connected with the center point of the first electrode, and the transmission line connected with the second electrode is connected with the center point of the second electrode. Further, the transmission lines are straight lines, and the transmission lines on the same wiring layer do not cross. If the transmission lines need to be crossed, the crossed transmission lines are respectively positioned on different wiring layers.
As shown in an enlarged portion of fig. 6 and fig. 7, a transmission line Z connected to the conductive pad C is connected to the center point of the conductive pad C, a transmission line Z connected to the first electrode 11 is connected to the center point of the first electrode 11, and a transmission line Z connected to the second electrode 12 is connected to the center point of the second electrode 12. It should be noted that only a part of the transmission line Z is schematically shown in fig. 6 and 7.
In this embodiment, the conductive pads C are rectangular, and the center point of each conductive pad C is the first insertion point a or the second insertion point B, that is, the center point of each conductive pad C is on the limit frame 3.
Through the steps, the embodiment can determine the limit frame between the electrode structure and the ion implantation layer, determine the first insertion point on the limit frame according to the edge of the ion implantation layer, then further determine the second insertion point, and realize layout construction of the conductive disc by using the first insertion point and the second insertion point.
The second embodiment of the invention provides a conducting disc layout method of a quantum bit layout. The layout construction method of the present embodiment includes all the technical features of the first embodiment, except that referring to fig. 8, the step of determining a plurality of first insertion points on the limiting frame according to the edge of each ion implantation layer closest to the limiting frame, that is, step S12 includes:
S121: and selecting any point on the edge of each ion implantation layer closest to the limit frame as a reference point.
In this embodiment, the reference point is a midpoint of an edge of the ion implantation layer closest to the stop frame. Referring to fig. 4 in combination, a midpoint M of an edge of the ion implantation layer closest to the limiting frame is a reference point.
S122: and searching a first intersection point between the perpendicular line from each datum point to the limiting frame and the limiting frame, and taking the intersection point as a first insertion point.
Referring to fig. 4, an intersection point exists between a perpendicular line (a broken line in the drawing) from the reference point (i.e., the middle point M) to the limit frame and the limit frame, and the first intersection point is taken as a first insertion point a.
The third embodiment of the invention provides a conducting disc layout method of a quantum bit layout. In the present embodiment, the second electrode 12 includes the first sub-electrode 121 and the second sub-electrode 122, the first sub-electrode 121 is located between two adjacent first electrodes 11, and the second sub-electrode 122 is not located between any two adjacent first electrodes 11. As shown in fig. 2, the remaining second electrodes 12 are first sub-electrodes 121 except for the noted second sub-electrode 122.
The layout construction method of the present embodiment includes all the technical features of the first embodiment, except that referring to fig. 9, the step of determining the second insertion point at other positions than the first insertion point on the limit frame, that is, step S13 includes:
s131: each first electrode having a first insertion point nearest to the first electrode is determined.
With reference to fig. 2, 5 and 7, according to the positions of the 6 first electrodes 11 and the positions of the 6 first insertion points a, the two first insertion points a at the upper edge of the limiting frame 3 correspond to the upper left and right first electrodes 11 in the electrode structure 1 in the left-right order, the two first insertion points a at the left edge of the limiting frame 3 correspond to the upper left and lower first electrodes 11 in the electrode structure 1 in the up-down order, and the two first insertion points a at the lower edge of the limiting frame 3 correspond to the lower left and right first electrodes 11 in the electrode structure 1 in the left-right order.
S132: and determining the second inserting points with the same number on the limiting frame section between the first inserting points corresponding to the current two adjacent first electrodes according to the number of the first sub-electrodes between the current two adjacent first electrodes.
Wherein, referring to fig. 5 in combination, the 6 first insertion points a divide the limit frame 3 into 6 limit frame segments. Taking the two adjacent first electrodes 11 on the right side in fig. 2 as an example, the number of first sub-electrodes 11 between the two adjacent first electrodes 11 is 11, it is necessary to determine 11 second insertion points B on the spacing frame section between the first insertion points a corresponding to the two adjacent first electrodes 11, that is, the number of second insertion points B on the spacing frame section on the right most side in fig. 5 is 11.
S133: and determining the second insertion points corresponding to the second sub-electrodes on the limit frame section with the minimum number of the second insertion points corresponding to the first sub-electrodes.
Referring to fig. 5, after the second insertion points B corresponding to the first sub-electrodes 121 are determined, only the second insertion points B on the uppermost, leftmost and lowermost limiting frame sections remain the least, and therefore, the second insertion points B corresponding to the second sub-electrodes 122 are determined on the three limiting frame sections. In this embodiment, the uppermost and lowermost limiting frame sections are selected to determine a second insertion point B, and thus the second insertion points B corresponding to all the second electrodes 12 are finally determined.
For the situation that the number of the second insertion points on the limiting frame sections is two or more, as a preferred implementation manner, the connection line from the second insertion point corresponding to the first sub-electrode on each limiting frame section to the central point of the electrode structure carries out angle average division on the sector area formed by the first insertion point on the current limiting frame section and the central point of the electrode structure. As shown in fig. 5, the two first insertion points a plus 11 second insertion points B on the rightmost bounding frame section add 13 points in total, and the included angles between every two adjacent connecting lines are equal in the connecting lines from 13 points to the center point of the electrode structure.
In the case that the number of the second insertion points on the limiting frame section is one, as a preferred implementation manner, the connection line from the second insertion point corresponding to the second sub-electrode on each limiting frame section to the center point of the electrode structure carries out angle average segmentation on the sector area formed by the first insertion point on the current limiting frame section and the center point of the electrode structure.
In the case that the number of the second insertion points on the limiting frame section is one, as another preferred embodiment, a connection line from the second insertion point corresponding to the second sub-electrode on each limiting frame section to the central point of the electrode structure is perpendicular to the current limiting frame section. As shown in fig. 5, there are only 1 second insertion points B between the two first insertion points a on the lowermost limit frame section, and the connection line from the second insertion point B to the center point of the electrode structure is perpendicular to the lower edge of the limit frame.
The third embodiment of the invention provides a conducting disc layout system of a quantum bit layout. The quantum bit layout comprises an electrode structure and a plurality of ion implantation layers positioned on the periphery of the electrode structure, the electrode structure comprises a plurality of first electrodes used for introducing carriers and a plurality of second electrodes used for regulating quantum bits, and the number of the first electrodes is equal to that of the ion implantation layers. Referring to fig. 10, the conductive pad layout system includes:
A first determining module 11 for determining a confinement frame between the electrode structure and the ion implantation layer. The limit frame can be drawn manually by a user, can be provided by a quantum bit layout, and can be generated according to parameters input by the user. For example, the user inputs the coordinates of each vertex of the limit frame, and then sequentially connects each vertex in a preset order to determine the limit frame. The limit frame may be any shape composed of line segments, and in general, the number of sides of the limit frame is as small as possible. In this embodiment, the limiting frame is a rectangular frame.
The second determining module 12 is configured to determine a plurality of first insertion points on the limiting frame according to an edge of each ion implantation layer closest to the limiting frame. The ion implantation layer must have a side nearest to the limiting frame no matter what shape the ion implantation layer is.
And the third determining module 13 is used for determining second insertion points at other positions except the first insertion points on the limiting frame, wherein the number of the second insertion points is equal to that of the second electrodes. The first insertion points divide the limit frame into a plurality of limit frame sections, and the second insertion points can be determined on the limit frame sections according to a set rule.
The pattern generation module 14 is configured to generate a conductive pad for connecting the first electrode at each first insertion point and generate a conductive pad for connecting the second electrode at each second insertion point. The pattern generation module 14 generates the same conductive pad at both the first insertion point and the second insertion point, wherein the conductive pad generated at the first insertion point needs to be connected to the first electrode, and the conductive pad generated at the second insertion point needs to be connected to the second electrode.
Since the transmission lines need to be drawn to connect the conductive pads with the first electrodes and the second electrodes, in order to improve the layout drawing efficiency, in this embodiment, the pattern generating module 14 is further configured to generate the transmission lines between each first electrode and the corresponding conductive pad and between each second electrode and the corresponding conductive pad. In order to avoid the phenomenon that the transmission line and the conductive disc are disconnected in the subsequent chip process preparation process, in the embodiment, the transmission line connected with the conductive disc is connected with the center point of the conductive disc, the transmission line connected with the first electrode is connected with the center point of the first electrode, and the transmission line connected with the second electrode is connected with the center point of the second electrode. Further, the transmission lines are straight lines, and the transmission lines on the same wiring layer do not cross. If the transmission lines need to be crossed, the crossed transmission lines are respectively positioned on different wiring layers.
In this embodiment, the conductive plates are rectangular, and the center point of each conductive plate is the first insertion point or the second insertion point, that is, the center point of each conductive plate is on the limiting frame.
The present invention also provides a storage medium having stored therein a computer program arranged to perform the conducting disc layout method of the qubit layout of the first or second embodiment when run.
Specifically, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
The invention also provides an electronic device comprising a memory in which a computer program is stored, and a processor arranged to run the computer program to perform the conductive pad layout method of the qubit layout of the first or second embodiment.
In particular, the memory and the processor may be connected by a data bus. In addition, the electronic device may further include a transmission device connected to the processor, and an input/output device connected to the processor.
In the description of the present specification, a description of the terms "one embodiment," "some embodiments," "examples," or "particular examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (16)
1. A conductive pad layout method of a qubit layout, the qubit layout including an electrode structure and a plurality of ion implantation layers located at a periphery of the electrode structure, the electrode structure including a plurality of first electrodes for introducing carriers and a plurality of second electrodes for regulating and controlling the qubits, and the number of the first electrodes and the number of the ion implantation layers being equal, the conductive pad layout method comprising:
Determining a limit frame between the electrode structure and the ion implantation layer;
Determining a plurality of first insertion points corresponding to each first electrode on the limiting frame according to the edge of each ion implantation layer nearest to the limiting frame;
determining second insertion points at other positions than the first insertion points on the limiting frame, wherein the number of the second insertion points is equal to that of the second electrodes;
A conductive pad for connecting the first electrodes is generated at each of the first insertion points, and a conductive pad for connecting the second electrodes is generated at each of the second insertion points.
2. The conductive pad layout method according to claim 1, wherein the stopper frame is a rectangular frame.
3. The conductive pad layout method according to claim 2, wherein the step of determining a plurality of first insertion points corresponding to each of the first electrodes on the stopper frame according to an edge of each of the ion implantation layers nearest to the stopper frame comprises:
selecting any point on the edge of each ion implantation layer closest to the limiting frame as a datum point;
and searching a first intersection point between the perpendicular line from each datum point to the limiting frame and the limiting frame, and taking the intersection point as a first insertion point.
4. The conductive pad layout method according to claim 3, wherein the reference point is a midpoint on an edge of the ion implantation layer closest to the stopper.
5. The conductive pad layout method according to claim 1, wherein the second electrode includes a first sub-electrode and a second sub-electrode, the first sub-electrode being located between adjacent two of the first electrodes, the second sub-electrode not being located between any adjacent two of the first electrodes;
The step of determining a second insertion point at other positions than the first insertion point on the limit frame includes:
determining the first electrode with each first insertion point nearest to the first electrode;
determining the same number of second insertion points on a limiting frame section between the first insertion points corresponding to the current two adjacent first electrodes according to the number of first sub-electrodes between the current two adjacent first electrodes;
And determining the second insertion points corresponding to the second sub-electrodes on the limit frame section with the minimum number of the second insertion points corresponding to the first sub-electrodes.
6. The method of patterning conductive pads of claim 5, wherein a line from a second insertion point corresponding to the first sub-electrode on each of the stopper frame segments to a center point of the electrode structure equally divides a sector area formed by the first insertion point on the current stopper frame segment and the center point of the electrode structure.
7. The method of patterning conductive pads according to claim 5, wherein a line from a second insertion point corresponding to the second sub-electrode on each of the limiting frame segments to a center point of the electrode structure equally divides a sector area formed by the first insertion point on the current limiting frame segment and the center point of the electrode structure.
8. The conductive pad layout method according to claim 5, wherein a line from a second insertion point corresponding to the second sub-electrode on each of the stopper frame segments to a center point of the electrode structure is perpendicular to the current stopper frame segment.
9. The conductive pad layout method according to claim 1, wherein the conductive pad is rectangular, and a center point of the conductive pad is the first insertion point or the second insertion point.
10. The conductive pad layout method according to claim 1, further comprising:
Transmission lines are generated between each of the first electrodes and the corresponding conductive pad and between each of the second electrodes and the corresponding conductive pad.
11. The conductive pad layout method according to claim 10, wherein a transmission line connected to the conductive pad is connected to a center point of the conductive pad, a transmission line connected to the first electrode is connected to a center point of the first electrode, and a transmission line connected to the second electrode is connected to a center point of the second electrode.
12. The conductive pad layout method according to claim 10, wherein the transmission lines are straight lines and the transmission lines on the same wiring layer do not intersect.
13. A conductive pad layout system of a qubit layout, the qubit layout including an electrode structure and a plurality of ion implantation layers located at a periphery of the electrode structure, the electrode structure including a plurality of first electrodes for introducing carriers and a plurality of second electrodes for regulating and controlling the qubits, and the number of the first electrodes and the ion implantation layers being equal, the conductive pad layout system comprising:
The first determining module is used for determining a limit frame between the electrode structure and the ion implantation layer;
The second determining module is used for determining a plurality of first insertion points corresponding to each first electrode on the limiting frame according to the edge of each ion implantation layer nearest to the limiting frame;
a third determining module, configured to determine a second insertion point at other positions than the first insertion point on the limiting frame, where the number of the second insertion points is equal to the number of the second electrodes;
And the pattern generation module is used for generating a conductive disc for connecting the first electrodes at each first insertion point and generating a conductive disc for connecting the second electrodes at each second insertion point.
14. The conductive pad layout system of claim 13, wherein the pattern generation module is further configured to generate transmission lines between each of the first electrodes and the corresponding conductive pad and between each of the second electrodes and the corresponding conductive pad.
15. A storage medium having stored therein a computer program arranged to perform the method of conducting disc patterning of a qubit layout according to any one of claims 1 to 12 when run.
16. An electronic device comprising a memory and a processor, the memory having stored therein a computer program, the processor being arranged to run the computer program to perform the conductive pad layout method of the qubit layout of any one of claims 1 to 12.
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| PCT/CN2023/084516 WO2023185882A1 (en) | 2022-03-31 | 2023-03-28 | Layout construction method and system for semiconductor qubit layout, medium, and device |
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