CN114299863A

CN114299863A - Signal generating circuit, scanning circuit, display panel and display device

Info

Publication number: CN114299863A
Application number: CN202111669545.8A
Authority: CN
Inventors: 翟应腾
Original assignee: Hubei Changjiang New Display Industry Innovation Center Co Ltd
Current assignee: Hubei Changjiang New Display Industry Innovation Center Co Ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2022-04-08
Anticipated expiration: 2041-12-31
Also published as: CN114299863B

Abstract

The invention provides a signal generating circuit, a scanning circuit, a display panel and a display device. In the display panel provided by the invention, the initial time of the pulse width control voltage generated by at least one signal generation circuit in all the signal generation circuits is different from the initial time of the pulse width control voltage generated by the rest signal generation circuits, so that all the pixel drive circuits of the display panel can not light the light-emitting elements initially, the condition that the voltage drop of the signal lines connected with the pixel drive circuits is overlarge when all the light-emitting elements are lighted at the same initial time is avoided, the stability of the pixel drive circuits is further improved, and the display effect of the display panel is improved.

Description

Signal generating circuit, scanning circuit, display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a signal generating circuit, a scanning circuit, a display panel, and a display device.

Background

With the increasing demand for display devices, the self-luminous display devices have been widely used in various electronic devices, including computers and mobile phones, due to their advantages of self-luminous, light and thin, low power consumption, high contrast, high color gamut, and flexible display. The self-luminous elements in the existing self-luminous display devices are generally Organic Light Emitting Diodes (OLEDs), Quantum Dot Light Emitting Diodes (QLEDs), Micro Light Emitting Diodes (Micro LEDs), and the like; in actual display, the pixel driving circuit refers to the pulse width control voltage as the ramp voltage and outputs the driving current to drive the light emitting element to emit light, so that the display device achieves the purpose of image display.

Disclosure of Invention

In view of this, the present invention provides a signal generating circuit, a scanning circuit, a display panel and a display device, which improve the stability of the signal generating circuit and improve the display effect of the display panel.

In order to achieve the purpose, the technical scheme provided by the invention is as follows:

a signal generating circuit comprising: the charging device comprises a constant current source, an access unit, a voltage holding unit, a charging unit and a charging and discharging capacitor;

the access unit is used for responding to and generating a control signal and communicating the constant current source with a first polar plate of the charge-discharge capacitor, the first polar plate of the charge-discharge capacitor is electrically connected with the output end of the signal generating circuit, and a second polar plate of the charge-discharge capacitor is electrically connected with a grounding end;

the voltage holding unit is used for responding to a holding control signal and electrically connecting a grounding end with the first polar plate of the charge-discharge capacitor;

the charging unit is used for responding to a charging control signal and transmitting a charging voltage to a first polar plate of the charging and discharging capacitor.

Optionally, the access unit includes an access transistor, a first end of the access transistor is electrically connected to the constant current source, a second end of the access transistor is electrically connected to the first electrode plate of the charge and discharge capacitor, and a gate of the access transistor is connected to the generation control signal;

the voltage holding unit comprises at least one holding transistor, wherein a first end of the holding transistor is electrically connected with a grounding end, a second end of the holding transistor is electrically connected with a first plate of the charge-discharge capacitor, and a grid electrode of the holding transistor is connected with the holding control signal;

the charging unit comprises a charging transistor, the first end of the charging transistor is connected to the charging voltage, the second end of the charging transistor is electrically connected with the first polar plate of the charging and discharging capacitor, and the grid electrode of the charging transistor is connected to the charging control signal.

Optionally, the signal generating circuit further includes: and the voltage stabilizing unit is electrically connected between the first polar plate of the charge and discharge capacitor and the output end of the signal generating circuit.

Optionally, the voltage stabilizing unit includes an operational amplifier, a non-inverting terminal of the operational amplifier is electrically connected to the first electrode plate of the charge-discharge capacitor, and an inverting terminal of the operational amplifier and an output terminal of the operational amplifier are electrically connected to an output terminal of the signal generating circuit.

Accordingly, the present invention also provides a scan circuit, comprising: a first signal generating circuit to an Nth signal generating circuit, any one of which is the above-mentioned signal generating circuit, N is an integer greater than or equal to 2;

in the first to nth signal generating circuits, an initial time when at least one of the signal generating circuits is switched in the active level of the generation control signal is different from initial times when the other signal generating circuits are switched in the active level of the generation control signal.

Correspondingly, the invention also provides a display panel, comprising:

a plurality of pixel driving circuit groups including a signal generating circuit and a pixel driving circuit;

the pixel circuit driving circuit comprises a pulse width modulation unit, a first light emitting control unit and a driving transistor; the pulse width modulation unit is used for outputting a pulse width setting signal by referring to the pulse width control voltage; the first light-emitting control unit is used for responding to a first light-emitting control signal and transmitting the pulse width setting signal to the grid electrode of the driving transistor;

the signal generating circuit is used for responding to the first light-emitting control signal and generating the pulse width control voltage; the initial time of the pulse width control voltage generated by at least one of the signal generating circuits in all the signal generating circuits is different from the initial time of the pulse width control voltage generated by the rest of the signal generating circuits.

Optionally, the signal generating circuit includes: the charging device comprises a constant current source, an access unit, a voltage holding unit, a charging unit and a charging and discharging capacitor;

the access unit is used for responding to the first light-emitting control signal and communicating the constant current source with a first polar plate of the charge-discharge capacitor, the first polar plate of the charge-discharge capacitor is electrically connected with the output end of the signal generating circuit, and a second polar plate of the charge-discharge capacitor is electrically connected with a grounding end;

Optionally, the access unit includes an access transistor, a first end of the access transistor is electrically connected to the constant current source, a second end of the access transistor is electrically connected to a first electrode plate of the charge and discharge capacitor, and a gate of the access transistor is connected to the first lighting control signal;

Optionally, the pulse width modulation unit is connected to a first control signal, a second control signal and the first light emitting control signal, and the pulse width modulation unit is configured to connect to a reset voltage in response to the first control signal, connect to a first data voltage in response to the second control signal, and connect to a turn-off voltage in response to the first light emitting control signal;

the display panel comprises N rows of pixel driving circuits, a first control signal of a pixel circuit in an i +1 th row and a second control signal of a pixel circuit in an i-th row are the same control signal, N is an integer larger than or equal to 2, and i is a positive integer smaller than N.

Optionally, the signal generating circuit includes the constant current source, the accessing unit, the voltage holding unit, the charging unit and the charging/discharging capacitor, the accessing unit includes the accessing transistor, the voltage holding unit includes at least one holding transistor, and the charging unit includes the charging transistor;

the pixel driving circuit group comprises M rows of pixel driving circuits, wherein the voltage holding unit comprises a first holding transistor to an M +1 th holding transistor, the holding control signal comprises a first sub-holding control signal to an M +1 th sub-holding control signal, the gate of the jth holding transistor is connected with the jth sub-holding control signal, M is an integer greater than or equal to 1, and j is a positive integer less than or equal to M + 1.

Optionally, when M is equal to 1, or when M is greater than 1 and the pixel driving circuits of M rows are adjacent rows:

the kth sub-holding control signal and a first control signal of the pixel driving circuit of the kth row are the same signal, the M +1 th sub-holding control signal and a second control signal of the pixel driving circuit of the Mth row are the same signal, and k is a positive integer less than or equal to M;

and the charging control signal of the current pixel driving circuit group and the second control signal of the pixel driving circuit of the next pixel driving circuit group and the adjacent first row are the same signal.

Optionally, M is greater than 1 and at least one of the M rows of pixel driving circuits is located in a different row from the rest of the pixel driving circuits.

Optionally, the pixel driving circuit includes a light emitting element and further includes a light emitting reset unit, and the light emitting reset unit is configured to transmit the reset voltage to the light emitting element in response to the second control signal.

Correspondingly, the invention further provides a display device which comprises the display panel.

Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:

the invention provides a signal generating circuit, a scanning circuit, a display panel and a display device, comprising: the charging device comprises a constant current source, an access unit, a voltage holding unit, a charging unit and a charging and discharging capacitor; the access unit is used for responding to and generating a control signal and communicating the constant current source with a first polar plate of the charge-discharge capacitor, the first polar plate of the charge-discharge capacitor is electrically connected with the output end of the signal generating circuit, and a second polar plate of the charge-discharge capacitor is electrically connected with a grounding end; the voltage holding unit is used for responding to a holding control signal and electrically connecting a grounding end with the first polar plate of the charge-discharge capacitor; the charging unit is used for responding to a charging control signal and transmitting a charging voltage to a first polar plate of the charging and discharging capacitor. The signal generating circuit provided by the invention firstly resets and stabilizes the charging and discharging capacitor through the voltage holding unit, then charges the charging and discharging capacitor through the charging unit, and finally the access unit communicates the constant current source with the first polar plate of the charging and discharging capacitor to generate the slope voltage under the action of the discharging process of the charging and discharging capacitor. Therefore, the voltage holding unit provided by the invention can reset and stabilize the charging and discharging capacitor, and the stability of the signal generating circuit is improved.

In the display panel provided by the invention, the initial time of the pulse width control voltage generated by at least one signal generation circuit in all the signal generation circuits is different from the initial time of the pulse width control voltage generated by the rest signal generation circuits, so that all the pixel drive circuits of the display panel can not light the light-emitting elements initially, the condition that the voltage drop of the signal lines connected with the pixel drive circuits is overlarge when all the light-emitting elements are lighted at the same initial time is avoided, the stability of the pixel drive circuits is further improved, and the display effect of the display panel is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a signal generating circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another signal generating circuit according to an embodiment of the present invention;

FIG. 3 is a timing diagram of a signal generating circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a constant current source according to an embodiment of the present invention;

fig. 5 is a timing diagram of a constant current source according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a signal generating circuit according to another embodiment of the present invention;

FIG. 7 is a schematic diagram of a signal generating circuit according to another embodiment of the present invention;

fig. 8 is a schematic structural diagram of a scan circuit according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the invention;

fig. 11 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the invention;

FIG. 12 is a timing diagram of a pixel driving circuit according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of a pixel driving circuit group according to an embodiment of the invention;

FIG. 14 is a timing diagram of a pixel driving circuit group according to an embodiment of the present invention;

fig. 15 is a schematic structural diagram of two adjacent pixel driving circuit groups according to an embodiment of the present invention;

FIG. 16 is a timing diagram of two adjacent pixel driving circuit groups according to an embodiment of the present invention;

fig. 17 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the invention;

fig. 18 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As background art shows, the demand for display devices has been increasing with the increase of display technology, and among various display technologies, self-luminous display devices have been widely used in various electronic devices including electronic products such as computers and mobile phones due to their advantages of self-luminescence, lightness, thinness, low power consumption, high contrast, high color gamut, and flexible display. The self-luminous elements in the existing self-luminous display devices are generally organic light-emitting diodes, quantum dot light-emitting diodes, micro light-emitting diodes and the like; in actual display, the pixel driving circuit refers to the pulse width control voltage as the ramp voltage and outputs the driving current to drive the light emitting element to emit light, so that the display device achieves the purpose of image display.

Accordingly, the embodiment of the invention provides a signal generating circuit, a scanning circuit, a display panel and a display device, which improve the stability of the signal generating circuit and improve the display effect of the display panel.

To achieve the above object, the technical solutions provided by the embodiments of the present invention are described in detail below, specifically with reference to fig. 1 to 18. For convenience of explanation, the transistors in each circuit structure provided in the following embodiments of the present invention are described by taking P-type transistors as examples.

Referring to fig. 1, a schematic structural diagram of a signal generating circuit according to an embodiment of the present invention is shown, where the signal generating circuit according to the embodiment of the present invention includes:

the charging device comprises a constant current source 110, an access unit 120, a voltage holding unit 130, a charging unit 140 and a charging and discharging capacitor 150.

The access unit 120 is configured to respond to a generated control signal Kj to communicate the constant current source 110 with a first plate of the charge and discharge capacitor 150, where the first plate of the charge and discharge capacitor 150 is electrically connected with the output terminal OUT of the signal generating circuit, and a second plate of the charge and discharge capacitor 150 is electrically connected with a ground terminal GND.

The voltage holding unit 130 is configured to electrically connect the ground GND to the first plate of the charge and discharge capacitor 150 in response to a holding control signal Kb.

The charging unit 140 is configured to transmit a charging voltage Vc to the first plate of the charging and discharging capacitor 150 in response to the charging control signal Kc, where the charging and discharging voltage Vc is greater than the voltage of the ground terminal GND, and if the voltage of the ground terminal GND is 0V, the voltage of the charging and discharging voltage Vc may be 6V, which is not limited in this disclosure.

The working process of the signal generating circuit provided by the embodiment of the invention is as follows: firstly, the voltage holding unit 130 is controlled to work by the holding control signal Kb, the grounding end GND is electrically connected with the first polar plate of the charge-discharge capacitor 150, and the second polar plate of the charge-discharge capacitor 150 is electrically connected with the grounding end GND, so that the voltage holding unit 130 can perform resetting and voltage stabilizing processing on the charge-discharge capacitor 150; at this time, the charging unit 140 and the access unit 120 are both in a non-operating state. Then, the voltage holding unit 130 stops working, and the charging control signal Kc controls the charging unit 140 to transmit the charging voltage Vc to the first plate of the charging and discharging capacitor 150, so as to charge the charging and discharging capacitor 150; the access unit 120 is now inactive. Finally, the voltage holding unit 130 and the charging unit 140 both maintain a non-operating state, and generate a control signal Kj to control the access unit 120 to connect the constant current source 110 with the first plate of the charging/discharging capacitor 150, so as to operate simultaneously with the discharging process of the charging/discharging capacitor 150, so that the output terminal OUT outputs a ramp voltage. Therefore, the embodiment of the present invention provides a technical solution that the voltage holding unit 130 can reset and stabilize the charging/discharging capacitor 150 before generating the ramp voltage, so as to improve the stability of the signal generating circuit.

Referring to fig. 2, a schematic structural diagram of another signal generating circuit provided in an embodiment of the present invention is shown, where the access unit 120 provided in the embodiment of the present invention includes an access transistor Mj, a first end of the access transistor Mj is electrically connected to the constant current source 110, a second end of the access transistor Mj is electrically connected to a first plate of the charge and discharge capacitor 150, and a gate of the access transistor Mj is connected to the generation control signal Kj.

The voltage holding unit 130 includes at least one holding transistor Mb, a first terminal of the holding transistor Mb is electrically connected to the ground GND, a second terminal of the holding transistor Mb is electrically connected to the first plate of the charge and discharge capacitor 150, and a gate of the holding transistor Mb is connected to the holding control signal Kb.

The charging unit 140 includes a charging transistor Mc, a first end of the charging transistor Mc is connected to the charging voltage Vc, a second end of the charging transistor Mc is electrically connected to the first plate of the charging and discharging capacitor 150, and a gate of the charging transistor Mc is connected to the charging control signal Kc.

In an embodiment of the present invention, the access transistor Mj, the holding transistor Mb, and the charging transistor Mc provided in the present invention may be all N-type transistors, or all P-type transistors, or a part of N-type transistors and a part of P-type transistors. The operation of the signal generating circuit according to the embodiment of the present invention will be described in more detail with reference to the accompanying drawings. As shown in fig. 3, a timing diagram of a signal generating circuit according to an embodiment of the present invention is provided, in which the operation of the signal generating circuit includes a first stage S11, a second stage S12, and a third stage S13. In the first stage S11, the holding control signal Kb is kept at a low level, the holding transistor Mb is controlled to be turned on, and the ground GND is connected to the first plate of the charge/discharge capacitor 150, so as to reset and stabilize the charge/discharge capacitor 150. In the second stage S12, the charging control signal Kc is at a low level, and controls the charging transistor Mc to be turned on, so as to transmit the charging voltage Vc to the first plate of the charging/discharging capacitor 150, so as to charge the charging/discharging capacitor 150. In the third stage S13, a control signal Kj is generated to control the access transistor Mj to be turned on, so as to connect the constant current source 110 with the first plate of the charge/discharge capacitor 150, and at the same time, the charge/discharge capacitor 150 starts to discharge, so that the output terminal OUT outputs a ramp voltage.

Referring to fig. 4, a schematic structural diagram of a constant current source provided in an embodiment of the present invention is shown, where the constant current source includes a first constant current transistor M1, a second constant current transistor M2, a third constant current transistor M3, a fourth constant current transistor M4, a fifth constant current transistor M5, a sixth constant current transistor M6, and a holding capacitor C, where a first end of the first constant current transistor M1 is electrically connected to a second end of the fifth constant current transistor M5 and a first end of the third constant current transistor M3, a second end of the first constant current transistor M1 is electrically connected to a second end of the fourth constant current transistor M4 and a first end of the sixth constant current transistor M6, and a gate of the first constant current transistor M1 is electrically connected to a second end of the third constant current transistor M3, a first end of the holding capacitor C and a second end of the second constant current transistor M2; a first end of the second constant current transistor M2 is connected to a reference voltage Vre, and a gate of the second constant current transistor M2 is connected to a first constant current control signal L1; the gate of the third constant current transistor M3 is connected to the second constant current control signal L2, the first end of the fourth constant current transistor M4 is connected to the limit voltage Vds, the gate of the fourth constant current transistor M4 is connected to the second constant current control signal L2, and the first end of the fifth constant current transistor M5 is connected to the voltage Vs, wherein the voltage Vs is less than the limit voltage Vds, and the voltage Vs and the limit voltage Vds are less than the voltage of the ground terminal GND in the panel; the gate of the fifth constant current transistor M5 is connected to generate a control signal Kj, the second terminal of the sixth constant current transistor M6 is the output terminal OUT1 of the constant current source, and the gate of the sixth constant current transistor M6 is connected to generate the control signal Kj.

It can be understood that the constant current source is used for outputting a current to the output terminal OUT of the signal generating circuit when the access unit 120 operates in the signal generating circuit, so that the operation process of the constant current source includes the same first stage S11, second stage S12 and third stage S13 as the signal generating circuit. As shown in the timing chart of fig. 5, in the first stage S11, the first constant current control signal L1 controls the second constant current transistor M2 to be turned on, and transmits the reference voltage Vre to the gate of the first constant current transistor M1 to perform the reset process; then, in the second stage S12, the second constant current control signal L2 controls the third constant current transistor M3 and the fourth constant current transistor M4 to be turned on, so as to maintain the on state of the first constant current transistor M1; finally, in the third stage S13, the control signal Kj is generated to control the fifth constant current transistor M5 and the sixth constant current transistor M6 to be turned on, so as to form a path from the voltage Vs to the output terminal OUT1 to output a current.

It should be noted that, in the embodiment of the present invention, the conduction type of the transistor included in the constant current source is not limited, and the transistor may be an N-type transistor or a P-type transistor; and at least one of the transistors included in the constant current source can be a double-gate transistor so as to improve the response speed of the transistor and reduce the leakage current of the transistor, thereby improving the performance of the constant current source. In the embodiment of the present invention, all the transistors included in the constant current source are P-type transistors for example; in contrast, in other embodiments of the present invention, all transistors included in the constant current source may also be N-type transistors; in other embodiments of the present invention, the circuit structure of the constant current source may be of other types, which need to be designed specifically according to practical applications.

Referring to fig. 6, a schematic structural diagram of another signal generating circuit provided in an embodiment of the present invention is shown, where the signal generating circuit provided in the embodiment of the present invention further includes: and a voltage stabilizing unit 160 electrically connected between the first plate of the charge and discharge capacitor 150 and the output terminal OUT of the signal generating circuit. Further, the ramp voltage output from the output terminal OUT is regulated by the voltage regulation unit 160 and then output, thereby improving the performance of the signal generation circuit.

The voltage stabilizing unit provided by the embodiment of the invention can comprise an operational amplifier. Referring to fig. 7 specifically, a schematic structural diagram of another signal generating circuit according to an embodiment of the present invention is shown, wherein the voltage stabilizing unit 160 according to an embodiment of the present invention includes an operational amplifier OP, a non-inverting terminal + of the operational amplifier OP is electrically connected to the first plate of the charging and discharging capacitor 150, and an inverting terminal-of the operational amplifier OP and an output terminal of the operational amplifier OP are electrically connected to the output terminal OUT of the signal generating circuit.

Correspondingly, the embodiment of the invention also provides a scanning circuit. Referring to fig. 8, a schematic structural diagram of a scan circuit according to an embodiment of the present invention is shown, where the scan circuit includes: the first signal generating circuit 101 to the nth signal generating circuit 10N, any one of the signal generating circuits provided in any one of the above embodiments, N being an integer greater than or equal to 2.

In the first to nth signal generating circuits 101 to 10N, an initial time at which at least one of the signal generating circuits switches on the active level of the generation control signal is different from initial times at which the remaining signal generating circuits switch on the active level of the generation control signal.

It can be understood that the effective level for generating the control signal provided by the embodiment of the present invention is a corresponding control level for controlling the access unit to access the constant current source to the output end of the signal generating circuit; that is, the control signal generation circuit generates the control level of the ramp voltage. The initial time when the at least one signal difference generation circuit is connected to generate the effective level of the control signal is different from other initial times, which indicates that the initial time when the at least one signal generation circuit outputs the ramp voltage is different. As shown in fig. 8, the first signal generating circuit 101 to the nth signal generating circuit 10N according to the embodiment of the present invention may be switched on to generate the active levels of the control signals one by one at regular intervals, so that the initial timings of the ramp voltages output by the first signal generating circuit 101 to the nth signal generating circuit 10N have a misalignment, and the first signal generating circuit 101 to the nth signal generating circuit 10N sequentially output the ramp voltages. As shown in fig. 8, the dotted line indicates the initial timing of the ramp voltage, and the first to nth signal generation circuits 101 to 10N sequentially output the ramp voltage at regular intervals.

Correspondingly, the embodiment of the invention also provides a display panel. With reference to fig. 9 and 10, fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and fig. 10 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention, where the display panel includes a display area AA and a non-display area NA located at a periphery of the display area AA, and the display panel includes:

a plurality of pixel driving circuit groups 10, the pixel driving circuit groups 10 including the signal generating circuit 100 and the pixel driving circuit 200, the pixel driving circuit 200 may be located in the display area AA, and the signal generating circuit 100 may be located in the non-display area NA.

The pixel circuit driving circuit 200 includes a pulse width modulation unit 210, a first light emission control unit 231, and a driving transistor T0; the pulse width modulation unit 210 is configured to output a pulse width setting signal with reference to a pulse width control voltage Sweep; the first light emission controlling unit 231 is configured to transmit the pulse width setting signal to the gate of the driving transistor T0 in response to a first light emission controlling signal K1.

The signal generating circuit 100 is configured to generate the pulse width control voltage sweet in response to the first lighting control signal K1; in all the signal generating circuits 100, the initial timing of the pulse width control voltage Sweep generated by at least one of the signal generating circuits 100 is different from the initial timing of the pulse width control voltage Sweep generated by the rest of the signal generating circuits 100.

As shown in fig. 10, the pixel driving circuit 200 provided for the embodiment of the present invention further includes: an amplitude modulation unit 220, a second light emission control unit 232, and a light emitting element 240. The amplitude modulation unit 220 is configured to output an amplitude setting signal to the gate of the driving transistor T0. The driving transistor T0 is used to generate a driving current with reference to the amplitude setting signal and the pulse width setting signal. The second light emission control unit 232 serves to transmit the driving current generated by the driving transistor T0 to the light emitting element 240. The light emitting element 240 emits light in response to the driving current.

It is to be understood that the pulse width control voltage sweet provided by the embodiment of the present invention is a ramp voltage, and is used for controlling the pulse width modulation unit 210 to generate a pulse width setting signal, and the pulse width setting signal is used for controlling the time length for which the driving transistor T0 generates the driving current, that is, the pulse width setting signal is used for controlling the light emitting time length of the light emitting element connected to the pixel driving circuit. Since the signal generating circuit 100 generates the pulse width control voltage sweet in response to the first lighting control signal K1 and the first lighting control unit 231 serves to transmit the pulse width setting signal to the gate of the driving transistor T0 in response to the first lighting control signal K1, the generation time of the pulse width control voltage sweet and the transmission time of the pulse width setting signal to the gate of the driving transistor T0 are synchronized.

Thus, the embodiment of the present invention controls the pulse width of the pulse-width control voltage Sweep generated by at least one of the signal generating circuits 100 in all the signal generating circuits 100, unlike the initial timing of the remaining pulse width control voltages Sweep generated by the signal generating circuit 100, which corresponds to the initial timing at which at least one of all the pulse width setting signals is transmitted to the gate of the corresponding driving transistor T0, unlike the initial timing at which the remaining pulse width setting signals are transmitted to the gates of the respective driving transistors T0, furthermore, all the pixel driving circuits of the display panel light the light-emitting elements at different initial moments, so that the situation that the voltage drop of the signal lines connected with the pixel driving circuits is overlarge when all the light-emitting elements light at the same initial moments is avoided, the stability of the pixel driving circuits is improved, and the display effect of the display panel is improved.

The following describes a specific structure of a signal generating circuit in a display panel according to an embodiment of the present invention with reference to the accompanying drawings, where the signal generating circuit in the display panel according to the present invention and the signal generating circuit according to any of the embodiments may have the same structure, but the signal generating circuit according to the present invention is specifically applied to a display panel, so that the difference is that control signals connected to some constituent units are different. Specifically, referring to fig. 1, the signal generating circuit of the display panel according to the embodiment of the present invention includes: the charging device comprises a constant current source 110, an access unit 120, a voltage holding unit 130, a charging unit 140 and a charging and discharging capacitor 150.

The access unit 120 is configured to communicate the constant current source 110 with a first plate of the charge and discharge capacitor 150 in response to the first lighting control signal K1, the first plate of the charge and discharge capacitor 150 is electrically connected with the output terminal OUT of the signal generating circuit, and a second plate of the charge and discharge capacitor 150 is electrically connected with a ground terminal GND. The voltage holding unit 130 is configured to electrically connect the ground GND to the first plate of the charge and discharge capacitor 150 in response to a holding control signal Kb. The charging unit 140 is configured to transmit a charging voltage Vc to the first plate of the charging and discharging capacitor 150 in response to the charging control signal Kc, where the charging and discharging voltage Vc is greater than the voltage of the ground terminal GND, and if the voltage of the ground terminal GND is 0V, the voltage of the charging and discharging voltage Vc may be 6V, which is not limited in this disclosure.

Referring to fig. 2, in the signal generating circuit of the display panel according to the embodiment of the present invention, the access unit 120 includes an access transistor Mj, a first end of the access transistor Mj is electrically connected to the constant current source 110, a second end of the access transistor Mj is electrically connected to a first plate of the charge and discharge capacitor 150, and a gate of the access transistor Mj is connected to the first lighting control signal K1. The voltage holding unit 130 includes at least one holding transistor Mb, a first terminal of the holding transistor Mb is electrically connected to the ground GND, a second terminal of the holding transistor Mb is electrically connected to the first plate of the charge and discharge capacitor 150, and a gate of the holding transistor Mb is connected to the holding control signal Kb. The charging unit 140 includes a charging transistor Mc, a first end of the charging transistor Mc is connected to the charging voltage Vc, a second end of the charging transistor Mc is electrically connected to the first plate of the charging and discharging capacitor 150, and a gate of the charging transistor Mc is connected to the charging control signal Kc.

Referring to fig. 6, the signal generating circuit of the display panel according to the embodiment of the present invention further includes: and a voltage stabilizing unit 160 electrically connected between the first plate of the charge and discharge capacitor 150 and the output terminal OUT of the signal generating circuit. Furthermore, the voltage stabilizing unit 160 stabilizes and outputs the ramp voltage (i.e., the pulse width control voltage sweet) output by the output terminal OUT, thereby improving the performance of the signal generating circuit. Referring to fig. 7 specifically, in the signal generating circuit of the display panel according to the embodiment of the present invention, the voltage stabilizing unit includes an operational amplifier, the voltage stabilizing unit 160 includes an operational amplifier OP, a non-inverting terminal + of the operational amplifier OP is electrically connected to the first plate of the charge and discharge capacitor 150, and an inverting terminal-of the operational amplifier OP and an output terminal of the operational amplifier OP are electrically connected to the output terminal OUT of the signal generating circuit.

Referring to fig. 11, a schematic structural diagram of another pixel driving circuit according to an embodiment of the present invention is shown, wherein the pulse width modulation unit 210 according to the embodiment of the present invention is connected to a first control signal S1, a second control signal S2 and the first light-emitting control signal K1, and the pulse width modulation unit 210 is configured to connect a reset voltage Vref in response to the first control signal S1, connect a first data voltage D1 in response to the second control signal S2, and connect an off-voltage Voff in response to the first light-emitting control signal K1. The amplitude modulation unit 220 is coupled to the first control signal S1 and the second control signal S2, and the amplitude modulation unit 220 is configured to couple to the reset voltage Vref in response to the first control signal S1 and to couple to the second data voltage D2 in response to the second control signal S2.

As shown in fig. 11, the pulse width modulation unit 210 according to the embodiment of the invention includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a first capacitor C1. The first light emission control unit 231 includes a sixth transistor T6. The amplitude modulation unit 220 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a second capacitor C2. And the second light emission control unit 232 includes a tenth transistor T10 and an eleventh transistor T11.

The first terminal of the first transistor T1 is connected to the reset voltage Vref, the second terminal of the first transistor T1 is electrically connected to the gate of the second transistor T2, the second terminal of the fourth transistor T4 and the second terminal of the first capacitor C1, the gate of the first transistor T1 is connected to the first control signal S1, and the first terminal of the first capacitor C1 is connected to the pulse width control voltage sweet, where the pulse width control voltage sweet is a linearly decreasing voltage. The first end of the second transistor T2 is electrically connected to the second end of the third transistor T3 and the second end of the fifth transistor T5, the second end of the second transistor T2 is electrically connected to the first end of the fourth transistor T4 and the first end of the sixth transistor T6, the first end of the third transistor T3 is connected to the first data voltage D1, the gate of the third transistor T3 is connected to the second control signal S2, the first end of the fifth transistor T5 is connected to the off-voltage Voff, the gate of the fifth transistor T5 is connected to the first light-emitting control signal K1, the second end of the sixth transistor T6 is electrically connected to the gate of the driving transistor T0, and the gate of the sixth transistor T6 is connected to the first light-emitting control signal K1.

A first terminal of the seventh transistor T7 is connected to the reset voltage Vref, a second terminal of the seventh transistor T7 is electrically connected to the gate of the driving transistor T0, a second terminal of the eighth transistor T8 and a second terminal of the second capacitor C2, a gate of the seventh transistor T7 is connected to the first control signal S1, a first terminal of the eighth transistor T8 is electrically connected to the second terminal of the driving transistor T0, a gate of the eighth transistor T8 is connected to the second control signal S2, and a first terminal of the second capacitor C2 is connected to the first power voltage V1. And a first terminal of the ninth transistor T9 is connected to the second data voltage D2, a second terminal of the ninth transistor T9 is electrically connected to the first terminal of the driving transistor T0, and a gate of the ninth transistor T9 is connected to the second control signal S2.

A first terminal of the tenth transistor T10 is connected to the first power voltage V1, a second terminal of the tenth transistor T10 is electrically connected to the first terminal of the driving transistor T0, and a gate of the tenth transistor T10 is connected to the second light emission control signal K2. And a first terminal of the eleventh transistor T11 is electrically connected to the second terminal of the driving transistor T0, a second terminal of the eleventh transistor T11 is electrically connected to the first terminal of the light emitting element 240, a gate of the eleventh transistor T11 is connected to the second light emission control signal K2, and a second terminal of the light emitting element 240 is connected to the second power voltage V2, wherein the first power voltage V1 is greater than the second power voltage V2.

In an embodiment of the invention, the display panel provided by the invention includes N rows of the pixel driving circuits scanned line by line, a first control signal of a pixel circuit in an i +1 th row and a second control signal of a pixel circuit in an i-th row are the same control signal, N is an integer greater than or equal to 2, and i is a positive integer less than N. Further, transmission lines corresponding to the control signals can be reduced, and the circuit wiring structure can be simplified.

Referring to fig. 12, a timing diagram of a pixel driving circuit according to an embodiment of the present invention is shown, and a driving method of the pixel driving circuit according to the embodiment of the present invention includes a signal generation phase S101 and a light emission control phase S102 performed in sequence.

The signal generation stage S101 includes a first sub-signal generation stage S111 and a second sub-signal generation stage S112 which are performed in sequence; wherein the second light emission control signal K2 and the first light emission control signal K1 are at a high level at the time of the signal generation stage S11, controlling the connected transistors to be turned off. During the first sub-signal generating stage S111, the first control signal S1 is at a low level, and the second control signal S2 is at a high level; at this time, the first control signal S1 controls the first transistor T1 and the seventh transistor T7 to be turned on, and thus, the reset voltage Vref is transmitted to the gate of the second transistor T2 and the gate of the driving transistor T0 to reset the second transistor T2 and the driving transistor T0; and the transistor with its gate tied to the second control signal S2 is off at this time.

Then, in the second sub-signal generating stage S112, the first control signal S1 is at a high level, and the second control signal S2 is at a low level; at this time, the second control signal S2 controls the third transistor T3, the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 to be turned on, and the first data voltage D1 is transmitted to the gate of the second transistor T2 through the third transistor T3, the second transistor T2 and the fourth transistor T4, so that the writing of the first data voltage D1, that is, the generation of the pulse width setting signal is completed; and the second data voltage D2 is transmitted to the gate of the driving transistor T0 through the ninth transistor T9, the driving transistor T0 and the eighth transistor T8, completing the writing of the second data voltage D2, i.e., completing the transmission of the amplitude setting signal to the gate of the driving transistor T0.

And, the control light emission phase S102 comprises a light emission sub-phase S121 and a turn-off sub-phase S122, which are performed in sequence; in the control light-emitting period S102, the first control signal S1 and the second control signal S2 are high, and the connected transistors are turned off. In the light-emitting sub-phase S121, the first light-emitting control signal K1 and the second light-emitting control signal K2 are both low level, and control the fifth transistor T5, the sixth transistor T6, the tenth transistor T10 and the eleventh transistor T11 to be turned on; at this time, the pulse width control voltage sweet controls the second transistor T2 to keep off through the first capacitor C1, although the fifth transistor T5 is turned on, the off-voltage Voff cannot be transmitted to the gate of the driving transistor T0 through the second transistor T2, and the pulse width setting signal transmitted by the sixth transistor T6 is substantially a floating signal; the tenth transistor T0 and the eleventh transistor T11 are turned on to turn on a path from the first power voltage V1 to the second power voltage V2, and the driving current generated by the driving transistor T0 is transmitted to the light emitting element 240.

Then, in the turn-off sub-stage S122, the light-emitting control signal K1 and the pulse width control signal K2 are at low level, and the corresponding transistors are controlled to be turned on; and the pulse width control voltage sweet is a slope voltage of a linearly decreasing voltage, which is decreased to the lowest level at this stage and cannot maintain the second transistor T2 to be kept off and controlled to be in an on state through the first capacitor C1, the off-voltage Voff is transmitted to the gate of the driving transistor T0 through the fifth transistor T5, the second transistor T2 and the sixth transistor T6 to control the driving transistor T0 to be off, and at this time, the driving transistor T0 no longer generates a driving current, so that the light emitting device 240 keeps off.

Alternatively, in another embodiment of the present invention, when the sub-phase is turned off, the ramp voltage of which the pulse width control voltage is a linearly decreased voltage is decreased to the lowest, the first light emitting control signal and the second light emitting control signal are converted to the high level, and the fifth transistor, the sixth transistor, the tenth transistor, and the eleventh transistor are controlled to be turned off, so that the light-off control of the light emitting element is completed.

In an embodiment of the present invention, the control signal in the signal generating circuit provided by the present invention can multiplex the control signal in the pixel driving circuit to reduce the number of signal ports and corresponding lines. As shown in fig. 13, a schematic structural diagram of a pixel driving circuit group according to an embodiment of the present invention is illustrated, in which the pixel driving circuit group includes two rows of pixel driving circuits 11 and 12 (only one pixel driving circuit is shown in each row). Wherein the signal generating circuit 100 includes the constant current source 110, the accessing unit 120, the voltage holding unit 130, the charging unit 140, and the charging and discharging capacitor 150, the accessing unit 120 includes the accessing transistor Mj, the voltage holding unit 130 includes at least one of the holding transistors, and the charging unit 140 includes the charging transistor Mc.

The pixel driving circuit group includes M rows of pixel driving circuits (first row 11 and second row 12), wherein the voltage holding unit 130 includes first to M +1 th holding transistors (first to third holding transistors Mb1 to Mb3), the holding control signals include first to M +1 th sub-holding control signals (first to third sub-holding control signals Kb1 to Kb3), a gate of the jth holding transistor is connected to the jth sub-holding control signal, M is an integer greater than or equal to 1, and j is a positive integer less than or equal to M + 1.

When M provided by the embodiment of the present invention is equal to 1, or when M provided by the embodiment of the present invention is greater than 1 and the pixel driving circuits of M rows are adjacent rows (such as the adjacent first row 11 and second row 12 in fig. 13): the kth sub-holding control signal and the first control signal of the pixel driving circuit of the kth row are the same signal, the M +1 th sub-holding control signal and the second control signal of the pixel driving circuit of the Mth row are the same signal, and k is a positive integer less than or equal to M. And the charging control signal of the current pixel driving circuit group and the second control signal of the pixel driving circuit of the next pixel driving circuit group and the adjacent first row are the same signal. Specifically, with reference to the timing diagram of a pixel driving circuit group shown in fig. 14, S101 is a signal generating phase of the pixel driving circuits in the first row 11, and S101' is a signal generating phase of the pixel driving circuits in the second row 11; the charging control signal Kc of the current pixel driving circuit group provided in the embodiment of the present invention is the same signal as the second control signal of the pixel driving circuit of the next pixel driving circuit group and the adjacent first row, so that the charging stage of the charging/discharging capacitor 150 of the signal generating circuit 100 (i.e., the second sub-signal generating stage of the pixel driving circuit of the next row adjacent to the current pixel driving circuit group) is performed after the pixel driving circuit of the second row 12 completes the signal generating stage S101'. After the charging of the charging/discharging capacitor 150 of the input signal generating circuit 100 is completed, the first light-emitting control signal K1 and the second light-emitting control signal K2 control all the pixel driving circuits in the first row 11 and the second row 12 to generate driving currents to control the light-emitting elements 240 to emit light.

In an embodiment of the invention, when the pixel driving circuit group provided by the invention includes a plurality of rows of pixel driving circuits, at least one row of pixel driving circuits may also be not adjacent to other rows of pixel driving circuits, that is, M is greater than 1 and at least one of the M rows of pixel driving circuits is located in a different row from the rest of the pixel driving circuits. Optionally, when the pixel driving circuit group provided by the embodiment of the present invention includes one or more rows of pixel driving circuits, and when the pixel driving circuits of the rows are adjacent or not adjacent, the control signal in the signal generating circuit may also be provided by an independent driving chip, which is not limited in particular to the present invention.

The operation of the different pixel driving circuit groups provided by the embodiment of the present invention is further described in detail with reference to fig. 15 and 16. Referring to fig. 15, a schematic diagram of a structure of two adjacent pixel driving circuit groups according to an embodiment of the present invention is shown, and fig. 16 is a timing diagram of two adjacent pixel driving circuit groups according to an embodiment of the present invention. Two adjacent pixel driving circuit groups are defined as a first pixel driving circuit group 1001 and a second pixel driving circuit group 1002. As shown in fig. 16:

in the stage S1001, the first control signal S1 of the first pixel driving circuit group 1001 is at a low level, the first transistor T1 and the seventh transistor T7 are controlled to be turned on, and the reset voltage Vref is transmitted to the gate of the second transistor T2 and the gate of the driving transistor T0 to reset the second transistor T2 and the driving transistor T0. At the same time, the first holding transistor Mb1 in the first pixel driving circuit group 1001 is turned on, and the ground GND is electrically connected to the first plate of the charge/discharge capacitor 150.

In the stage S1002, the second control signal S1 of the first pixel driving circuit group 1001 is at a low level, and controls the third transistor T3, the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 to be turned on, and the first data voltage D1 is transmitted to the gate of the second transistor T2 through the third transistor T3, the second transistor T2 and the fourth transistor T4, so that the writing of the first data voltage D1, that is, the generation of the pulse width setting signal is completed; and the second data voltage D2 is transmitted to the gate of the driving transistor T0 through the ninth transistor T9, the driving transistor T0 and the eighth transistor T8, completing the writing of the second data voltage D2, i.e., completing the transmission of the amplitude setting signal to the gate of the driving transistor T0. The second holding transistor Mb2 in the first pixel driving circuit group 1001 is turned on, and the ground GND is electrically connected to the first plate of the charge/discharge capacitor 150. Meanwhile, the first control signal S1 of the second pixel driving circuit group 1002 is at a low level, and controls the first transistor T1 and the seventh transistor T7 to be turned on, and the reset voltage Vref is transmitted to the gate of the second transistor T2 and the gate of the driving transistor T0 to reset the second transistor T2 and the driving transistor T0. At the same time, the first holding transistor Mb1 in the second pixel driving circuit group 1002 is turned on, and the ground GND is electrically connected to the first plate of the charge/discharge capacitor 150.

In the stage S1003, the second control signal S1 of the second pixel driving circuit group 1002 is at a low level, and controls the third transistor T3, the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 to be turned on, and the first data voltage D1 is transmitted to the gate of the second transistor T2 through the third transistor T3, the second transistor T2 and the fourth transistor T4, so that the writing of the first data voltage D1, that is, the generation of the pulse width setting signal is completed; and the second data voltage D2 is transmitted to the gate of the driving transistor T0 through the ninth transistor T9, the driving transistor T0 and the eighth transistor T8, completing the writing of the second data voltage D2, i.e., completing the transmission of the amplitude setting signal to the gate of the driving transistor T0. The second holding transistor Mb2 in the second pixel driving circuit group 1002 is turned on, and the ground GND is electrically connected to the first plate of the charge/discharge capacitor 150. Meanwhile, the charge control signal Kc of the first pixel driving circuit group 1001 is at a low level to control the conduction of the charge transistor Mc, so as to charge the charge/discharge capacitor 150.

At a stage S1004, the first light-emitting control signal K1 and the second light-emitting control signal K2 of the first pixel driving circuit group 1001 are at a low level, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the eleventh transistor T11 and the access transistor Mj are controlled to be turned on, and the signal generating circuit 100 outputs a pulse width control voltage sweet to control the pulse width modulation unit 210 to generate a pulse width setting signal and transmit the pulse width setting signal to the gate of the driving transistor T0; the tenth transistor T0 and the eleventh transistor T11 are turned on to turn on a path from the first power voltage V1 to the second power voltage V2, and the driving current generated by the driving transistor T0 is transmitted to the light emitting element 240. Meanwhile, the charge control signal Kc of the second pixel driving circuit group 1002 is at a low level to control the conduction of the charge transistor Mc, so as to charge the charge/discharge capacitor 150.

In the stage S1005, the first light-emitting control signal K1 and the second light-emitting control signal K2 of the second pixel driving circuit group 1002 are at a low level, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the eleventh transistor T11 and the access transistor Mj are controlled to be turned on, and the signal generating circuit 100 outputs the pulse width control voltage sweet to control the pulse width modulating unit 210 to generate the pulse width setting signal and transmit the pulse width setting signal to the gate of the driving transistor T0; the tenth transistor T0 and the eleventh transistor T11 are turned on to turn on a path from the first power voltage V1 to the second power voltage V2, and the driving current generated by the driving transistor T0 is transmitted to the light emitting element 240.

As can be seen from the above, in the technical solution provided in the embodiment of the present invention, the light emitting element of the first pixel driving circuit group 1001 is turned on at the initial time of the stage S1003, and the light emitting element of the second pixel driving circuit group 1002 is turned on at the initial time of the stage S1004, so that the situation that the light emitting element 240 in the first pixel driving circuit group 1001 and the light emitting element 240 in the second pixel driving circuit group 1002 are turned on at the same time is avoided, and further, the situation that the voltage drop on the signal line shared by the pixel driving circuit groups is too large is avoided, the stability of the pixel driving circuit is improved, and the display effect of the display panel is improved.

Referring to fig. 17, a schematic structural diagram of another pixel driving circuit according to an embodiment of the present invention is provided, wherein the pixel driving circuit includes a light emitting element 240 and further includes a light emitting reset unit 250, and the light emitting reset unit 250 is configured to transmit the reset voltage Vref to the light emitting element 240 in response to the second control signal S2. Optionally, the light emitting reset unit 250 includes a twelfth transistor T12, a first terminal of the twelfth transistor T12 is connected to the reset voltage Vref, a second terminal of the twelfth transistor M12 is connected to the first terminal of the light emitting device 240, a gate of the twelfth transistor M12 is connected to the second control signal S2, and the second control signal S2 controls the twelfth transistor M12 to transmit the reset voltage Vref to the light emitting device 240, so as to reset the light emitting device 240.

Correspondingly, the invention further provides a display device which comprises the display panel provided by any one of the embodiments.

Referring to fig. 18, a display device 1000 according to an embodiment of the present invention may be a mobile terminal, and the mobile terminal includes the display panel according to any of the embodiments.

It should be noted that the display device provided in the embodiment of the present invention may also be a notebook, a tablet, a computer, a wearable device, and the like, and the present invention is not limited in particular.

The embodiment of the invention provides a signal generating circuit, a scanning circuit, a display panel and a display device, comprising: the charging device comprises a constant current source, an access unit, a voltage holding unit, a charging unit and a charging and discharging capacitor; the access unit is used for responding to and generating a control signal and communicating the constant current source with a first polar plate of the charge-discharge capacitor, the first polar plate of the charge-discharge capacitor is electrically connected with the output end of the signal generating circuit, and a second polar plate of the charge-discharge capacitor is electrically connected with a grounding end; the voltage holding unit is used for responding to a holding control signal and electrically connecting a grounding end with the first polar plate of the charge-discharge capacitor; the charging unit is used for responding to a charging control signal and transmitting a charging voltage to a first polar plate of the charging and discharging capacitor. According to the signal generating circuit provided by the embodiment of the invention, firstly, the charge and discharge capacitor is reset and stabilized through the voltage holding unit, then, the charge and discharge capacitor is charged through the charging unit, and finally, the constant current source is communicated with the first polar plate of the charge and discharge capacitor through the access unit and acts with the discharge process of the charge and discharge capacitor to generate the slope voltage. Therefore, the voltage holding unit provided by the embodiment of the invention can reset and stabilize the charging and discharging capacitor, and the stability of the signal generating circuit is improved.

In the display panel provided by the embodiment of the present invention, the initial time of the pulse width control voltage generated by at least one of the signal generation circuits is different from the initial times of the pulse width control voltages generated by the remaining signal generation circuits, so that all the pixel driving circuits of the display panel light the light emitting elements at different initial times, thereby avoiding the occurrence of an excessive voltage drop caused by the lighting of all the light emitting elements at the same initial time to the signal lines connected to the pixel driving circuits, further improving the stability of the pixel driving circuits, and improving the display effect of the display panel.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A signal generating circuit, comprising: the charging device comprises a constant current source, an access unit, a voltage holding unit, a charging unit and a charging and discharging capacitor;

2. The signal generating circuit of claim 1, wherein the access unit comprises an access transistor, a first terminal of the access transistor is electrically connected to the constant current source, a second terminal of the access transistor is electrically connected to a first plate of the charge and discharge capacitor, and a gate of the access transistor is connected to the generation control signal;

3. The signal generation circuit of claim 1, further comprising: and the voltage stabilizing unit is electrically connected between the first polar plate of the charge and discharge capacitor and the output end of the signal generating circuit.

4. The signal generating circuit of claim 3, wherein the voltage stabilizing unit comprises an operational amplifier, a non-inverting terminal of the operational amplifier is electrically connected to the first plate of the charge-discharge capacitor, and an inverting terminal of the operational amplifier and an output terminal of the operational amplifier are electrically connected to an output terminal of the signal generating circuit.

5. A scan circuit, comprising: a first signal generating circuit to an nth signal generating circuit, any one of the signal generating circuits being the signal generating circuit of any one of claims 1 to 4, N being an integer greater than or equal to 2;

6. A display panel, comprising:

7. The display panel according to claim 6, wherein the signal generation circuit comprises: the charging device comprises a constant current source, an access unit, a voltage holding unit, a charging unit and a charging and discharging capacitor;

8. The display panel according to claim 7, wherein the access unit comprises an access transistor, a first terminal of the access transistor is electrically connected to the constant current source, a second terminal of the access transistor is electrically connected to a first plate of the charge and discharge capacitor, and a gate of the access transistor is connected to the first light emission control signal;

9. The display panel according to claim 7, wherein the signal generation circuit further comprises: and the voltage stabilizing unit is electrically connected between the first polar plate of the charge and discharge capacitor and the output end of the signal generating circuit.

10. The display panel according to claim 9, wherein the voltage stabilizing unit comprises an operational amplifier, a non-inverting terminal of the operational amplifier is electrically connected to the first plate of the charge and discharge capacitor, and an inverting terminal of the operational amplifier and an output terminal of the operational amplifier are electrically connected to an output terminal of the signal generating circuit.

11. The display panel according to any one of claims 6 to 10, wherein the pulse width modulation unit switches in a first control signal, a second control signal and the first lighting control signal, the pulse width modulation unit is configured to switch in a reset voltage in response to the first control signal, switch in a first data voltage in response to the second control signal, and switch in a turn-off voltage in response to the first lighting control signal;

12. The display panel according to claim 11, wherein the signal generation circuit includes the constant current source, the access unit, the voltage holding unit, the charging unit, and the charge and discharge capacitor, the access unit includes the access transistor, the voltage holding unit includes at least one of the holding transistors, and the charging unit includes the charging transistor;

13. The display panel according to claim 12, wherein when M is equal to 1, or when M is greater than 1 and M rows of pixel driving circuits are adjacent rows:

14. The display panel of claim 12, wherein M is greater than 1 and at least one of the M rows of pixel driving circuits is in a different row than the remaining pixel driving circuits.

15. The display panel according to claim 6, wherein the pixel driving circuit includes a light emitting element and further comprises a light emission reset unit for transmitting the reset voltage to the light emitting element in response to the second control signal.

16. A display device characterized in that it comprises a display panel according to any one of claims 6 to 15.