CN113823596A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113823596A
CN113823596A CN202010562009.7A CN202010562009A CN113823596A CN 113823596 A CN113823596 A CN 113823596A CN 202010562009 A CN202010562009 A CN 202010562009A CN 113823596 A CN113823596 A CN 113823596A
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isolation
isolation region
forming
dummy gates
substrate
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涂武涛
陈建
王彦
张海洋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202010562009.7A priority Critical patent/CN113823596A/en
Publication of CN113823596A publication Critical patent/CN113823596A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a base, wherein the base comprises a substrate, a plurality of parallel dummy gates on the substrate and side structures on two sides of the dummy gates, the base comprises an isolation region, and the extension direction of the isolation region intersects with the plurality of parallel dummy gates; removing the dummy gates intersected in the isolation region to form an initial transverse isolation trench transversely intersecting the plurality of parallel dummy gates; removing the side structure in the isolation region to form a target transverse cutting isolation groove; and forming a transverse isolation structure for filling the target transverse isolation trench. The method improves the performance of the device.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In Semiconductor manufacturing, as the feature size of an integrated circuit is continuously reduced along with the development trend of a very large scale integrated circuit, the channel length of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is continuously shortened in order to adapt to the smaller feature size. However, as the Channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the control capability of the gate structure to the Channel is deteriorated, the difficulty of the gate voltage to pinch off the Channel is increased, and the sub-threshold leakage (SCE), which is a so-called Short Channel effect, is more likely to occur.
Therefore, in order to reduce the influence of short channel Effect, the semiconductor process gradually starts to transition from planar MOSFET to three-dimensional Transistor with higher efficiency, such as Fin-Field-Effect Transistor (FinFET). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, compared with a planar MOSFET, the gate structure has stronger control capability on a channel, can well inhibit a short-channel effect, and has better compatibility with the existing integrated circuit manufacturing.
However, the performance of the devices formed by the existing semiconductor process is not good.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including:
providing a base, wherein the base comprises a substrate, a plurality of parallel dummy gates on the substrate and side structures on two sides of the dummy gates, the base comprises an isolation region, and the extension direction of the isolation region intersects with the plurality of parallel dummy gates;
removing the dummy gates intersected in the isolation region to form an initial transverse isolation trench transversely intersecting the plurality of parallel dummy gates;
removing the side structure in the isolation region to form a target transverse cutting isolation groove;
and forming a transverse isolation structure for filling the target transverse isolation trench.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including:
the substrate comprises a substrate, a plurality of parallel dummy gates on the substrate and side structures on two sides of the dummy gates, wherein the substrate comprises an isolation region, and the extension direction of the isolation region is intersected with the plurality of parallel dummy gates;
a cross-cut isolation structure within the isolation region, the cross-cut isolation structure isolating the plurality of parallel dummy gates and side structures between the plurality of parallel dummy gates.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, when the target transverse isolation groove is formed, the dummy gate intersected in the isolation region is removed, and meanwhile, the side structure in the isolation region is also removed, so that the protrusion possibly positioned on the side surface of the dummy gate is removed, the damage of the metal gate caused by the protrusion in the subsequent process is avoided, and the performance of the device is further improved.
Drawings
Fig. 1 to 8 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;
fig. 9 to 21 are schematic structural views corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the invention;
fig. 22 to 24 are schematic structural views of a semiconductor structure according to an embodiment of the invention.
Detailed Description
As can be seen from the background art, the devices formed by the prior art process still have poor performance. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1 to 8, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
As shown in fig. 1 to 2, a base 100 is provided, and the base includes a substrate 101 and a plurality of parallel dummy gates 120 located on the substrate, wherein the base 100 includes an isolation region 10A, and an extending direction of the isolation region 10A intersects with the plurality of parallel dummy gates 120. Wherein, fig. 2 is a cross-sectional view along AA' of fig. 1.
As shown in fig. 3, the dummy gates intersecting in the isolation region 10A are etched and removed by an anisotropic etching process to form a cross-cut isolation trench 121 crossing the plurality of parallel dummy gates.
As shown in fig. 4, a cross-cut isolation structure 140 is deposited in the cross-cut isolation trench 121.
As shown in fig. 5, a metal gate 150 is formed at the remaining dummy gate location.
As shown in fig. 5 to 7, the isolation gate 151 in the metal gate 150 is removed by wet etching, and a cut isolation trench 161 is formed. Fig. 7 is a cross-sectional view of fig. 6 taken along the direction BB'.
As shown in fig. 8, a truncated isolation structure 160 filling the truncated isolation trench 161 is formed.
The inventor finds that the device formed by the method has poor performance because the dummy gate structure may form a protrusion based on environmental influences (such as temperature, pressure, and the like) during or after the formation of the dummy gate structure, such as the black shaded region shown in fig. 2 to 4, for example, when the dummy gate is made of polysilicon, crystallization is likely to occur in a high temperature environment (such as a high temperature environment during a sidewall deposition process), and thus the protrusion protrudes from the original process space and intrudes into the side structures at two sides of the dummy gate; furthermore, in the forming process of the transversal isolation trench, the anisotropic etching process only etches in the direction perpendicular to the substrate surface, but does not etch in other directions, so as to avoid damaging the dummy gates at other parts, which results in that the protruding parts protruding out of the original process space cannot be removed, and if the protruding parts which cannot be removed are connected with the remaining dummy gates, the metal gates formed in the dummy gate process space subsequently extend to the protruding positions at the same time, so that during the step of removing the isolation gate in the metal gate by wet etching, the etching liquid can easily etch the material at the protruding positions, and immerse into the metal gate which does not need to be etched (as shown by the dotted arrow in fig. 6) through the protruding positions (as shown in fig. 7), thereby causing damage to the gate structure of the device.
Based on this, in the embodiment of the present invention, when the target transverse isolation trench is formed, the dummy gate intersecting in the isolation region is removed, and the side structure in the isolation region is also removed, so as to remove the protrusion possibly located on the side surface of the dummy gate, thereby avoiding the damage of the metal gate caused by the protrusion in the subsequent process, and further improving the performance of the device.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 9 to 21 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 9-10, a base 200 is provided, the base including a substrate 201, a plurality of parallel dummy gates 220 on the substrate, and side structures on both sides of the dummy gates.
Fig. 10 is a sectional view taken along direction CC' in fig. 9.
The substrate includes an isolation region 20A, an extending direction of the isolation region 20A intersects with the plurality of parallel dummy gates, and optionally, the extending direction of the isolation region is perpendicular to the extending direction of the plurality of parallel dummy gates. The isolation region 20A is a region of the substrate 200 for forming a target cross-cut isolation trench, and the region covers a partial structure of the plurality of parallel dummy gates and a partial structure of a side structure between the plurality of parallel dummy gates, so that the target cross-cut isolation trench is formed by subsequently etching the isolation region.
The width of the isolation region should not be too large or too small, and if the width of the isolation region is too large, the width of a subsequently formed target transverse cutting isolation trench is also correspondingly too large, so that too much space is occupied, and the size of the semiconductor structure is not favorably reduced; if the width of the isolation region is too small, the width of a subsequently formed target transverse isolation trench is also correspondingly too small, which is not favorable for playing a role of isolating devices. Accordingly, the width of the isolation region may be 10 nm to 30 nm.
The substrate 201 is used to provide support for other structures. In the embodiment of the present invention, the material of the substrate 201 may be silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration. The surface of the substrate 201 can also be formed with an interface layer, and the interface layer is made of silicon oxide, silicon nitride, silicon oxynitride, or the like.
The dummy gate 220 occupies a space for a metal gate structure formed in a subsequent process. The dummy gate 220 may be polysilicon, and in other embodiments, the material of the dummy gate 220 may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon.
In the device structure forming process, in order to simultaneously form a plurality of device structures, a plurality of parallel dummy gates are usually simultaneously formed on the substrate, so that corresponding processing is simultaneously performed in the device forming process, and the process flow is simplified.
In an embodiment of the invention, the substrate further includes a discrete fin portion protruding from the substrate, and the plurality of dummy gates cross over the fin portion. The material of the fin portion may be the same as or different from the material of the substrate. The dummy gate crosses over the discrete fin portion, so that the fin portion is used as a channel structure to control a device.
Side structures are formed on two sides of the dummy gate 220, and the side structures are used for providing isolation, support, definition of a process space and the like for the dummy gate 220 to form a corresponding device structure.
In the embodiment of the present invention, the side structure may include side walls 230 located at two sides of the dummy gate, and the side walls 230 may define a formation region of the source-drain doping layer. Further, in the embodiment of the present invention, the side structure may further include an interlayer dielectric layer 240 located between adjacent sidewalls, where the interlayer dielectric layer is used to isolate different device structures and further define a process space for the device.
The side wall may be made of silicon nitride. In other embodiments of the present invention, the sidewall spacer may also be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
The interlayer dielectric layer 240 is made of an insulating material. In this embodiment, the interlayer dielectric layer 240 is made of silicon oxide. In other embodiments, the material of the interlayer dielectric layer 240 may also be other dielectric materials such as silicon nitride or silicon oxynitride.
In the embodiment of the present invention, a hard mask layer 250 may be further formed on the dummy gate 220, and the side structure (including the sidewall spacers 230 and the interlayer dielectric layer 240) is flush with the hard mask layer 250. The hard mask layer 250 is used to protect the dummy gate, the hard mask layer 250 may be made of silicon nitride, and in other embodiments, the hard mask layer may also be made of silicon oxynitride.
In the embodiment of the present invention, in order to remove the dummy gate intersecting the isolation region subsequently, referring to fig. 11 to 12, in the embodiment of the present invention, the hard mask layer and the interlayer dielectric layer with a partial thickness in the isolation region 20A are removed first, and the dummy gate is exposed.
Specifically, the hard mask layer and the side structure with a partial thickness in the isolation region may be removed through a series of semiconductor processes such as photolithography and etching. For example, a patterned first mask layer (260 shown in fig. 11) may be formed, the first mask layer having an opening exposing the isolation region, and the hard mask layer 250 and a part of the thickness of the side structure (shown in fig. 12) in the corresponding region may be further removed by using the first mask layer 260 as a mask, thereby exposing the dummy gate.
Then, the dummy gates intersected in the isolation region are removed, and an initial transverse isolation trench which transversely intersects the plurality of parallel dummy gates is formed.
Specifically, the initial cross-cut isolation trench that crosses the plurality of parallel dummy gates may be formed through a series of semiconductor processes such as photolithography and etching. For example, a patterned second mask layer may be formed, the second mask layer having an opening exposing the isolation region, and further removing a corresponding portion of the dummy gate using the second mask layer as a mask, thereby forming an initial cross-cut isolation trench that cross-cuts the plurality of parallel dummy gates.
It can be understood that, in the process of removing the dummy gate, based on that the material of the dummy gate is different from the material of other parts, an etching process with a higher selective etching ratio on the material of the dummy gate may be selected according to the characteristics of the material to etch the initial cross-cut isolation trench, so that damage to other parts of the device structure may be reduced.
And then, removing the side structure in the isolation region to form a target transverse isolation trench.
The target transects the isolation trench to intercept the dummy gate in a dummy gate extension direction to isolate a plurality of corresponding device structures in the dummy gate extension direction. It should be noted that, in order to facilitate the semiconductor integration process, the target is to cut off the parallel dummy gates in the direction perpendicular to the extension direction of the dummy gates at the same time across the isolation trenches to isolate the device structures at the same time. Correspondingly, the extension direction of the isolation region is perpendicular to the extension direction of the plurality of parallel dummy gates and intersects with the dummy gates.
In the embodiment of the invention, the side structure in the isolation region is removed, so that the protrusion possibly positioned in the side structure between the dummy gates can be removed at the same time, the damage of the metal gate caused by the protrusion in the subsequent process is avoided, and the performance of the device is improved.
It should be noted that, when the side structure only includes the side wall formed on the side of the dummy gate, the target transverse isolation trench may be formed by deleting only the side wall in the isolation region. In a further embodiment, the side structure may further include an interlayer dielectric layer located between the sidewalls and used for isolating the device structure, so that the device structure located at the side of the dummy gate may be completely removed, and thus the target cross-cut structure formed in the isolation region is a through-trench, which further completely removes a structure where a protrusion may occur and facilitates complete filling of a subsequent cross-cut isolation structure.
In order to further and completely remove the protrusion located on the side of the dummy gate, in the embodiment of the present invention, the isolation region is further configured to cover the sidewall of the dummy gate located at the edge of the isolation region, the sidewall being close to the edge of the isolation region, so that in this step, the side structure that may have the protrusion is further and completely removed.
In the embodiment of the invention, the removal of the dummy gate intersected in the isolation region and the removal of the side structure in the isolation region can be simultaneously performed, so that the process flow can be simplified, and the process cost can be reduced.
Specifically, the removing the dummy gate crossing the isolation region and the removing the side structure in the isolation region simultaneously may include:
referring to fig. 12, a patterned isolation mask layer is formed on the substrate, exposing the isolation regions.
The isolation mask layer can be a hard mask layer or a photoresist mask layer and can be formed through photoetching and etching or a photoetching process, and the isolation region is exposed through the isolation mask layer so as to facilitate the corresponding process flow of the structure in the isolation region.
In the embodiment of the present invention, the isolation mask layer may be the first mask layer 260, and the step of forming the corresponding isolation mask layer may be performed in a step of removing the hard mask layer and the interlayer dielectric layer with a partial thickness in the isolation region to expose the dummy gate, so as to simplify the process flow in the embodiment.
Referring to fig. 13, the isolation mask layer 260 is used as a mask to etch and remove the dummy gate 220 intersecting the isolation region 20A and the side structure in the isolation region.
The process flow is simplified by simultaneously removing the dummy gate 220 that intersects within the isolation region 20A and the side structures within the isolation region.
Specifically, in the embodiment of the present invention, the dummy gate 220 intersecting with the isolation region 20A and the side structure in the isolation region may be removed by etching using a dry etching process. Different process gases are used in the dry etching process, depending on the materials of the dummy gate 220 and the side structure. Specifically, in the dry etching process, the process gas for removing the pseudo gate by etching is chlorine-containing gas, and the pressure is 50 mt-100 mt; the process gas adopted for removing the side structure by etching is fluorine-containing gas, and the pressure is 0 mt-20 mt. Wherein the chlorine-containing gas comprises chlorine, and the flow rate of the chlorine is 0 sccm-300 sccm; the fluorine-containing gas comprises CH2F2And CF4，CH2F2The flow rate of (1) is 0sccm to 50sccm, CF4The flow rate of (b) is 60sccm to 100 sccm.
It should be noted that, in order to ensure that the etching process has good anisotropic characteristics, thereby avoiding damage to other structures in the substrate, the gas pressure in the embodiment of the present invention is generally low, so that the corresponding etching ions have high sag.
After removing the dummy gate 220 in the isolation region 20A and the side structures in the isolation region, the isolation mask layer is further removed to provide a process space for a subsequent formation process.
Next, referring to fig. 14-15, a crosscut isolation structure 270 is formed filling the target crosscut isolation trench. Fig. 15 is a sectional view taken along direction CC' of fig. 14.
Isolation of the device structure is achieved by forming a lateral isolation structure 270 filling the target lateral isolation trench. The material of the lateral isolation structure 270 may be an insulating material, so as to electrically isolate the device structures.
The material of the transverse cutting isolation structure 270 may be one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In an embodiment of the present invention, the material of the lateral isolation structure 270 may be silicon nitride.
In an embodiment of the present invention, the process of forming the lateral isolation structure filling the target lateral isolation trench may include: forming a transverse cutting isolation material which completely covers one side of the substrate with the transverse cutting isolation groove; the substrate surface is polished to remove the cross-cut isolation material, and the cross-cut isolation material in the target cross-cut isolation trench is retained as the cross-cut isolation structure 270.
The process of forming the transverse isolation material may be a Flow Chemical Vapor Deposition (FCVD) process. The grinding process can be chemical mechanical grinding so that the transverse isolation structure forms good morphological characteristics.
In the embodiment of the present invention, after forming the lateral isolation structure filling the target lateral isolation trench, the following process may be further included:
referring to fig. 16, the dummy gate remaining on the substrate is removed by wet etching to form a gate trench 281.
The dummy gate is removed to form a gate trench 281, which is used to provide a process space for forming a metal gate.
In order to completely remove the residual pseudo grid and the isolation mask layer on the substrate, a wet etching process is adopted in the step to remove the pseudo grid and the isolation mask layer. Specifically, the etching of the dummy gate may be performed using an acidic oxidation etching solution such as a mixed solution of nitric acid (HN) and hydrofluoric acid (HF).
It should be noted that, in the process of removing the dummy gate, a hard mask layer is further formed on the dummy gate, and correspondingly, in this step, the hard mask layer is removed first to expose the dummy gate, so as to remove the dummy gate.
In the embodiment of the present invention, the side structure where the protrusion may be formed has been removed, so that the process of forming the gate trench in this step does not form a void corresponding to the protrusion portion based on the protrusion in the side structure.
Referring to fig. 16 to 18, a metal gate 280 is formed in the gate trench 281; fig. 18 is a cross-sectional view of the bitmap 17 taken along the DD'.
Specifically, after the gate trench 281 is formed, a metal material may be formed in the gate trench 281 by a deposition, plating, or the like, and the metal material outside the gate trench may be removed by a polishing process to form the metal gate 280 in the gate trench 281.
It should be noted that, in the forming process of the embodiment of the present invention, the metal gate 280 is formed to include an isolation gate 282 serving as an isolation gate in addition to a metal conductive gate serving as a gate structure in a device structure. The isolation gate 282 is used for etching removal in subsequent steps and forms a truncated isolation structure at a corresponding spatial position, thereby achieving isolation between device structures.
In the embodiment of the present invention, the side structure where the protrusion may be formed has been removed, the process of correspondingly forming the gate trench does not form a void corresponding to the protrusion portion based on the protrusion in the side structure, and further, the metal material formed in the void does not appear in this step.
Further, referring to fig. 18-20, the isolation gate 282 in the metal gate 280 is removed by wet etching to form a cut isolation trench 291. Fig. 20 is a sectional view taken along direction DD' in fig. 19.
Correspondingly, in this step, the isolation gate may be removed by wet etching or a combination process of wet etching and dry etching, which is not described herein again.
According to the embodiment of the invention, the side structure possibly provided with the protrusion is removed, the gap corresponding to the protrusion part is not formed on the basis of the protrusion in the side structure in the process of correspondingly forming the gate groove, and further, the metal material formed in the gap is not generated in the process of forming the metal gate, so that the etching liquid is not immersed into the metal gate which does not need to be etched through the corresponding gap in the step, or the etching liquid is further immersed into the metal gate which does not need to be etched after the metal material in the gap is removed through etching, and the damage to the gate structure of the device is avoided.
Further, referring to fig. 21, a truncated isolation structure 290 filling the truncated isolation trench is formed.
Isolation of the device structure is achieved by forming a truncated isolation structure 290 that fills the truncated isolation trench. The material of the intercepting isolation structures 290 may be an insulating material, so as to electrically isolate the device structures.
The blocking isolation structure 290 may be one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In an embodiment of the present invention, the intercepting isolation structures 290 may be silicon nitride.
In an embodiment of the present invention, the process of forming the intercepting isolation structure 290 filling the intercepting isolation trench may include: forming a truncated isolation material completely covering one side of the substrate having the truncated isolation trench; the truncated isolation material on the substrate surface is removed by grinding, and the truncated isolation material in the truncated isolation trench is retained as the truncated isolation structure 290.
The process of forming the cutoff isolation material may be a Flowable Chemical Vapor Deposition process (FCVD). The grinding process may be chemical mechanical grinding to form the truncated isolation structures with good topography.
An embodiment of the present invention further provides a semiconductor structure, referring to fig. 22-24, where fig. 23 is a cross-sectional view taken along EE 'in fig. 22, and fig. 24 is a cross-sectional view taken along FF' in fig. 22, including:
the substrate 300 includes a substrate 301, a plurality of parallel dummy gates 320 on the substrate, and side structures 330 on two sides of the dummy gates, wherein the substrate 300 includes an isolation region 30A, and an extending direction of the isolation region 30A intersects with the plurality of parallel dummy gates 320.
The isolation region 30A provides the substrate 300 with a region targeted to traverse an isolation trench that traverses a portion of the structure of the plurality of parallel dummy gates 320 and a portion of the structure of the side portion between the plurality of parallel dummy gates.
It should be noted that the target intersecting isolation trench 370 is used to cut off the dummy gate in the dummy gate extending direction, so as to isolate a plurality of corresponding device structures in the dummy gate extending direction. It should be noted that, in order to facilitate the semiconductor integration process, the target is to cut off the parallel dummy gates in the direction perpendicular to the extension direction of the dummy gates at the same time across the isolation trenches to isolate the device structures at the same time. Correspondingly, the extension direction of the isolation region is perpendicular to the extension direction of the plurality of parallel dummy gates and intersects with the dummy gates.
The width of the isolation region 30A should not be too large or too small, and if the width of the isolation region 30A is too large, the width of a subsequently formed target transverse isolation trench is also correspondingly too large, which occupies too much space and is not beneficial to reducing the size of a semiconductor structure; if the width of the isolation region 30A is too small, the width of the target transversal isolation trench correspondingly set is also too small, which is not favorable for the isolation device. Accordingly, the width of the isolation region may be 10 nm to 30 nm.
The substrate 301 is used to provide support for other structures. In the embodiment of the present invention, the material of the substrate 301 may be silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration. The surface of the substrate 301 may also be formed with an interface layer, and the interface layer is made of silicon oxide, silicon nitride, silicon oxynitride, or the like.
The dummy gate 320 occupies a space for a metal gate structure formed in a subsequent process. The dummy gate 320 may be polysilicon, and in other embodiments, the material of the dummy gate 320 may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon.
In the device structure forming process, in order to simultaneously form a plurality of device structures, a plurality of parallel dummy gates are usually simultaneously formed on the substrate, so that corresponding processing is simultaneously performed in the device forming process, and the process flow is simplified.
In an embodiment of the invention, the substrate further includes a discrete fin portion protruding from the substrate, and the plurality of dummy gates cross over the fin portion. The material of the fin portion may be the same as or different from the material of the substrate. The dummy gate crosses over the discrete fin portion, so that the fin portion is used as a channel structure to control a device.
Side structures are formed on two sides of the dummy gate 320, and the side structures are used for providing isolation, support, and definition of a process space for the dummy gate 320.
In the embodiment of the present invention, the side structure may include side walls 330 located at two sides of the dummy gate, and the side walls 330 may define a formation region of the source-drain doping layer. Further, in the embodiment of the present invention, the side structure may further include an interlayer dielectric layer 340 located between adjacent sidewalls 330, where the interlayer dielectric layer 340 is used to isolate different device structures, and further define a process space for the device.
The material of the sidewall spacers 330 may be silicon nitride. In other embodiments of the present invention, the sidewall spacer may also be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
The interlayer dielectric layer 340 is made of an insulating material. In this embodiment, the interlayer dielectric layer 340 is made of silicon oxide. In other embodiments, the material of the interlayer dielectric layer 340 may also be other dielectric materials such as silicon nitride or silicon oxynitride.
In the embodiment of the present invention, a hard mask layer 350 may be further formed on the dummy gate 320, and the side structures (including the sidewall spacers 330 and the interlayer dielectric layer 340) are flush with the hard mask layer 350. The hard mask layer 350 is used to protect the dummy gate, the hard mask layer 350 may be made of silicon nitride, and in other embodiments, the hard mask layer 350 may also be made of silicon oxynitride.
Further, the semiconductor structure further comprises: a cross-cut isolation structure 370 within the isolation region 30A, the cross-cut isolation structure 370 isolating the plurality of parallel dummy gates 320 and side structures between the plurality of parallel dummy gates 320.
Optionally, the cross-cut isolation structure 370 is used to implement isolation of the device structure. The material of the lateral isolation structure 370 may be an insulating material, so as to electrically isolate the device structures.
The material of the transverse isolation structure 370 may be one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In an embodiment of the present invention, the material of the lateral isolation structure 370 may be silicon nitride.
Based on the embodiment of the invention, the side structure possibly provided with the protrusion is removed, the process of correspondingly forming the gate groove does not form the gap corresponding to the protrusion part based on the protrusion in the side structure, and further the metal material formed in the gap is not generated in the process of forming the metal gate, so that the etching liquid is not immersed into the metal gate which does not need to be etched through the corresponding gap in the step, or the etching liquid is further immersed into the metal gate which does not need to be etched after the metal material in the gap is removed through etching, and the damage to the gate structure of the device is avoided.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate, a plurality of parallel dummy gates on the substrate and side structures on two sides of the dummy gates, the base comprises an isolation region, and the extension direction of the isolation region intersects with the plurality of parallel dummy gates;
removing the dummy gates intersected in the isolation region to form an initial transverse isolation trench transversely intersecting the plurality of parallel dummy gates;
removing the side structure in the isolation region to form a target transverse cutting isolation groove;
and forming a transverse isolation structure for filling the target transverse isolation trench.
2. The method of claim 1, wherein the side structures comprise at least spacers formed on sides of the dummy gates.
3. The method of forming a semiconductor structure of claim 2, wherein the side structures further comprise an interlevel dielectric layer between the sidewalls.
4. The method of claim 1, wherein the isolation region covers a portion of the structure of the plurality of parallel dummy gates and a portion of the side structure between the plurality of parallel dummy gates.
5. The method for forming the semiconductor structure according to claim 4, wherein the isolation region further covers a sidewall of the dummy gate at the edge of the isolation region on a side close to the edge of the isolation region.
6. The method of forming a semiconductor structure of claim 1, wherein said removing dummy gates that intersect within the isolation region and said removing side structures within the isolation region are performed simultaneously.
7. The method of forming a semiconductor structure of claim 6, wherein said removing dummy gates that intersect within the isolation region and said removing side structures within the isolation region are performed simultaneously, comprising:
forming a graphical isolation mask layer on the substrate, wherein the isolation mask layer exposes the isolation region;
and etching and removing the pseudo gate intersected in the isolation region and the side structure in the isolation region by taking the isolation mask layer as a mask.
8. The method for forming a semiconductor structure according to claim 7, wherein the dummy gate crossing the isolation region and the side structure crossing the isolation region are etched away by a dry etching process.
9. The method for forming a semiconductor structure according to claim 8, wherein in the dry etching process, the process gas for removing the dummy gate by etching is a chlorine-containing gas, and the pressure is 50mt to 100 mt; the process gas adopted for removing the side structure by etching is fluorine-containing gas, and the pressure is 0 mt-20 mt.
10. The method according to claim 9, wherein the chlorine-containing gas comprises chlorine gas, and the flow rate of the chlorine gas is 0sccm to 300 sccm; the fluorine-containing gas comprises CH2F2And CF4，CH2F2The flow rate of (1) is 0sccm to 50sccm, CF4The flow rate of (b) is 60sccm to 100 sccm.
11. The method of claim 1, wherein a hard mask layer is further formed on the dummy gate, and the side structures are flush with the hard mask layer; after the step of providing the substrate and before the step of removing the dummy gate intersecting in the isolation region, the method further includes: and removing the hard mask layer and the side structure with partial thickness in the isolation region to expose the pseudo gate.
12. The method of forming a semiconductor structure of claim 1, wherein said forming a cross-cut isolation structure filling said target cross-cut isolation trench comprises:
forming a transverse cutting isolation material which completely covers one side of the substrate with the transverse cutting isolation groove;
and grinding and removing the isolation material on the surface of the substrate, and reserving the transverse cutting isolation material in the target transverse cutting isolation groove as the transverse cutting isolation structure.
13. The method of forming a semiconductor structure of claim 1, wherein after forming the crosscut isolation structure filling the target crosscut isolation trench, further comprising:
removing the residual pseudo grid on the substrate by adopting wet etching to form a grid groove;
forming a metal gate in the gate trench;
removing the isolation grid in the metal grid by adopting wet etching to form a cut-off isolation groove;
and forming a cut-off isolation structure filling the cut-off groove.
14. The method of claim 13, wherein the base further comprises a discrete fin raised above the substrate, the plurality of parallel dummy gates crossing the fin; after removing the isolation gate in the metal gate and before forming the cut isolation structure filling the cut trench, the method further includes:
and removing the fin part below the isolation grid electrode to enable the cut-off isolation groove to extend to the substrate.
15. The method of forming a semiconductor structure of claim 1, wherein the material of the lateral isolation structure comprises: one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
16. A semiconductor structure, comprising:
the substrate comprises a substrate, a plurality of parallel dummy gates on the substrate and side structures on two sides of the dummy gates, wherein the substrate comprises an isolation region, and the extension direction of the isolation region is intersected with the plurality of parallel dummy gates;
a cross-cut isolation structure within the isolation region, the cross-cut isolation structure isolating the plurality of parallel dummy gates and side structures between the plurality of parallel dummy gates.
17. The semiconductor structure of claim 16, wherein the side structures comprise at least spacers formed on sides of the dummy gates.
18. The semiconductor structure of claim 17, wherein the side structures further comprise an interlevel dielectric layer between the sidewalls.
19. The semiconductor structure of claim 16, wherein the isolation region covers a portion of the structure of the plurality of parallel dummy gates and a portion of the side structure between the plurality of parallel dummy gates.
20. The semiconductor structure of claim 19, wherein the isolation region further covers a portion of the sidewall of the dummy gate at the edge of the isolation region on a side close to the edge of the isolation region.
CN202010562009.7A 2020-06-18 2020-06-18 Semiconductor structure and forming method thereof Pending CN113823596A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1123470A (en) * 1994-09-13 1996-05-29 株式会社东芝 Insulated-gate device (IG device) having narrowbandgap-source structure and method of manufacturing the same
US20030001196A1 (en) * 2001-06-28 2003-01-02 Samsung Electronics Co., Ltd. Non-volatile memory device and method of fabricating the same
US20030127697A1 (en) * 2002-01-10 2003-07-10 Hiroyuki Ohta Semiconductor device
US20190148242A1 (en) * 2017-11-14 2019-05-16 Globalfoundries Inc. Forming single diffusion break and end isolation region after metal gate replacement, and related structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1123470A (en) * 1994-09-13 1996-05-29 株式会社东芝 Insulated-gate device (IG device) having narrowbandgap-source structure and method of manufacturing the same
US20030001196A1 (en) * 2001-06-28 2003-01-02 Samsung Electronics Co., Ltd. Non-volatile memory device and method of fabricating the same
US20030127697A1 (en) * 2002-01-10 2003-07-10 Hiroyuki Ohta Semiconductor device
US20190148242A1 (en) * 2017-11-14 2019-05-16 Globalfoundries Inc. Forming single diffusion break and end isolation region after metal gate replacement, and related structure

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