CN113703799B - Computing device and BIOS updating method and medium thereof - Google Patents

Abstract

The application relates to the field of computers, and discloses a computing device, and a method and medium for updating a BIOS (basic input output system) of the computing device. The updating method of the BIOS system comprises the following steps: the operating system of the computing device enters a sleep state; restarting the basic input/output system after the operating system enters a dormant state; the basic input/output system acquires an update file of the basic input/output system, and executes the update of the basic input/output system based on the acquired update file; and after the basic input and output system finishes updating, the operating system wakes up from the dormant state. The updating of the BIOS system can be completed after the operating system of the computing device enters the dormant state, the computing device is not required to be restarted, and the working state of the operating system can be maintained before and after the updating of the BIOS system.

Description

Computing device and BIOS updating method and medium thereof

Technical Field

The application relates to the field of computers, and more particularly discloses a computing device, a BIOS updating method and a medium thereof.

Background

The basic input output system (Basic Input Output System, BIOS) is usually a set of programs stored in a nonvolatile memory on a computer motherboard, including the most important basic input output program of a terminal, a self-checking program after power-on, a system self-starting program, and the like, which are one of the bases of the terminal system. With the rapid development of computers, BIOS is updated more and more frequently as the most important bottom firmware of PCs. The iteration and update of the BIOS can better solve the product problems, such as security holes and product design problems of hardware such as a CPU (Central Processing Unit ), so as to improve the user experience.

However, since the BIOS update requires a system restart, the current operation of the system cannot be saved, so the user will not update the system much, and in addition, the BIOS cannot force the push update.

Disclosure of Invention

The application aims to provide a computing device, a BIOS updating method and a BIOS updating medium thereof, which realize the updating of the BIOS without restarting an operating system, thereby saving the current operation of the operating system.

In a first aspect, an embodiment of the present application provides a method for updating a basic input output system of a computing device, including: an operating system of the computing device enters a sleep state; restarting the basic input and output system after the operating system enters a dormant state; the basic input/output system acquires an update file of the basic input/output system, and executes the update of the basic input/output system based on the acquired update file; and after the basic input and output system finishes updating, the operating system wakes up from the dormant state.

That is, in this method, the OS is put into a sleep state, and the BIOS is turned off. The BIOS is then restarted so that the BIOS begins to update and wakes up the OS after the BIOS update is completed. Thereby saving the current operation of the OS while completing the BIOS update.

In one implementation of the first aspect, the entering the sleep state by the operating system of the computing device includes: and the updating program of the basic input/output system sends a dormancy instruction to the operating system, and the operating system enters a dormancy state. Specifically, the update program of the BIOS may send a sleep instruction to the CPU of the computing device through the BIOS, the CPU turns off the power supply, and the OS enters a sleep state.

In an implementation of the first aspect, restarting the bios after the os enters the sleep state includes: after the operating system enters a dormant state, the embedded controller of the computing device resets the central processor of the computing device to restart the basic input and output system.

After the OS enters the sleep state, the EC of the embedded controller decoupled from the OS is still in a working state, so the EC decoupled from the OS can be used to reset the CPU, thereby restarting the BIOS for updating.

In one implementation of the first aspect, the method further includes: before the operating system enters a dormant state, the basic input/output system sets a wake-up flag bit for the embedded controller, wherein the embedded controller resets the central processing unit after acquiring the wake-up flag bit.

In one implementation of the first aspect, the method further includes: and deleting the wake-up flag bit by the embedded controller after resetting the central processing unit.

In one implementation of the first aspect, the bios performs the updating of the bios by: the basic input/output system writes the updated file into a basic input/output system chip of the computing device; the basic input output system resets the central processing unit of the computing device so as to load the updated file in the basic input output system chip into the memory of the computing device.

That is, after the BIOS writes the update file of the BIOS into the BIOS chip, the BIOS needs to be reset to load the update file of the BIOS into the memory to complete the update of the BIOS.

In an implementation of the first aspect, after the bios completes updating, waking up the operating system from the sleep state includes: reading related data before the operating system enters a dormant state from a hard disk of the computing device; and returning the operating system to the working state before entering the dormant state based on the acquired related data.

In a second aspect, an embodiment of the present application discloses a method for updating a basic input output system of a computing device, including: the basic input and output system sends a dormancy instruction acquired from an updating program of the basic input and output system to an operating system of the computing equipment, wherein the dormancy instruction is used for instructing the operating system to enter a dormancy state; restarting the basic input/output system; the basic input/output system acquires an update file of the basic input/output system; and the basic input/output system performs updating of the basic input/output system based on the acquired updating file.

That is, in this method, the OS is put into a sleep state, and the BIOS is turned off. The BIOS is then restarted so that the BIOS begins to update and wakes up the OS after the BIOS update is completed. Thereby saving the current operation of the OS while completing the BIOS update.

In one implementation of the second aspect, the updating of the bios by the bios based on the acquired update file includes: the basic input/output system writes the updated file into a basic input/output system chip of the computing device; the basic input and output system restarts the central processing unit of the computing device to load the update file in the basic input and output system chip into the memory of the computing device.

In a third aspect, an embodiment of the present application discloses a method for updating a basic input output system of a computing device, including: the embedded controller of the computing device detects that the power state of the central processing unit of the computing device is a dormant state; the embedded controller resets the central processing unit to restart the basic input output system of the computing device to update the basic input output system.

In one implementation of the third aspect, the resetting the central processor by the embedded controller includes:

And under the condition that the embedded controller acquires the wake-up flag bit, resetting the central processing unit.

In one implementation of the third aspect, the method further includes:

The embedded controller detects that the basic input and output system writes an update file of the basic input and output system into a basic input and output system chip of the computing device; the embedded controller resets the central processor of the computing device to write the update file into the memory of the computing device.

In a fourth aspect, embodiments of the present application disclose a readable medium of a computing device having stored thereon instructions that, when executed on a computing device, cause the computing device to perform the method of the first or second aspect described above.

In a fifth aspect, embodiments of the present application disclose a computing device comprising: a memory and a controller;

Wherein the memory is to store instructions for execution by one or more controllers of the computing device;

the controller comprises a central processor and an embedded controller for executing the method described in the first or second aspect.

Drawings

Fig. 1 is a schematic diagram of a computer 100 according to an embodiment of the present application.

Fig. 2 is a BIOS update control system 200 according to an embodiment of the application.

FIG. 3 is a flowchart of a BIOS update method according to an embodiment of the application.

FIG. 4 (a) is a diagram of an operating system display interface prior to BIOS update according to an embodiment of the application.

FIG. 4 (b) is a diagram of an operating system display interface after BIOS update according to an embodiment of the application.

FIG. 5 is a schematic diagram of an example computing device according to an embodiment of the application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that some alternative embodiments may be practiced using the features described in part. For purposes of explanation, specific numbers and configurations are set forth in order to provide a more thorough understanding of the illustrative embodiments. However, it will be apparent to one skilled in the art that the alternative embodiments may be practiced without the specific details. In some other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments of the application. It should be noted that in the present specification, like reference numerals and letters denote like items in the following drawings.

In various electronic devices such as computers, the BIOS is very important bottom firmware, and iteration and update of the BIOS can better solve product problems, such as security holes of hardware such as CPU and product design problems, so as to improve user experience. However, updating of the BIOS typically requires a system restart, resulting in current operation of the system being unable to save. The embodiment of the application provides a scheme capable of updating BIOS and simultaneously saving current operation based on the situation.

Illustrative embodiments of the application include, but are not limited to, BIOS update methods, apparatus, media, devices, systems, and the like.

Embodiments of the application may be applied to a variety of electronic devices with embedded controllers (Embedded Controller, EC), such as personal computers, notebook computers, desktop, hand-held or laptop computers, tablet computers, portable gaming devices, servers, and the like.

Next, taking the computer 100 as an example, a schematic structural diagram of an electronic device according to an embodiment of the present application will be described with reference to fig. 1.

As shown in fig. 1, the computer 100 may include a main processor 110, a memory 120, an input device 130, an embedded controller 140, a graphic card 150, a display 151, a power supply 160, a sensor 170, and an audio module 180, etc.

It should be understood that the architecture shown in the exemplary embodiment of the present application is not intended to limit the computer 100 to any particular configuration. In other embodiments of the application, computer 100 may include more or less components than illustrated, or certain components may be combined, or certain components may be split, or different arrangements of components and/or different architectures. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The main processor 110 is a control center of the computer 100, connects various parts of the entire computer 100 using various interfaces and lines, and performs various functions and data processing of the computer 100 by running or executing software programs and/or data stored in the memory 120, thereby controlling the computer 100 as a whole. For example, the main processor 110 may perform related operations performed by the CPU 222 and the like described later in connection with fig. 2 and 3 to implement the functions provided by the embodiments of the present application.

The main processor 110 may include one or more processing units, wherein different processing units may be separate devices or may be integrated in one or more processors. A memory may also be provided in the main processor 110 for storing instructions and data. In some embodiments, the memory in the main processor 110 is a cache memory. The memory may hold instructions or data that is just used or recycled by the main processor 110. If the main processor 110 needs to reuse the instruction or data, it can be called directly from the memory. Repeated accesses are avoided and the latency of the main processor 110 is reduced, thereby improving the efficiency of the system.

The memory 120 may include any suitable non-volatile memory and/or any suitable non-volatile storage device, such as flash memory, a hard disk drive (HARD DISK DRIVE, HDD), a solid state drive (solid-STATE DRIVE, SSD), a Compact Disk (CD) drive, and/or a digital versatile disk (DIGITAL VERSATILE DISK, DVD) drive, among others. Memory 120 may be used to store computer-executable program code that includes instructions. According to some embodiments of the present application, the memory 120 may include a storage program area and a storage data area. The storage program area may store an operating system, an application program required for at least one function (such as a function of controlling the computer 100 to enter a sleep state, a function of waking up the computer 100, etc.), and the like. The storage data area may store data (e.g., audio data, image data, etc.) created during use of the computer 100, and the like. The main processor 110 performs various functional applications of the computer 100 and data processing by executing instructions stored in the memory 120 and/or instructions stored in a memory provided in the processor.

The input device 130 may be used to receive input digital information, character information, or touch operation/non-contact gestures, and to generate signal inputs related to user settings and function controls of the computer 100, etc.

Specifically, according to some embodiments of the present application, the input device 130 may include a touch panel 131, a keyboard 132, and a mouse 133. The touch panel 131 may be used to collect touch operations on or near the user (e.g., operations of the user on the touch panel 131 using any suitable object or accessory such as a finger, a stylus, etc.), and to drive the corresponding connection device according to a preset program. Characters, numbers, punctuation marks, etc. may be entered into the computer 100 through the keyboard 132, and commands may be issued to the computer 100 through function keys on the keyboard 132. The mouse 133 can position the cursor on the current display 151, and operate the screen element at the position where the cursor passes through the key and the roller device, so as to trigger the computer 100 to execute the corresponding command.

According to some embodiments of the present application, computer 100 may also include other input devices that may include, but are not limited to, any one or more of function keys (such as volume control keys, switch keys, etc.), trackballs, light pens, joysticks, and the like.

The embedded controller (Embedded Controller, EC) 140 is a control system for performing specified independent control functions and having complex processing data capabilities. During system start-up, the EC 140 controls the timing of most of the important signals. For example, in embodiments of the application below, the EC 140 wakes up the BIOS by starting the CPU 222 to perform a BIOS update.

The display 151 may be used to display information input by a user or information provided to a user, such as various menu interfaces of the computer 100, and the like. The display 151 includes a display panel. The display panel may employ a Liquid Crystal Display (LCD) CRYSTAL DISPLAY, an organic light-emitting diode (OLED), an active-matrix organic LIGHT EMITTING diode (AMOLED), a flexible light-emitting diode (FLED), miniled, microLed, micro-oLed, a quantum dot LIGHT EMITTING diode (QLED), or the like. Alternatively, the display screen 151 may be configured in the form of a Liquid Crystal Display (LCD) CRYSTAL DISPLAY or an organic light-emitting diode (OLED) or the like. In some embodiments, a portion of the touch panel 131 may be integrated with the display 151 to form a touch display.

The graphics card 150 may include a graphics processing unit (graphics processing unit, GPU) or a video processing unit (Video Processing Unit, VPU) for converting digital signals input into the computer 100 into analog signals and causing the display 151 to display the converted analog signals, and the graphics card 150 may also have image processing capabilities, and the processed images are displayed on the display 151. The graphics card 150 may be integrated on the motherboard of the computer 100 or may be separate from the motherboard of the computer 100.

The power supply 160 is used to power other modules, and the power supply 160 may include a charge management module and a power management module. The charge management module is to receive a charge input from a charger. The charger can be a wireless charger or a wired charger. The charging management module can also supply power to the electronic equipment through the power management module while charging the battery. The power management module is configured to receive input from the battery and/or the charge management module and to power the various modules within the computer 100. The power management module can also be used for monitoring parameters such as battery capacity, battery cycle times, battery health status (leakage, impedance) and the like.

The computer 100 may include one or more sensors 170 for sensing various information and converting the sensed information into electrical signals or other desired forms of information output according to a certain rule. In an embodiment of the present application, the sensor 170 may include various types of sensors, such as an image sensor, a brightness sensor, a light sensor, a GPS sensor, an infrared sensor, and the like.

Computer 100 may implement audio functions via audio module 180, speaker 181, microphone 182, headphone interface 183, and host processor 110, among others. Such as music playing, recording, etc.

The audio module 180 is used to convert digital audio information into an analog audio signal output and also to convert an analog audio input into a digital audio signal. The audio module 180 may also be used to encode and decode audio signals. In some embodiments, the audio module 180 may be provided in the main processor 110, or some functional modules of the audio module 180 may be provided in the main processor 110.

The speaker 181 is used to convert an audio electric signal into a sound signal. The computer 100 may output sound through the speaker 181.

The microphone 182 is used to pick up sound signals and convert the sound signals into electrical signals. The computer 100 may be provided with at least one microphone 182. In other embodiments, the computer 100 may be provided with two microphones 182, which may perform a noise reduction function in addition to collecting sound signals. In other embodiments, the computer 100 may also be provided with three, four or more microphones 182 to enable collection of sound signals, noise reduction, identification of sound sources, directional recording functions, etc.

The headphone interface 183 is for connecting a wired headphone. The headphone interface 183 may be a USB interface, a 3.5mm open mobile electronic device platform (open mobile terminal platform, OMTP) standard interface, a american cellular telecommunications industry association (cellular telecommunications industry association of the USA, CTIA) standard interface, or the like.

The computer 100 may further include a Radio Frequency (RF) circuit 191 for performing network communication with a wireless network device, and a WIFI module 192 for performing WIFI communication with other devices, acquiring data transmitted by the other devices, and so on.

A BIOS update control system 200 according to an embodiment of the application is described below in conjunction with fig. 2. The update control system 200 may be implemented in a computer 100 as shown in fig. 1.

The update control System 200 may include a Software (SW) part 210 and a Hardware (HW) part 220, the Software 210 part including a basic input output System (Basic Input Output System, BIOS) 211 and an Operating System (OS) 212, and the Hardware 220 part may include a hard disk 221, a central processor (Central Processing Unit, CPU) 222, a BIOS chip 223 and an Embedded Controller (EC) 224.

The OS 212 is a computer program that manages hardware and software resources in a computer, and is mainly used to handle basic transactions such as managing and configuring memory, prioritizing supply and demand of system resources, controlling input devices and output devices, operating networks, and managing file systems. The OS 212 may perform scheduling tasks on various resources of the computer system, including hardware and software devices, as well as data, information, etc., while also providing an interface for a user to interact with the computer 100. Common operating systems include, but are not limited to: windows, android, IOS, etc. It will be appreciated that in embodiments of the present application, OS 212 is decoupled from EC 224, and that after OS 212 sleeps, EC 224 continues to operate, performing functions such as waking up CPU 222.

The BIOS 211 is a set of programs in the BIOS chip 223 solidified on the computer motherboard, including the most important basic input/output program, the boot self-test program and the system self-start program of the computer, and is used for directly performing hardware-level control on the input/output device in the computer system, so as to provide a foundation for establishing connection between other software programs and hardware devices. The BIOS 211 is a program that is executed first after the computer is powered on, and performs functions such as initialization setting and testing on each hardware device of the system, so as to ensure that the system can work normally. After the initialization of the hardware resources by the BIOS 211, the OS 212 operates to perform various services through the initialized hardware resources.

Specifically, from the time the host of the computer 100 is powered up to load a bootloader, i.e., the BIOS 211 completes the boot task and enters an idle state, the BIOS 211 mainly undergoes three phases: pown On (inactive power phase), POST (Power on selftes t ), and bootloader. Wherein:

1) The main task of stage Pown On is to check if the content in the CMOS (Complementary Metal Oxide Semiconductor ) is correct, check the status of certain hardware on the host to determine the next self-test.

2) Stage POST (power on self test) checks whether some key devices such as memory and display card can work normally or not, and provides simple memory test, and as long as the test has no problem, the basic information of the hardware is displayed on the screen. Generally, the basic process of BIOS 211 in the POST phase is as follows: BIOS 211 searches the BIOS code of the display card, then calls the initialization code of the display card, the BIOS of the display card completes the initialization of the display card, and then the screen can display information; subsequently, the BIOS 211 invokes the BIOS code of the found other device to complete the initialization of the corresponding device, and so on. After checking other devices, the BIOS 211 will display its own startup screen, and then check the type and operating frequency of the CPU 222, the memory capacity of the computer, etc.; the BIOS 211 then begins testing and configuring some standard hardware devices installed in the system, such as hard disk, optical drive, interface, etc., and the BIOS 211 then checks and configures the plug-and-play devices in the computer system. Generally, all needed devices are activated during the POST phase at power-on and after power-on.

3) In the bootloader loading phase, the BIOS drop to is to give the master control right of the loading OS to the MBR (Master Boot Record, master boot sector) of the hard disk, that is, the contents on the physical sector 0-column 0-plane 1 sector of the hard disk, so that the boot manager (bootloader) hidden in the memory brings the pointer to the place of the system core.

Further, it will be appreciated that in some embodiments of the application, BIOS 211 exits after OS 212 enters a sleep state, and can be restarted after CPU222 is reset. As will be described in detail below.

The hard disk 221 is one of the most important memories in a computer. Most of the applications and data required for the computer to function properly are stored on the hard disk 221. The hard disk 221 may include, but is not limited to: solid state disk drives (Solid STATE DRIVE, SSD for short), mechanical hard disk drives (HARD DISK DRIVE, HDD), and the like. In updating BIOS211, the BIOS update tool may initially store a binary (bin) file of the BIOS into hard disk 221. It should be appreciated that in embodiments of the present application, the storage location of the bin file of the BIOS is not limited to the hard disk 221, and in some embodiments, the bin file of the BIOS (i.e., the update file of the BIOS) may be stored in various internal memories or accessible external storage devices, for example, may be stored in a mobile storage device such as a usb disk.

The CPU 222 is a core hardware unit that performs control allocation and general-purpose operation on all hardware resources of the computer 100. The CPU 222, which is the operation and control core of the computer 100, is the final execution unit for information processing and program execution, and the operations of all the software layers 210 in the computer system are mapped into the operations of the CPU 222 through the instruction set. In some embodiments of the present application, the update program of the BIOS sends a sleep instruction to the CPU 222 through the BIOS 211, and the Yes OS 212 enters a sleep state.

The BIOS chip 223 is a nonvolatile memory provided on the computer motherboard for storing the BIOS 211 described above, and it is not necessary to supply power to keep the data from being lost. The BIOS chip 223 may be a Read-Only Memory (ROM) chip or a Flash Memory (Flash) chip, etc. The BIOS chip is typically a flash ROM (flash read only memory) chip. Currently, the capacity of FlashROM chips is generally 1M or 2M up to 8M, and is roughly divided into 28 and 29 series. The 28 series flash rom chip is of a dual voltage design that can be read at a voltage of 5V, while the write must provide a voltage of 12V. When the main board of the chip is upgraded, the case is opened and jumper setting is changed. The 29 series flash ROM chip is relatively simple, and because the flash ROM chip adopts a single-voltage design, the read-write operation adopts 5V voltage, and therefore, the read-write Firmware operation can be completed only by software.

The embedded controller (Embedded Controller, EC) 224 is a control system for performing specified independent control functions and having complex processing data capabilities. EC 224 is used as a single processor, and can be realized by a single chip microcomputer, and has the function of global management on the whole system before and during the starting process. EC 224 performs control functions using logic programs (i.e., EC codes) stored in Flash, in some embodiments EC 224 itself may integrate a certain amount of Flash or the like to store the EC codes, in some embodiments EC 224 may not integrate Flash, but rather store the EC codes in BIOS chip 223.

During system start-up, EC 224 controls the timing of most important signals. In a computer, the EC 224 will always be on whenever the computer is powered on, whether the computer is in an on state or an off state, unless the battery and adapter are completely removed. In the off state, EC 224 remains running all the time and waits for the user's power on information. After the power is turned on, the EC 224 performs control or support functions of the keyboard, the fan, the charge and discharge, the indicator light, and the like, and is responsible for the tasks of keyboard, mouse, battery power and temperature control detection. In some embodiments, EC 224 is also used to control the standby, sleep, etc. states of the system.

The process of performing a BIOS update using the BIOS update control system 200 shown in fig. 2 is described below in connection with fig. 3.

First, S301: in the running state of the OS 212, the BIOS update tool is used to store a new BIOS bin file to a specified location of the hard disk of the computer, where the specified location is determined by a storage path of the BIOS bin file, and the file storage path may be set by default by the BIOS update tool or may be defined by a user. For example, a new BIOS bin file may be stored in an EFI System Partition (ESP) of hard disk 221 so that BIOS 211 may be directly accessed without a driver. It will be appreciated that the new BIOS bin file may also be stored in other partitions of the hard disk 221 or other storage devices of the computer 100.

S302: the update flag bit (update flag) is set by the BIOS 211 update tool, and the update flag can be used in the POST process of the BIOS 211 to enable the BIOS 211 to self-check whether an update is required.

S303-S304: the BIOS 211 update utility is utilized to inform the BIOS to send a sleep instruction to the CPU 222 to put the computer into a sleep state. Wherein, when the OS 212 enters the sleep state, the BIOS 211 also exits.

For example, as shown in fig. 4 (a), when the computer system enters the sleep state, the user may be reminded of the BIOS update to be performed on the computer through the display interface of the computer 100, and the computer system enters the sleep state immediately after the user clicks the confirm. If the user chooses to update later, the user may be reminded to update after a predetermined time. Or may also set the user with a choice of update time, such as 4 hours later, night time, etc.

According to some embodiments of the present application, the sleep instruction sent by the BIOS 211 to the CPU 222 may be an S4 sleep instruction to control the computer system to enter an S4 state, also referred to as a Suspend To Disk (STD) state. In the S4 state, the CPU 222 is powered off, the system main power is turned off, but the hard disk is still powered on and can be awakened, relevant data in operation is saved to the hard disk, and then all components are stopped. In the STD state, the current operation of the user is not lost, then the system can be awakened again by pressing a power key and the like, and after the system is awakened, the related data can be read from the hard disk and restored to the working state before STD.

According to other embodiments of the present application, the sleep instruction sent by the BIOS 211 to the CPU 222 may also be an S3 sleep instruction to control the computer system to enter an S3 state, also referred to as a Suspend To RAM (STR) state. In the STR state, the CPU 222 is also powered off and the operating state data before the system enters STR is stored in memory. In the STR state, the power supply still continues to supply power to the most necessary components such as the memory, so as to ensure that data is not lost, while other components are in the off state. Similarly, the system can be awakened again by pressing a power key and the like, and the system can immediately read data from the memory and restore to the working state before STR after being awakened. Since the memory is very fast to read and write, the time to enter and leave the STR state is shorter than the time to enter and leave the STD state. The system entering S3 or S4 sleep may be implemented through an advanced configuration and power interface (Advanced Configuration and Power Interface, ACPI).

Further, it is understood that in other embodiments, BIOS 211 may also send sleep instructions to CPU 222 via other systems co-located on computer 100, e.g., BIOS 211 may send sleep instructions to the CPU via OS 212.

S305: the operation of the BIOS 211 to configure the wake flag (i.e., the wake flag bit) for the EC 224 may be performed while the BIOS 211 sends the sleep instruction to the CPU 222, or may be performed before or after the operation of the BIOS 211 sending the sleep instruction to the CPU 222, according to some embodiments of the present application, but it is ensured that the operation of the BIOS 211 to configure the wake flag for the EC 224 is completed when the BIOS 211 has the operation authority, that is, before the CPU 222 sleeps. The wake-up flag is set before the CPU 222 sleeps, so that it can be ensured that after the computer system goes to sleep, the EC 224 can start the CPU 222 according to the obtained wake-up flag, thereby waking up the BIOS 211 to perform BIOS update.

Under normal conditions, after the BIOS 211 sends a sleep instruction to the CPU 222, the OS 212 and the BIOS 211 will enter a sleep state together, and in order to enable the BIOS to be awakened and updated, the embodiment of the application configures an awake flag for the EC 224 while sending the sleep instruction to the CPU 222. The wake-up flag is set in a location accessible to the EC 224, so that the EC 224 can wake up the BIOS 211 after reading the wake-up flag.

S306: the BIOS 211 is awakened with EC 224 and the wake flag is cleared.

Since the EC 224 will always be on with power on, the EC 224 will always remain on even if the computer goes to sleep and the previously set wake-up flag can be accessed. In an embodiment of the present application, EC 224 is configured to perform an operation of resetting CPU 222 after reading the wake flag, BIOS 211 is turned on after CPU 222 is reset, and clear the wake flag after BIOS 211 is turned on. The clear operation may be performed by the EC after accessing the wake-up flag; or may be performed by the BIOS 211, for example, the BIOS 211 sets the wake flag to clear when it is accessed.

S307-S308: after the BIOS 211 is turned on, a boot task is performed, and in the event that an update flag is detected in the POST stage (for example, an update flag of 1 is detected), a BIOS update operation is performed. As described above, the BIOS 211 enters the POST stage when executing the boot task, and when the BIOS 211 detects that the update flag is 1 in the POST stage, the BIOS update operation is executed, the BIOS bin file originally stored in the hard disk 221 is written into the BIOS chip 223, and the update flag is cleared.

Specifically, after the BIOS 211 detects that the update flag is 1 in the POST stage, the BIOS 211 may read a new BIOS file from a specified location of the hard disk 221, for example, read the new BIOS file from the above-mentioned ESP, and then verify the new BIOS file (for example, verify whether the new BIOS file carries a virus, detect the integrity of the new BIOS file, etc.), confirm that the new BIOS file that needs to be updated is stored in the ESP, and check whether the update condition is currently met. According to some embodiments of the present application, the upgrade condition may include whether the current power level of the computer device meets the upgrade requirement, etc., and the upgrade condition may be set in a customized manner, which is not limited herein.

When the BIOS 211 confirms that the new BIOS file to be updated is stored in the ESP, and the current computer device has the update condition, the preparation for the BIOS update is started, and the new BIOS file is written into the BIOS chip 223. After the new BIOS file writing action is completed, the read-write test can be performed, the test success indicates that the BIOS writing is successful, and if the test fails, the writing can be rewritten.

After the BIOS 211 writes the new BIOS file into the BIOS chip 223, the BIOS 211 sends a message to the EC 224 that the update file is successfully written into the BIOS chip 223, and the BIOS 211 restarts the CPU 222, and after the CPU 222 restarts, the new BIOS file in the BIOS chip 223 is loaded into the memory of the computer 100, so that the BIOS 211 completes the update.

In addition, it can be understood that in other embodiments, the EC 224 may instruct the CPU to restart, that is, after the BIOS 211 writes a new BIOS file into the BIOS chip 223, the BIOS 211 sends a message that the update file is successfully written into the BIOS chip 223 to the EC 224, the EC 224 causes the CPU 222 to restart, and after the CPU 222 restarts, the new BIOS file in the BIOS chip 223 is loaded into the memory of the computer 100, so that the BIOS 211 completes the update.

S309: after the updating of the BIOS211 is completed and the starting is successful, the OS 212 wakes up from the dormant state, enters into the S0 state, reads the relevant data from the memory or the hard disk, and resumes the working state before the dormancy, and the relevant operation of the system before the updating of the BIOS is saved. For example, as shown in fig. 4 (b), after the completion of the update of the BIOS211, the OS 212 enters S0 state, and the related operation before the update is saved. The S0 state of the OS 212 is a normal operating state of the OS 212, where the hardware devices of the computer 100 are basically all in an on state.

Embodiments of the present application implement the updating of BIOS 211 through the interactive design of OS 212, BIOS 211, and EC 224. During the BIOS update process, BIOS 211 is decoupled from OS 212, allowing OS 212 to remain dormant, while BIOS 211 initiates the update. In the updating process of the BIOS 211, the OS 212 is in the S3 or S4 sleep state, so that the current operating state and files of the OS system can be saved, so that the BIOS is updated while the current system operation is not lost, thereby meeting the requirements of automatic idle update and forced update of the BIOS 211.

An example computing device 500 according to some embodiments of the application is described below in conjunction with fig. 5. In embodiments of the application, the computing device 500 may be or may include the update control system 200 shown in FIG. 2, and in various embodiments, the computing device 500 may have more or fewer components and/or different architectures.

In one embodiment, computing device 500 may include one or more processors 504, system control logic 508 coupled to at least one of processors 504, system memory 512 coupled to system control logic 508, memory 516 (e.g., non-volatile memory (NVM)) coupled to system control logic 508, and network interface 520 coupled to system control logic 508.

Processor 504 may include one or more single-core or multi-core processors. Processor 504 may include any combination of general-purpose and special-purpose processors (e.g., graphics processor, application processor, baseband processor, etc.). In some cases, processor 504 may be configured to perform various operations performed by CPU 222 or EC 224 described above in connection with fig. 2-3.

The system control logic 508 for a certain embodiment may include any suitable interface controller to provide any suitable interface to at least one of the processors 504 and/or any suitable device or component in communication with the system control logic 508. The system control logic 508 for certain embodiments may include one or more memory controllers to provide an interface to the system memory 512. The system memory 512 may be used to load and store data and/or instructions, for example, for the computing device 500, the system memory 512 for an embodiment may include any suitable volatile memory, such as a suitable random-access memory (RAM) or dynamic random-access memory (dynamic random access memory, DRAM).

Memory 516 may include one or more tangible, non-transitory computer-readable media for storing data and/or instructions. For example, memory 516 may include any suitable nonvolatile memory and/or any suitable nonvolatile storage device, such as flash memory, a hard disk drive (HARD DISK DRIVE, HDD), a solid-state drive (solid-STATE DRIVE, SSD), a Compact Disk (CD) drive, and/or a digital versatile disk (DIGITAL VERSATILE DISK, DVD) drive, among others.

Memory 516 may include a portion of a storage resource on the apparatus in which computing device 500 is installed, or it may be accessed by, but not necessarily part of, the device. For example, memory 516 may be accessed over a network via network interface 520.

In particular, system memory 512 and storage 516 may each include: temporary and permanent copies of instruction 524. The instructions 524 may include: instructions that, when executed by at least one of the processors 504, cause the computing device 500 to implement the methods described above. In various embodiments, instructions 524 or hardware, firmware, and/or software components thereof may additionally/alternatively be disposed in system control logic 508, network interface 520, and/or processor 504.

Network interface 520 may include a transceiver to provide a radio interface for computing device 500 to communicate with any other suitable device (e.g., front end module, antenna, etc.) over one or more networks. In various embodiments, network interface 520 may be integrated with other components of computing device 500. For example, the network interface may include a processor of the processors 504, memory of the system memory 512, memory of the memory 516, and/or a firmware device (not shown) having instructions that, when executed by at least one of the processors 504, cause the computing device 500 to implement a method as described in fig. 3.

Network interface 520 may further include any suitable hardware and/or firmware to provide a multiple-input multiple-output radio interface. For example, network interface 520 for a particular embodiment may be a network adapter, a wireless network adapter, a telephone modem, and/or a wireless modem.

For one embodiment, at least one of the processors 504 may be packaged together with logic for one or more controllers of the system control logic 508. For one embodiment, at least one of the processors 504 may be packaged together with logic for one or more controllers of the system control logic 508 to form a System In Package (SiP). For one embodiment, at least one of the processors 504 may be integrated with logic for one or more controllers of the system control logic 508. For one embodiment, at least one of the processors 504 may be integrated with logic for one or more controllers of the system control logic 508 to form a system on a chip (SoC).

Computing device 500 may further include: an input/output (I/O) device 532. The I/O device 532 may include a user interface designed to enable a user to interact with the computing device 500; a peripheral component interface designed to enable peripheral components to also interact with computing device 500; and/or sensors designed to determine environmental conditions and/or location information associated with computing device 500, etc.

Embodiments of the present disclosure may be implemented in hardware, software, firmware, or a combination of these implementations. Embodiments of the application may be implemented as a computer program or program code that is executed on a programmable system that may include at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Program code may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices in a known manner.

Program code in the present application may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. Program code may also be implemented in assembly or machine language, if desired. Indeed, the mechanisms described in the present application are not limited in scope by any particular programming language. In either case, the language may be a compiled or interpreted language.

In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented in the form of instructions or a program loaded onto or stored on one or more transitory or non-transitory machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors, etc. When the instructions or programs are executed by a machine, the machine may perform the various methods described above. For example, the instructions may be distributed over a network or other computer readable medium. Thus, a machine-readable medium may include, but is not limited to, any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), such as a floppy disk, an optical disk, a compact disk read-only memory (CD-ROMs), a magneto-optical disk, a read-only memory (ROM), a Random Access Memory (RAM), an erasable programmable read-only memory (EPROM), an electronically erasable programmable read-only memory (EEPROM), a magnetic or optical card, or a flash memory or a tangible machine-readable memory for transmitting network information via electrical, optical, acoustical or other form of signal (e.g., carrier waves, infrared signals, digital signals, etc.). Thus, a machine-readable medium includes any form of machine-readable medium suitable for storing or transmitting electronic instructions or information readable by a machine (e.g., a computer).

Thus, embodiments of the application also include a non-transitory, tangible machine-readable medium containing instructions or containing design data, such as a Hardware Description Language (HDL), that defines the structures, circuits, devices, processors, and/or system features described herein. These embodiments are also referred to as program products.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various features, these features should not be limited by these terms. These terms are used merely for distinguishing and are not to be construed as indicating or implying relative importance. For example, a first feature may be referred to as a second feature, and similarly a second feature may be referred to as a first feature, without departing from the scope of the example embodiments.

Furthermore, various operations will be described as multiple discrete operations, in a manner that is most helpful in understanding the illustrative embodiments; however, the order of description should not be construed as to imply that these operations are necessarily order dependent, and that many of the operations be performed in parallel, concurrently or with other operations. Furthermore, the order of the operations may also be rearranged. When the described operations are completed, the process may be terminated, but may also have additional operations not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.

References in the specification to "one embodiment," "an illustrative embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature is described in connection with a particular embodiment, it is within the knowledge of one skilled in the art to affect such feature in connection with other embodiments, whether or not such embodiment is explicitly described.

The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise. The phrase "A/B" means "A or B". The phrase "a and/or B" means "(a), (B) or (a and B)".

As used herein, the term "module" may refer to, be part of, or include: a memory (shared, dedicated, or group) for running one or more software or firmware programs, an Application Specific Integrated Circuit (ASIC), an electronic circuit and/or processor (shared, dedicated, or group), a combinational logic circuit, and/or other suitable components that provide the described functionality.

In the drawings, some structural or methodological features may be shown in a particular arrangement and/or order. However, it should be understood that such a particular arrangement and/or ordering is not required. Rather, in some embodiments, these features may be described in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or methodological feature in a particular drawing does not imply that all embodiments need to include such feature, and in some embodiments may not be included or may be combined with other features.

The embodiments of the present application have been described in detail above with reference to the accompanying drawings, but the use of the technical solution of the present application is not limited to the applications mentioned in the embodiments of the present application, and various structures and modifications can be easily implemented with reference to the technical solution of the present application to achieve the various advantageous effects mentioned herein. Various changes, which may be made by those skilled in the art without departing from the spirit of the application, are deemed to be within the scope of the application as defined by the appended claims.

Claims (6)

1. A method for updating a basic input output system of a computing device, comprising:

The operating system of the computing device enters a dormant state, relevant data before the operating system enters the dormant state is stored in a memory or a hard disk, and the operating system of the computing device enters the dormant state and comprises the following steps: the updating program of the basic input/output system sends a dormancy instruction to the operating system, and the operating system enters a dormancy state;

Restarting the basic input and output system after the operating system enters the dormant state, wherein the restarting the basic input and output system after the operating system enters the dormant state comprises the following steps: after the operating system enters a dormant state, the embedded controller of the computing device resets the central processing unit of the computing device to restart the basic input and output system;

the basic input/output system acquires an update file of the basic input/output system, and executes the update of the basic input/output system based on the acquired update file;

After the basic input and output system is updated, the operating system wakes up from the dormant state;

after the basic input/output system finishes updating, the operating system wakes up from the dormant state, which comprises the following steps:

Reading related data before the operating system enters a dormant state from a memory or a hard disk of the computing device;

and returning the operating system to the working state before entering the dormant state based on the acquired related data.

2. The updating method according to claim 1, further comprising:

Before the operating system enters a dormant state, the basic input/output system sets a wake-up flag bit for the embedded controller, wherein the embedded controller resets the central processing unit after acquiring the wake-up flag bit.

3. The updating method according to claim 2, further comprising:

And deleting the wake-up flag bit by the embedded controller after resetting the central processing unit.

4. The updating method according to claim 1, wherein the basic input output system performs the updating of the basic input output system by:

The basic input/output system writes the updated file into a basic input/output system chip of the computing device;

the basic input output system resets the central processing unit of the computing device so as to load the updated file in the basic input output system chip into the memory of the computing device.

5. A readable medium of a computing device, wherein instructions stored thereon, which when executed on a computing device, cause the computing device to perform the method of any of claims 1 to 4.

6. A computing device, comprising: a memory and a controller;

Wherein the memory is to store instructions for execution by one or more controllers of the computing device;

The controller comprising a central processor and an embedded controller for performing the method of any one of claims 1 to 4.