CN113611703B - Method for manufacturing semiconductor structure - Google Patents
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- CN113611703B CN113611703B CN202110463759.3A CN202110463759A CN113611703B CN 113611703 B CN113611703 B CN 113611703B CN 202110463759 A CN202110463759 A CN 202110463759A CN 113611703 B CN113611703 B CN 113611703B
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000002955 isolation Methods 0.000 claims abstract description 92
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000015654 memory Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- Semiconductor Memories (AREA)
- Element Separation (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Semiconductor Lasers (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention discloses a method for manufacturing a semiconductor structure, which comprises the following operations. A substrate extending in a first direction is provided. A trench is formed across the substrate to define a first active region and a second active region. A bottom isolation structure is formed in the trench, wherein the bottom isolation structure exposes a portion of a sidewall of the substrate. The exposed sidewalls of the substrate are oxidized to form a top isolation structure on the bottom isolation structure, wherein the top isolation structure extends into the substrate. A conductive structure is formed embedded in the top isolation structure. A first transistor and a second transistor are formed in the first active region and the second active region, respectively. The method of the present invention can reduce the size of a semiconductor structure having an antifuse structure and a transistor, thereby achieving high device density.
Description
Technical Field
The invention relates to a method for manufacturing a semiconductor structure. More particularly, the present invention relates to a method of fabricating a semiconductor structure having an antifuse structure.
Background
Fuse (fuse) elements are commonly used in semiconductor devices, such as semiconductor memories or logic devices. The antifuse has an electrical characteristic opposite to that of the fuse, and a defective cell can be repaired by replacing the defective cell with a redundant cell.
Typically, an antifuse needs to be controlled by a control gate adjacent thereto. Thus, one memory cell (unit cell) is defined as 1T1C, representing one transistor (gate) and one capacitor (antifuse). However, as the number of antifuses increases, the conventional 1T1C structure will occupy a large area. To achieve high density memory cells or redundancy, the memory cells should be as small as possible.
Disclosure of Invention
An object of the present invention is to provide a method of manufacturing a semiconductor structure, which can reduce the size of a semiconductor structure having an antifuse structure and a transistor, thereby achieving high device density.
According to various embodiments of the present invention, a method of fabricating a semiconductor structure is provided. The method includes providing a substrate extending along a first direction. A trench is formed across the substrate to define a first active region and a second active region. The exposed sidewalls of the substrate are oxidized to form a top isolation structure on the bottom isolation structure, wherein the top isolation structure extends into the substrate. A conductive structure is formed embedded in the top isolation structure. A first transistor and a second transistor are formed in the first active region and the second active region, respectively.
According to some embodiments of the present invention, the source/drain regions of the first transistor and the second transistor respectively have a lower surface located below the lower surface of the conductive structure.
According to some embodiments of the present invention, the top isolation structure and the bottom isolation structure together separate the conductive structure from the source/drain regions of the first transistor and the second transistor.
According to some embodiments of the invention, the width of the trench is greater than the width of the conductive structure.
According to some embodiments of the present invention, forming the first transistor and the second transistor includes forming a gate structure on a substrate of the first active region and the second active region; and forming source/drain regions in the substrate of the first and second active regions, wherein the source/drain regions are located on opposite sides of the top isolation structure.
According to some embodiments of the present invention, the method further comprises forming a plurality of contact plugs connected to the source/drain regions, the gate structures and the conductive structures of the first transistor and the second transistor, respectively.
According to various embodiments of the present invention, a method of fabricating a semiconductor structure is provided. The method includes providing a substrate including a plurality of active regions extending along a first direction, wherein the active regions are separated from each other by a shallow trench isolation structure. A trench is formed across the active region and the shallow trench isolation structure. An antifuse structure is formed in the trench, wherein the antifuse structure includes an isolation structure overlying the trench and a conductive structure embedded in the isolation structure. Transistors are formed in each active region, wherein the transistors are separated from the conductive structures by isolation structures.
According to some embodiments of the present invention, forming the antifuse structure comprises forming a bottom portion of the isolation structure in the trench, wherein a height of the bottom portion of the isolation structure is less than a depth of the trench; forming a top portion of the isolation structure, wherein the top portion extends laterally into the substrate; and forming a conductive structure over the isolation structure.
According to some embodiments of the present invention, forming a transistor includes forming a gate structure on a substrate of each active region; and forming source/drain regions in the substrate of the active region, wherein the source/drain regions are adjacent to the gate structure and have a lower surface below the lower surface of the conductive structure.
According to some embodiments of the present invention, the method includes forming a plurality of contact plugs connected to the source/drain regions, the gate structure, and the conductive structure, respectively.
Compared with the prior art, the method for manufacturing the semiconductor structure has the following beneficial effects: a pair of antifuse structures is formed between two adjacent transistors and can be blown simultaneously. Thus, the method can reduce the size of the semiconductor structure having the antifuse structure and the transistor, thereby achieving high device density.
Drawings
The various aspects of the present invention will become more fully apparent from the following detailed description when taken in conjunction with the accompanying drawings. It is noted that the various features are not drawn to scale in accordance with industry standard practices. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a flow chart of a method of fabricating a semiconductor structure according to some embodiments of the present invention.
Fig. 2-4 are top views illustrating various steps in a process for fabricating a semiconductor structure in accordance with certain embodiments of the present invention.
Fig. 5A, 6A, 7A, 8A, 9A, and 10A are cross-sectional views taken along line A-A' of fig. 4 illustrating various steps of a process for fabricating a semiconductor structure in accordance with certain embodiments of the present invention.
Fig. 5B, 6B, 7B, 8B, 9B, and 10B are cross-sectional views taken along line B-B' of fig. 4 illustrating various steps of a process for fabricating a semiconductor structure in accordance with certain embodiments of the present invention.
Fig. 11 is a cross-sectional view of a semiconductor structure, according to some embodiments of the present invention.
The main reference numerals illustrate:
10-method; 12,14,16,18,20, 22-operations; 100-semiconductor; 102,104, 106-an active region; 102 A-A first active region; 102 b-a second active region; 108-sidewalls; 110-shallow trench isolation structures; 120-masking layer; 200-isolation structures; 200' -isolating layer; 202-a bottom isolation structure; 204-top isolation structure; 210-a conductive structure; 210s,312s,322 s-lower surface; 302 A-A first transistor; 302 b-a second transistor; 310, 320-gate structure; 312, 322-source/drain regions; 400-contact plugs; A-A ', B-B' -segment; AF1, AF 2-antifuse structure; d1—a first direction; d2—a second direction; h1, H1' -depth; h2-height; OP 1-opening; t1-grooves; w1, W2-width.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, such examples are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Spatially relative terms, such as "under," "beneath," "over," "above," and the like, may be used herein for ease of description of the relative relationship between one element or feature and another element or feature as depicted in the figures. The true meaning of these spatially relative terms encompasses other orientations. For example, when the drawing is turned over 180 degrees up and down, the relationship between one element and another element might be changed from "below," below, "to" above, "" over. In addition, spatially relative terms are used herein in the same sense.
Fig. 1 is a flow chart of a method 10 of fabricating a semiconductor structure according to some embodiments of the present invention. The method 10 includes an operation 12, an operation 14, an operation 16, an operation 18, an operation 20, and an operation 22. It should be noted that the method shown in fig. 1 is merely an example and is not intended to limit the present invention. Accordingly, additional operations may be performed before, during, and/or after the method illustrated in fig. 1, and only some other operations are briefly described herein. Fig. 2-4 and 5A-11 are top and cross-sectional views, respectively, of steps of a process for fabricating a semiconductor structure according to method 10 of fig. 1.
Please refer to fig. 1 and 2. In operation 12 of fig. 1, a substrate 100 extending in a first direction D1 is provided. The substrate 100 may include a plurality of active regions 102, 104, and 106 extending along a first direction D1. Adjacent active regions are separated by shallow trench isolation structures 110. For example, as shown in fig. 2, shallow trench isolation structures 110 are located between and separate the active regions 102 and 104. In some embodiments, the substrate 100 may be a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium or the like, a Silicon On Insulator (SOI) substrate, or the like. In some embodiments, the shallow trench isolation structure 110 comprises Tetraethoxysilane (TEOS), silicon oxide, silicon nitride, silicon oxynitride, or fluoride doped silicate (FSG).
Referring to fig. 3, a mask layer 120 is formed on the substrate 100 to cover the active regions 102, 104, 106 and the shallow trench isolation structure 110. In some embodiments, the mask layer 120 is made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other suitable materials, or combinations thereof. The mask layer 120 may be formed on the substrate 100 by a suitable deposition method including a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, or a combination thereof. In some embodiments, the mask layer 120 is patterned and has an opening OP1 to expose the structure thereunder. The mask layer 120 may be patterned by suitable methods, such as using a photolithographic patterning (photolithography patterning) process and an etching process. Accordingly, an opening OP1 is formed in the mask layer 120 to expose portions of the active regions 102, 104, and 106 and the shallow trench isolation structure 110.
Please refer to fig. 1 and fig. 4. In operation 14 of fig. 1, a trench T1 is formed across the substrate 100. In some embodiments, the portions of the active regions 102, 104, 106 and the shallow trench isolation structure 110 exposed by the opening OP1 (shown in fig. 3) are etched to form a trench T1 in the substrate 100. The trench T1 extends in the second direction D2 across the active regions 102, 104 and 106 and the shallow trench isolation structure 110 such that the active regions 102, 104 and 106 are divided into a plurality of segments. For example, the trench T1 spans the active region 102 to define a first active region 102a and a second active region 102b.
Fig. 5A and 5B are sectional views taken along line A-A 'and B-B' of fig. 4, respectively. As shown in fig. 5A, the trench T1 exposes the sidewall 108 of the substrate 100. A portion of the substrate 100 and the shallow trench isolation structure 110 may be etched to form the trench T1 by a suitable etching process. In some embodiments, the depth H1 of the trench T1 in the active region 102 (as shown in fig. 5A) is deeper than the depth H1' in the shallow trench isolation structure 110 (as shown in fig. 5B). In the following operation, a cross-sectional view of the active region 102 and the adjacent shallow trench isolation structure 110 is taken as an example.
Next, in operation 16 of fig. 1, a bottom isolation structure 202 is formed in the trench T1. Fig. 6A-7B illustrate detailed steps of performing operation 16 according to an embodiment of the invention. Fig. 6A, 7A and 6B, 7B are cross-sections taken along line segments A-A 'and B-B' of fig. 4, respectively.
Referring to fig. 6A and 6B, the trench T1 is filled with an insulating material, thereby forming an isolation layer 200'. In some embodiments, isolation layer 200' comprises silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), or fluoride doped silicate (FSG). In some examples, the material of the isolation layer 200' is the same as the material of the shallow trench isolation structure 110. The isolation layer 200' may be formed by a suitable deposition method, including a CVD process, an ALD process, a PVD process, or combinations thereof. In some embodiments, an isolation material may be formed in the trench T1 and cover the top surface of the mask layer 120, and then a planarization process, such as a Chemical Mechanical Polishing (CMP) process, is performed to form the isolation layer 200'.
Referring to fig. 7A and 7B, the isolation layer 200' is recessed to form a bottom isolation structure 202. The recess isolation layer 200' exposes a portion of the sidewalls 108 of the substrate 100 so that it is oxidized in a subsequent step. In some embodiments, the bottom isolation structures 202 are formed using a suitable anisotropic (anisotropic) etching process (e.g., a dry etching process). In some embodiments, the height H2 of the bottom isolation structure 202 is less than the depth H1 of the trench T1 in the substrate 100.
Please refer to fig. 1 and fig. 8A-8B. In operation 18 of fig. 1, exposed sidewalls 108 of the substrate 100 are oxidized to form a top isolation structure 204 on the bottom isolation structure 202, wherein the top isolation structure 204 extends into the substrate 100. In some embodiments, the top isolation structures 204 are formed by performing a thermal oxidation process to oxidize the exposed sidewalls 108 of the substrate 100 (as shown in fig. 7A). As shown in fig. 8A, the top isolation structure 204 extends laterally into the substrate 100. Specifically, the top isolation structure 204 is formed on the bottom isolation structure 202 and has an opening exposing a portion of the top surface of the bottom isolation structure 202. As such, the top isolation structure 204 and the bottom isolation structure 202 together form the isolation structure 200 to cover the sidewalls and bottom of the trench T1.
Please refer to fig. 1 and fig. 9A-9B. In operation 20 of fig. 1, a conductive structure 210 is formed embedded in the isolation structure 200. In some embodiments, conductive structure 210 is formed by suitable deposition methods, including chemical vapor deposition (chemical vapor deposition, CVD) processes, atomic layer deposition (atomic layer deposition, ALD) processes, physical vapor deposition (physical vapor deposition, PVD) processes, or combinations thereof. Conductive structure 210 is disposed on the exposed top surface of bottom isolation structure 202 shown in fig. 8A. Specifically, a bottom portion of the sidewall of the conductive structure 210 is covered by the top isolation structure 204. That is, the top isolation structure 204 separates the conductive structure 210 from the substrate 100. As shown in fig. 9A, the width W2 of the conductive structure 210 is smaller than the width W1 of the trench T1. In some implementations, the conductive structure 210 includes a conductive material (e.g., polysilicon, metal alloy), other suitable materials, and/or combinations thereof.
Referring to fig. 10A and 10B, after forming the conductive structure 210, the mask layer 120 is removed (as shown in fig. 9A and 9B). Specifically, the mask layer 120 is removed by an etching process such as a dry etching process or a wet etching process to expose the top surface of the substrate 100. .
Please refer to fig. 1 and 11. In operation 22 of fig. 1, a first transistor 302a and a second transistor 302 are formed in the first active region 102a and the second active region 102b, respectively. As shown in fig. 11, the first transistor 302a includes a gate structure 310 and source/drain regions 312, and the second transistor 302b includes a gate structure 320 and source/drain regions 322. In some embodiments, the first transistor 302a and the second transistor 302b are formed in a p-well region (not shown) of the substrate 100. Source/drain regions 312 and 322 are located on opposite sides of isolation structure 200, adjacent to gate structures 310 and 320, respectively. The source/drain regions 312 and 322 have lower surfaces 312s and 322s, respectively, below the lower surface 210s of the conductive structure 210 to completely isolate the conductive structure from the p-well region of the substrate 100 to prevent leakage.
The formation of the first transistor 302a may include forming a gate structure 310 on the substrate 100 of the first active region 102a and forming source/drain regions 312 in the substrate 100 of the first active region 102 a. For example, the formation of gate structure 310 may include a suitable deposition method, such as a CVD process, a PVD process, or the like. In some embodiments, the gate structure 310 comprises polysilicon, a metal such as aluminum (Al), copper (Cu), or tungsten (W), other conductive materials, or a combination thereof. In addition, the source/drain regions 312 may be formed by performing an ion implantation (ion implantation) process, and the depth of doping must be deeper than the lower surface 210s of the conductive structure 210. In some embodiments, the source/drain regions 312 are doped with an N-type dopant, such as phosphorus or arsenic. The materials and formation of the gate structure 320 and the source/drain regions 322 of the second transistor 302b may be the same as those of the first transistor 302a described above, and will not be described again. It should be noted that other transistors (not shown) may also be formed in other active regions (e.g., active regions 104, 106) by the processes described above.
In some embodiments, after forming the first transistor 302a and the second transistor 302b, the method further includes forming a plurality of contact plugs connected to the source/drain regions 312, 322 and the gate structures 310, 320 of the first and second transistors 302a, 302b, respectively, and the conductive structure 210. For example, the contact plug 400 is grounded and connected to the source/drain regions 312 and 322, respectively, remote from the isolation structure 200.
With continued reference to fig. 11, isolation structure 200 separates conductive structure 210 from source/drain regions 312 and 322 of first transistor 302a and second transistor 302 b. A pair of antifuse structures AF1 and AF2 are formed between transistors 302a and 302 b. The conductive structure 210 acts as a top plate for the antifuse structures AF1 and AF 2. The source/drain regions 312 and 322 serve as the bottom plates (bottom plates) for the antifuse structures AF1 and AF 2. Isolation structure 200, and more particularly top isolation structure 204, acts as a dielectric layer between the top and bottom plates of antifuse structures AF1 and AF 2. Specifically, antifuse structure AF1 includes conductive structure 210, isolation structure 200, and source/drain regions 312 that are shared with transistor 302 a. Similarly, antifuse structure AF2 includes conductive structure 210, isolation structure 200, and source/drain regions 322 that are shared with transistor 302 b. A voltage may be applied across antifuses AF1 and AF2 (i.e., source/drain regions 312, 322 and conductive structure 210) to cause breakdown (break down) of the dielectric layer, which results in rupture (rupture) of the dielectric layer.
As described above, according to an embodiment of the present invention, a method of manufacturing a semiconductor structure is provided. In the fabrication of the semiconductor structure of the present invention, the isolation structure separates the substrate into a plurality of active regions. Conductive structures are then embedded from the top surface of the isolation structures and transistors are formed in the active regions on opposite sides of the isolation structures. Thus, a pair of antifuse structures is formed between two adjacent transistors, and can be blown (blown out) simultaneously. In other words, the method of the present invention can reduce the size of the semiconductor structure having the antifuse structure and the transistor, thereby achieving high device density.
While the present invention has been described with reference to the embodiments, it should be understood that the invention is not limited thereto, but may be modified and altered in various ways without departing from the spirit and scope of the present invention.
Claims (9)
1. A method of fabricating a semiconductor structure, comprising:
Providing a substrate extending along a first direction;
Forming a trench across the substrate to define a first active region and a second active region, wherein the trench has a width;
forming a bottom isolation structure in the trench, wherein the bottom isolation structure exposes a portion of a sidewall of the substrate;
Oxidizing the sidewalls of the substrate exposure to form a top isolation structure on the bottom isolation structure, wherein the top isolation structure extends into the substrate;
Forming a conductive structure embedded in the top isolation structure, wherein the conductive structure has a width less than the width of the trench; and
And forming a first transistor and a second transistor in the first active region and the second active region respectively.
2. The method of claim 1, wherein source/drain regions of the first transistor and the second transistor each have a lower surface below a lower surface of the conductive structure.
3. The method of claim 2, wherein the top isolation structure and the bottom isolation structure together separate the conductive structure from the source/drain regions of the first transistor and the second transistor.
4. The method of claim 1, wherein forming the first transistor and the second transistor comprises:
forming a gate structure on the substrate of the first active region and the second active region; and
Source/drain regions are formed in the substrate of the first and second active regions, wherein the source/drain regions are located on opposite sides of the top isolation structure.
5. The method of claim 4, further comprising forming a plurality of contact plugs connected to the source/drain regions, the gate structure, and the conductive structure of the first transistor and the second transistor, respectively.
6. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a plurality of active regions extending along a first direction, and the plurality of active regions are separated from each other by a shallow trench isolation structure;
Forming a trench across the plurality of active regions and the shallow trench isolation structure, wherein the trench has a width;
Forming an antifuse structure in the trench, wherein the antifuse structure includes an isolation structure covering the trench and a conductive structure embedded in the isolation structure, wherein the conductive structure has a width less than the width of the trench; and
A transistor is formed in each active region, wherein the transistor is separated from the conductive structure by the isolation structure.
7. The method of claim 6, wherein forming the antifuse structure comprises:
forming a bottom portion of the isolation structure in the trench, wherein the bottom portion of the isolation structure has a height less than a depth of the trench;
forming a top portion of the isolation structure, wherein the top portion extends laterally into the substrate; and
The conductive structure is formed on the isolation structure.
8. The method of claim 6, wherein forming the transistor comprises:
forming a gate structure on the substrate of each active region; and
Source/drain regions are formed in the substrate of each of the active regions, wherein the source/drain regions are adjacent to the gate structure and have a lower surface below a lower surface of the conductive structure.
9. The method of claim 8, further comprising forming a plurality of contact plugs connected to the source/drain regions, the gate structure, and the conductive structure, respectively.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/865,429 US11315918B2 (en) | 2020-05-04 | 2020-05-04 | Semiconductor structure and semiconductor layout structure |
| US16/865,428 | 2020-05-04 | ||
| US16/865,429 | 2020-05-04 | ||
| US16/865,428 US11107730B1 (en) | 2020-05-04 | 2020-05-04 | Method of manufacturing semiconductor device with anti-fuse structures |
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| Publication Number | Publication Date |
|---|---|
| CN113611703A CN113611703A (en) | 2021-11-05 |
| CN113611703B true CN113611703B (en) | 2024-07-26 |
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| CN202110463759.3A Active CN113611703B (en) | 2020-05-04 | 2021-04-28 | Method for manufacturing semiconductor structure |
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| CN113611684A (en) | 2021-11-05 |
| TW202143396A (en) | 2021-11-16 |
| TWI749953B (en) | 2021-12-11 |
| CN113611703A (en) | 2021-11-05 |
| TWI779462B (en) | 2022-10-01 |
| TW202143495A (en) | 2021-11-16 |
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