CN113555228B - Nano forest based MEMS super capacitor and preparation method thereof - Google Patents
Nano forest based MEMS super capacitor and preparation method thereof Download PDFInfo
- Publication number
- CN113555228B CN113555228B CN202110825193.4A CN202110825193A CN113555228B CN 113555228 B CN113555228 B CN 113555228B CN 202110825193 A CN202110825193 A CN 202110825193A CN 113555228 B CN113555228 B CN 113555228B
- Authority
- CN
- China
- Prior art keywords
- layer
- capacitor
- upper electrode
- substrate
- nano
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 324
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 211
- 238000000034 method Methods 0.000 claims abstract description 39
- 239000010410 layer Substances 0.000 claims description 348
- 238000002161 passivation Methods 0.000 claims description 136
- 238000005530 etching Methods 0.000 claims description 27
- 239000011241 protective layer Substances 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 12
- 230000000873 masking effect Effects 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000011049 filling Methods 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 18
- 239000000463 material Substances 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 230000003044 adaptive effect Effects 0.000 description 6
- 238000004146 energy storage Methods 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- 239000002061 nanopillar Substances 0.000 description 3
- 239000002073 nanorod Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003985 ceramic capacitor Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 1
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- YTAHJIFKAKIKAV-XNMGPUDCSA-N [(1R)-3-morpholin-4-yl-1-phenylpropyl] N-[(3S)-2-oxo-5-phenyl-1,3-dihydro-1,4-benzodiazepin-3-yl]carbamate Chemical compound O=C1[C@H](N=C(C2=C(N1)C=CC=C2)C1=CC=CC=C1)NC(O[C@H](CCN1CCOCC1)C1=CC=CC=C1)=O YTAHJIFKAKIKAV-XNMGPUDCSA-N 0.000 description 1
- -1 aluminum-silicon-copper Chemical compound 0.000 description 1
- 229910021418 black silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
- H01G11/22—Electrodes
- H01G11/30—Electrodes characterised by their material
- H01G11/32—Carbon-based
- H01G11/36—Nanostructures, e.g. nanofibres, nanotubes or fullerenes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
- H01G11/84—Processes for the manufacture of hybrid or EDL capacitors, or components thereof
- H01G11/86—Processes for the manufacture of hybrid or EDL capacitors, or components thereof specially adapted for electrodes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/13—Energy storage using capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Crystallography & Structural Chemistry (AREA)
- Nanotechnology (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a nano forest based MEMS super capacitor and a preparation method thereof. According to the technical scheme provided by the invention, the nano forest based MEMS super capacitor comprises a capacitor substrate, a nano forest structure matched with the capacitor substrate and a capacitor unit body matched and connected with the nano forest structure, wherein the capacitor unit body comprises a lower electrode layer, a capacitor dielectric layer and an upper electrode layer which are sequentially deposited and arranged in the nano forest structure, and the upper electrode layer and the lower electrode layer are insulated and isolated through the capacitor dielectric layer; the lower electrode layer is in ohmic contact with the capacitor substrate, and the lower electrode of the MEMS capacitor can be obtained through the matching of the lower electrode layer and the capacitor substrate; the upper electrode of the MEMS capacitor can be formed by the upper electrode layer and an upper electrode lead-out unit electrically connected to the upper electrode layer. The invention is compatible with the existing process, and the prepared capacitor has large capacity-volume ratio, high capacitance density and low cost.
Description
Technical Field
The invention relates to an MEMS super capacitor and a preparation method thereof, in particular to an MEMS super capacitor based on a nano forest and a preparation method thereof.
Background
At present, in the field of energy storage of MEMS, common micro capacitors include ceramic capacitors, organic thin film dielectric capacitors, tantalum electrolytic capacitors, aluminum electrolytic capacitors, and the like. With the wider application field of micro energy sources, more rigorous requirements on the severe environment of energy storage devices are provided. The energy storage device faces the technical bottleneck problems of poor environmental adaptability, small capacity-volume ratio and the like, and the conventional ceramic capacitor has weaker capability of bearing transient high-voltage pulse and is easy to break down by pulse voltage; the organic film dielectric capacitor has small capacitance, larger loss and poor high temperature resistance; the aluminum electrolytic capacitor is sensitive to the requirements of temperature and use frequency, large in capacity error and large in leakage current. Therefore, in a micro energy system, the characteristics of miniaturization, high reliability, high performance and the like of the MEMS capacitor become key core characteristics of the energy storage device in the 21 st century.
The technical difficulty of the MEMS capacitor is how to prepare a structure with a high specific surface area on a substrate to realize a large volume ratio of the capacitor. At present, when an MEMS capacitor is manufactured, a method generally used is a deep silicon etching technique using silicon dioxide as a mask, and the deep silicon etching technique is to etch a silicon pillar on the surface of a silicon wafer using silicon oxide as a mask as a lower electrode of the capacitor. However, the preparation process has the following problems: 1) the equipment cost is high and the equipment is single; 2) the phenomena of black silicon and etching load effect are easy to occur; 3) the de-masking process is complex and the silicon dioxide removal affects performance.
In summary, under the condition of ensuring the cost, how to prepare the MEMS capacitor with large volume ratio is a difficult problem to be solved urgently at present.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a nano forest based MEMS super capacitor and a preparation method thereof, wherein the nano forest based MEMS super capacitor is compatible with the prior art, the prepared capacitor has large capacity-volume ratio and higher capacitance density, the cost is reduced, and the performance of the MEMS capacitor can be ensured.
According to the technical scheme provided by the invention, the nano forest based MEMS super capacitor comprises a capacitor substrate, a nano forest structure adaptive to the capacitor substrate and a capacitor unit body adaptive to the nano forest structure, wherein the capacitor unit body comprises a lower electrode layer, a capacitor dielectric layer and an upper electrode layer which are deposited in sequence and cover the nano forest structure, and the upper electrode layer and the lower electrode layer are insulated and isolated through the capacitor dielectric layer; the lower electrode layer is in ohmic contact with the capacitor substrate, and the lower electrode of the MEMS capacitor can be obtained through the matching of the lower electrode layer and the capacitor substrate; the upper electrode of the MEMS capacitor can be formed by the upper electrode layer and the upper electrode drawing unit electrically connected to the upper electrode layer.
The nano forest structure can be prepared in the capacitor substrate or supported on the capacitor substrate; when the nano forest structure is prepared in the capacitor substrate, the height of the nano columns in the nano forest structure is not more than the thickness of the capacitor substrate.
The capacitor comprises a capacitor substrate and is characterized by further comprising a lower electrode leading-out unit which is in adaptive connection with the capacitor substrate, wherein the lower electrode leading-out unit and the upper electrode leading-out unit are located on the same side of the capacitor substrate or located on two corresponding sides of the capacitor substrate respectively.
The upper electrode lead-out unit comprises an electrode lead-out insulating layer arranged on the upper electrode layer and a capacitor interconnection layer positioned above the electrode lead-out insulating layer, and the capacitor interconnection layer can be electrically connected with the upper electrode layer through an upper electrode lead-out connector in the electrode lead-out insulating layer.
A preparation method of an MEMS super capacitor based on a nano forest comprises the following steps:
and 3, preparing an upper electrode leading-out unit on the capacitor unit body, wherein the upper electrode leading-out unit covers the upper electrode layer, and the upper electrode leading-out unit is electrically connected with the upper electrode layer so as to form an upper electrode of the capacitor.
The method comprises the following steps:
step 1.1, providing a nano forest carrier substrate for forming a capacitance substrate, and arranging a carrier substrate mask layer on the nano forest carrier substrate;
step 1.2, etching the carrier substrate mask layer to form a required substrate mask layer nanometer forest by utilizing the carrier substrate mask layer;
step 1.3, etching the nano forest carrier substrate by using the substrate mask layer nano forest as a mask to obtain a carrier substrate inner nano forest in the nano forest carrier substrate;
and 1.4, removing the nano forest of the mask layer of the substrate so as to form a required nano forest structure by using the nano forest in the carrier substrate.
The method comprises the following steps:
step a, providing a nano forest support substrate for forming a capacitance substrate, and arranging a support substrate mask layer on the nano forest support substrate;
and b, etching the support substrate mask layer so as to form a required mask layer body nano forest by using the carrier substrate mask layer, wherein the height of a mask layer body nano column in the mask layer body nano forest is consistent with the thickness of the support substrate mask layer so as to form a required nano forest structure by using the mask layer body nano forest.
The deposition process used to prepare the lower electrode layer, the capacitor dielectric layer and the upper electrode layer includes atomic layer deposition.
In step 3, the specific process for preparing the upper electrode leading-out unit comprises the following steps:
3.1, depositing a first passivation protection layer of the capacitor unit, wherein the first passivation protection layer of the capacitor unit covers the upper electrode layer;
step 3.2, selectively masking and etching the first passivation protection layer of the capacitor unit to obtain a first passivation protection connecting hole of the capacitor unit, which penetrates through the first passivation protection layer of the capacitor unit, and exposing an upper electrode layer which is just corresponding to the first passivation protection connecting hole of the capacitor unit through the first passivation protection connecting hole of the capacitor unit;
step 3.3, filling an upper electrode first lead-out connector in the first passivation protection connecting hole of the capacitor unit, wherein the upper electrode first lead-out connector is electrically connected with the upper electrode layer;
step 3.4, arranging a second passivation protection layer of the capacitor unit on the first passivation protection layer of the capacitor unit;
step 3.5, selectively masking and etching the second passivation protection layer of the capacitor unit to obtain a second passivation protection connecting hole of the capacitor unit, which penetrates through the second passivation protection layer of the capacitor unit, wherein the second passivation protection connecting hole of the capacitor unit corresponds to the first leading-out connecting body of the upper electrode so as to expose the first leading-out connecting body of the upper electrode through the second passivation protection connecting hole of the capacitor unit;
and 3.6, depositing an upper electrode leading-out connecting layer on the second passivation protective layer of the capacitor unit, wherein the upper electrode leading-out connecting layer covers the second passivation protective layer of the capacitor unit and can be filled in the second passivation protective connecting hole of the capacitor unit, the upper electrode leading-out connecting layer can be contacted with the upper electrode first leading-out connecting body, and the upper electrode leading-out connecting layer can be electrically connected with the upper electrode through the upper electrode first leading-out connecting body.
The capacitor comprises a capacitor substrate and is characterized by further comprising a lower electrode leading-out unit electrically connected with the capacitor substrate, wherein the lower electrode leading-out unit and the upper electrode leading-out unit are located on the same side of the capacitor substrate or located on two corresponding sides of the capacitor substrate respectively.
The invention has the advantages that: the nano forest structure can be prepared through an MEMS process, the nano forest structure is matched with the capacitor substrate, and the required capacitor unit bodies are prepared by utilizing the nano forest structure, namely the capacitor unit bodies correspond to the nano forest structure, so that the prepared capacitor unit bodies have the characteristics of a nano forest, namely the prepared capacitor has a large capacity-volume ratio, the performance of the MEMS capacitor is ensured, and the MEMS capacitor is compatible with the existing process and low in cost.
Drawings
FIGS. 1 to 14 are schematic views of the detailed steps of embodiment 1 of the present invention, wherein
Figure 1 is a schematic representation of a nano forest carrier substrate of the present invention.
Fig. 2 is a schematic diagram of the carrier substrate mask layer obtained according to the present invention.
FIG. 3 is a schematic diagram of a substrate mask layer nano forest obtained by the present invention.
FIG. 4 is a schematic representation of the invention after obtaining a nano forest within the carrier substrate.
FIG. 5 is a schematic diagram of the present invention after removing the nano forest of the substrate mask layer.
FIG. 6 is a schematic diagram of the bottom electrode layer according to the present invention.
FIG. 7 is a schematic diagram of a capacitor dielectric layer obtained according to the present invention.
Fig. 8 is a schematic diagram of the present invention after obtaining the upper electrode layer.
Fig. 9 is a schematic diagram of the capacitor unit after obtaining the first passivation layer.
Fig. 10 is a schematic diagram of the capacitor unit after a first passivation protection connection hole is obtained.
FIG. 11 is a schematic view of the present invention after obtaining a first lead connector for an upper electrode.
Fig. 12 is a schematic diagram of the capacitor unit after obtaining the second passivation layer.
Fig. 13 is a schematic diagram of the capacitor unit after a second passivation protection connection hole is obtained.
FIG. 14 is a schematic view of the present invention after an upper electrode lead-out connection layer is obtained.
FIGS. 15 to 16 are schematic views showing the steps of embodiment 2 of the present invention, wherein
Fig. 15 is a schematic diagram of the capacitor unit after obtaining the first passivation protection connection hole and the second passivation protection connection hole of the capacitor unit according to the invention.
Fig. 16 is a schematic view of the first upper electrode lead-out connector and the lower electrode lead-out connector according to the present invention.
FIGS. 17 to 27 are schematic views of the detailed steps of embodiment 3 of the present invention, wherein
Fig. 17 is a schematic view of a forest support substrate and a mask layer of the support substrate according to the present invention.
FIG. 18 is a schematic view of the mask layer body nano forest obtained by using the supporting substrate mask layer according to the present invention.
FIG. 19 is a schematic view of the invention after obtaining the bottom electrode layer.
FIG. 20 is a schematic diagram of a capacitor dielectric layer obtained according to the present invention.
Fig. 21 is a schematic diagram of the invention after obtaining the upper electrode layer.
Fig. 22 is a schematic diagram of the capacitor unit after obtaining the first passivation layer according to the present invention.
Fig. 23 is a schematic diagram of the capacitor unit after a first passivation protection connection hole is obtained.
FIG. 24 is a schematic view of the present invention after obtaining a first lead connector for an upper electrode.
Fig. 25 is a schematic diagram of a capacitor unit after a second passivation layer is obtained.
Fig. 26 is a schematic diagram of the capacitor unit after a second passivation protection connection hole is obtained.
FIG. 27 is a schematic view of the present invention after an upper electrode lead-out connection layer is obtained.
Description of reference numerals: 1-nano forest carrier substrate, 2-carrier substrate mask layer, 3-substrate mask layer nano forest, 4-carrier substrate inner nano column, 5-carrier substrate inner nano column groove, 6-lower electrode layer, 7-capacitor dielectric layer, 8-upper electrode layer, 9-capacitor unit first passivation protection layer, 10-capacitor unit first passivation protection connection hole, 11-upper electrode first leading-out connector, 12-capacitor unit second passivation protection layer, 13-capacitor unit second passivation protection connection hole, 14-capacitor interconnection layer, 15-nano forest support substrate, 16-support substrate mask layer, 17-mask layer body nano column, 18-mask layer body nano column groove, 19-capacitor unit second passivation protection connection hole, 3-substrate mask layer nano forest, 20-lower electrode lead-out connector.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
In order to enable the capacitor to have a large capacity-volume ratio and ensure the performance of the capacitor, the capacitor comprises a capacitor substrate, a nano forest structure adaptive to the capacitor substrate and a capacitor unit body adaptive to the nano forest structure, wherein the capacitor unit body comprises a lower electrode layer 6, a capacitor dielectric layer 7 and an upper electrode layer 8 which are deposited and cover the nano forest structure in sequence, and the upper electrode layer 6 and the lower electrode layer 8 are isolated in an insulating way through the capacitor dielectric layer 7; the lower electrode layer 6 is in ohmic contact with the capacitor substrate, and the lower electrode of the MEMS capacitor can be obtained through the matching of the lower electrode layer 6 and the capacitor substrate; the upper electrode of the MEMS capacitor can be formed by the upper electrode layer 8 and an upper electrode lead-out unit electrically connected to the upper electrode layer 8.
Specifically, the capacitor substrate may be made of a conventional semiconductor material, such as a silicon substrate, and when the silicon substrate is adopted, the silicon substrate is preferably made of low-resistance silicon or heavily-doped silicon, and the specific material type may be selected according to actual needs, which is not described herein again. The nano forest structure is matched with the capacitor substrate, and specifically, the nano forest structure can be prepared in the capacitor substrate or supported on the capacitor substrate. When the nano forest structure is prepared in the capacitor substrate, the height of the nano columns in the nano forest structure is not larger than the thickness of the capacitor substrate, namely the nano forest structure and the capacitor substrate are integrated, and after the nano forest structure and the capacitor substrate are connected into a whole, the strength of the nano forest structure is improved, the subsequent process is convenient to implement, and certainly, the ohmic contact between the lower electrode layer 6 and the capacitor substrate can be facilitated.
In the embodiment of the invention, the capacitor unit bodies are matched with the nano forest structure, namely the shape of the capacitor unit bodies is consistent with the nano forest structure. Specifically, the lower electrode layer 6, the capacitance dielectric layer 7 and the upper electrode layer 8 are sequentially deposited in the nano forest structure area, and the capacitance unit body can be formed by matching the lower electrode layer 6, the capacitance dielectric layer 7 and the upper electrode layer 8. The lower electrode layer 6 covers the nano forest structure, the capacitor dielectric layer 7 covers the lower electrode layer 6, and the upper electrode layer 8 covers the capacitor dielectric layer 7. In specific implementation, the lower electrode layer 6 is in ohmic contact with the capacitor substrate, so that the lower electrode layer 6 can be led out through the capacitor substrate, so as to form a lower electrode of the MEMS capacitor. An upper electrode lead-out unit is arranged above the capacitor unit body, and the upper electrode lead-out unit can be electrically connected with the upper electrode layer 8, namely the upper electrode layer 8 can be led out through the upper electrode lead-out unit so as to form an upper electrode of the MEMS capacitor. The MEMS capacitor is formed by the lower electrode, the upper electrode and the capacitor dielectric layer, the form of the MEMS capacitor formed in a matched mode is consistent with the structure of the existing capacitor, and the prepared MEMS capacitor has a large volume ratio of large capacity due to the fact that the nano forest structure has a large surface ratio when the capacitor unit body is matched with the nano forest structure.
The capacitor further comprises a lower electrode leading-out unit which is in adaptive connection with the capacitor substrate, wherein the lower electrode leading-out unit and the upper electrode leading-out unit are positioned on the same side of the capacitor substrate or respectively positioned on two corresponding sides of the capacitor substrate.
In the embodiment of the invention, the lower electrode layer 6 is in ohmic contact with the capacitor substrate, and at the moment, the lower electrode layer 6 can be directly led out through the capacitor substrate. Of course, when other lead-out forms are needed, the lower electrode layer 6 can be led out through the lower electrode lead-out unit, and the lower electrode lead-out unit is in ohmic contact with the capacitor substrate, so that the lower electrode layer 6 is electrically connected. In specific implementation, the lower electrode leading-out unit and the upper electrode leading-out unit are located on the same side of the capacitor substrate, or are respectively located on two sides corresponding to the capacitor substrate, and the specific position relationship between the lower electrode leading-out unit and the upper electrode leading-out unit can be selected according to actual needs, which is not described herein again.
Further, the upper electrode lead-out unit includes an electrode lead-out insulating layer disposed on the upper electrode layer 8 and a capacitance interconnection layer 14 located above the electrode lead-out insulating layer, and the capacitance interconnection layer 14 can be electrically connected to the upper electrode layer 8 through an upper electrode lead-out connector in the electrode lead-out insulating layer.
In the embodiment of the invention, the electrode lead-out insulating layer is arranged on the upper electrode layer 8, the capacitor interconnection layer 14 is arranged on the electrode lead-out insulating layer, the electrode lead-out insulating layer can be used for realizing protection and insulation isolation of the upper electrode layer 8, the capacitor interconnection layer 14 can be electrically connected with the upper electrode layer 8, namely the upper electrode layer 8 can be led out through the capacitor interconnection layer 14, so that the upper electrode of the MEMS capacitor can be conveniently formed, and the capacitor interconnection layer 14 can be conveniently connected with an external circuit. The specific structure and the manufacturing process of the upper electrode lead-out unit can be specifically described by the following description of the specific manufacturing process, which is not repeated herein.
Certainly, in specific implementation, a plurality of nano forest structures can exist, and after the capacitor unit bodies are arranged on each nano forest structure, a plurality of MEMS capacitors can be formed. When a plurality of MEMS capacitors are formed, all the MEMS capacitors can be connected into a whole by utilizing the capacitor interconnection layer 14, namely, the plurality of MEMS capacitors are connected in parallel, and the capacitance sensors with different capacitance values can be realized by controlling the capacitance value of a single MEMS capacitor.
In summary, the MEMS super capacitor based on the nano forest may be prepared by the following process steps, and specifically, the preparation method of the MEMS super capacitor includes the following steps:
specifically, the capacitor substrate is generally a commonly used semiconductor material, and a specifically prepared nano forest structure and the matching between the nano forest structure and the capacitor substrate are described by the following specific examples.
specifically, the process of preparing the capacitor unit body and covering the nano forest structure, etc. is specifically described by the following process.
And 3, preparing an upper electrode leading-out unit on the capacitor unit body, wherein the upper electrode leading-out unit covers the upper electrode layer 8, and the upper electrode leading-out unit is electrically connected with the upper electrode layer 8 so as to form an upper electrode of the capacitor.
In step 3, the specific process for preparing the upper electrode lead-out unit comprises the following steps:
step 3.1, depositing a first passivation protection layer 9 of the capacitor unit, wherein the first passivation protection layer 9 of the capacitor unit covers the upper electrode layer 8;
step 3.2, selectively masking and etching the first passivation layer 9 of the capacitor unit to obtain a first passivation protection connection hole 10 of the capacitor unit, which penetrates through the first passivation layer 9 of the capacitor unit, and exposing the upper electrode layer 8, which corresponds to the first passivation protection connection hole 10 of the capacitor unit, through the first passivation protection connection hole 10 of the capacitor unit;
step 3.3, filling an upper electrode first leading-out connector 11 in the first passivation protection connecting hole 10 of the capacitor unit, wherein the upper electrode first leading-out connector 11 is electrically connected with the upper electrode layer 8;
step 3.4, arranging a second passivation protective layer 12 of the capacitor unit on the first passivation protective layer 9 of the capacitor unit;
step 3.5, selectively masking and etching the capacitor unit second passivation protection layer 12 to obtain a capacitor unit second passivation protection connection hole 13 penetrating through the capacitor unit second passivation protection layer 12, wherein the capacitor unit second passivation protection connection hole 13 corresponds to the upper electrode first leading-out connection body 11 so as to expose the upper electrode first leading-out connection body 11 through the capacitor unit second passivation protection connection hole 13;
and 3.6, depositing an upper electrode lead-out connecting layer 14 on the second passivation protective layer 12 of the capacitor unit, wherein the upper electrode lead-out connecting layer 14 covers the second passivation protective layer 12 of the capacitor unit and can be filled in the second passivation protective connecting hole 13 of the capacitor unit, the upper electrode lead-out connecting layer 14 can be in contact with the upper electrode first lead-out connecting body 11, and the upper electrode lead-out connecting layer 14 can be electrically connected with the upper electrode layer 8 through the upper electrode first lead-out connecting body 11.
Specifically, the capacitor unit first passivation protection layer 9 and the capacitor unit second passivation protection layer 12 can form an electrode leading-out insulation layer, and the electrode first leading-out connector 11 and the part of the upper electrode leading-out connection layer 14 filled in the capacitor unit second passivation protection connection hole 13 can form an upper electrode leading-out connector. The specific structure and the specific manufacturing process of the upper electrode lead-out unit can be specifically described in detail by the following specific examples.
Example 1
As shown in fig. 1 to 14, the specific preparation method comprises the following steps:
step 1-1, providing a nano forest carrier substrate 1 for forming a capacitance substrate, and arranging a carrier substrate mask layer 2 on the nano forest carrier substrate 1;
specifically, the nano forest carrier substrate 1 may be silicon, the carrier substrate mask layer 2 may be PI (polyimide), and the carrier substrate mask layer 2 may be disposed on the front surface of the nano forest carrier substrate 1 by spin coating or the like, as shown in fig. 1 and 2. The thickness of the carrier substrate mask layer 2 may be generally 5 μm to 10 μm, and the process of spin coating the front surface of the nano forest carrier substrate 1 is the same as the prior art, and is known to those skilled in the art, and is not described herein again.
Step 1-2, etching the carrier substrate mask layer 2 to form a required substrate mask layer nanometer forest 3 by utilizing the carrier substrate mask layer 2;
specifically, the carrier substrate mask layer 2 is etched by a common technical means in the technical field, and the substrate mask layer nanometer forest 3 can be obtained after etching, as shown in fig. 3. And etching the carrier substrate mask layer 2 to form a substrate mask layer nano forest 3 with the height of 3-7 μm and the width of 100-500 nm, wherein the height of the nano columns in the substrate mask layer nano forest 3 is less than the thickness of the carrier substrate mask layer 2, namely, the corresponding front surface of the nano forest carrier substrate 1 can be exposed through the gaps among the nano columns in the substrate mask layer nano forest 3, so that the nano forest carrier substrate 1 can be etched in the subsequent process.
Step 1-3, etching the nano forest carrier substrate 1 by using the substrate mask layer nano forest 3 as a mask to obtain a carrier substrate inner nano forest in the nano forest carrier substrate 1;
specifically, the nano forest carrier substrate 1 is etched by using the substrate mask layer nano forest 3 as a mask, so that the carrier substrate nano forest can be prepared in the nano forest carrier substrate 1, as shown in fig. 4. The carrier substrate nano forest is in positive correspondence with the substrate mask layer nano forest 3, the carrier substrate nano forest comprises carrier substrate inner nano columns 4 and carrier substrate inner nano column grooves 5, the carrier substrate inner nano columns 4 can be in positive correspondence with the substrate mask layer nano forest 3 inner nano columns, and the carrier substrate inner nano column grooves 5 are in positive correspondence with gaps among the base mask layer nano forest 3 inner nano columns. The height of the nano-columns 4 in the carrier substrate is smaller than the thickness of the nano-forest carrier substrate 1, that is, the nano-forest carrier substrate 1 which is not etched can be used for supporting the nano-columns 4 in the carrier substrate, and the specific process and process conditions for etching the nano-forest carrier substrate 1 by using the substrate mask layer nano-forest 3 as a mask to obtain the nano-forest in the carrier substrate can be consistent with those of the prior art, and are particularly well known by those skilled in the art, and are not described herein again. Typically, the height of the nanopillars 4 within the carrier substrate is 5 μm-50 μm.
And 1-4, removing the substrate mask layer nanometer forest 3 to form a required nanometer forest structure by utilizing the nanometer forest in the carrier substrate.
Specifically, the substrate mask layer nano forest 3 is removed by a commonly used technical means in the technical field, and after the substrate mask layer nano forest 3 is removed, the nano forest in the carrier substrate is used for forming a required nano forest structure, as shown in fig. 5.
In specific implementation, the purpose of the step 1 can be realized through the corresponding process from the step 1-1 to the step 1-4, namely the nano forest structure is prepared on the capacitor substrate.
And 1-5, depositing a lower electrode layer material to obtain a lower electrode layer 6, wherein the lower electrode layer 6 can be made of titanium nitride, silver, titanium and/or tungsten, and the thickness of the lower electrode layer 6 can be 10 nm-20 nm generally. The lower electrode layer 6 can be supported on the nano forest carrier substrate 1 and covers the nano forest in the carrier substrate; the lower electrode layer 6 covering the nano forest carrier substrate 1 is positioned on the outer ring of the nano forest in the carrier substrate, and the lower electrode layer 6 can cover the nano column 4 in the carrier substrate and is filled in the nano column groove 5 in the carrier substrate, as shown in fig. 6. The lower electrode layer 6 is in ohmic contact with the nano forest carrier substrate 1, namely, the ohmic contact between the lower electrode layer 6 and the capacitor substrate can be realized.
Step 1-6, depositing a capacitance dielectric material to obtain a capacitance dielectric layer 7, wherein the capacitance dielectric layer 7 covers the lower electrode layer 6, as shown in fig. 7. The capacitor dielectric layer 7 may be made of aluminum oxide or other common capacitor dielectric materials, or may be made of high-K materials, such as hafnium oxide and titanium oxide, and the specific material type may be selected according to the requirement. The thickness of the capacitor dielectric layer 7 can be generally 5nm to 20 nm.
Step 1-7, depositing the upper electrode layer material to obtain an upper electrode layer 8, wherein the upper electrode layer 8 covers the capacitor dielectric layer 7, as shown in fig. 8, the material of the upper electrode layer 8 may specifically be titanium nitride, and the thickness of the upper electrode layer 8 is 20nm to 50 nm. The distribution state of the upper electrode layer 8 and the capacitance dielectric layer 7 in the nano forest carrier substrate 1 and the nano forest in the carrier substrate is consistent with the specific distribution state of the lower electrode layer 6.
Specifically, the purpose of step 2 can be achieved through the corresponding process from step 1-5 to step 1-8, that is, the capacitor unit body is prepared, and generally, the thickness of the capacitor unit body is smaller than the groove width of the nanorod grooves 5 in the carrier substrate. In the above steps 1-5 to 1-8, the specific deposition process may be Atomic Layer Deposition (ALD), and the specific process and process conditions of the atomic layer deposition may be selected according to actual needs, which are known to those skilled in the art, and are not described herein again.
Step 1-8, depositing a passivation protection layer material to obtain a first passivation protection layer 9 of the capacitor unit, where the first passivation protection layer 9 of the capacitor unit may be made of a conventional passivation protection material, such as silicon dioxide, and may be specifically selected as needed, and details are not described here. The capacitor unit first passivation layer 9 covers the upper electrode layer, and when the thickness of the capacitor unit body is smaller than the width of the nanorod groove 5 in the carrier substrate, the capacitor unit first passivation layer 9 is also filled in the nanorod groove 5 in the carrier substrate, as shown in fig. 9. The thickness of the first passivation layer 9 of the capacitor unit may be greater than that of the capacitor unit body, and the thickness of the first passivation layer 9 of the capacitor unit may be 50nm to 200 nm.
Step 1-9, selectively masking and etching the first passivation protection layer 9 of the capacitor unit to obtain a first passivation protection connection hole 10 of the capacitor unit penetrating through the first passivation protection layer 9 of the capacitor unit, as shown in fig. 10. Generally, the first passivation protection connecting hole 10 of the capacitor unit is located outside the nano forest in the carrier substrate, and the corresponding upper electrode layer 10 can be exposed through the first passivation protection connecting hole 10 of the capacitor unit. The specific size and position of the first passivation connecting hole 10 of the capacitor unit can be selected according to actual needs, and will not be described herein.
Step 1-10, filling an upper electrode first leading-out connector 11 in the first passivation protection connection hole 10 of the capacitor unit, where the upper electrode first leading-out connector 11 is electrically connected to the upper electrode layer 8, as shown in fig. 11. The upper electrode first lead-out connector 11 may be made of a conventional metal material, such as aluminum-silicon-copper alloy, and the specific material type may be selected as required, as long as it can be filled in the capacitor unit first passivation protection connection hole 10 and electrically connected to the upper electrode layer 8, which is not described herein again. The height of the upper electrode first lead-out connector 11 may be consistent with the thickness of the capacitive unit first passivation protection layer 9 on the nano-forest carrier substrate 1.
Step 1-11, a capacitor unit second passivation layer 12 is disposed on the capacitor unit first passivation layer 9, and the capacitor unit second passivation layer 12 can cover the capacitor unit first passivation layer 9 and the upper electrode first leading-out connector 11 at the same time, as shown in fig. 12. The second passivation layer 12 of the capacitor unit may specifically be made of a conventional material, such as silicon nitride, and the process and manner for specifically preparing the second passivation layer 12 of the capacitor unit may be selected as needed, which are well known to those skilled in the art and will not be described herein again. The thickness of the second passivation and protection layer 12 of the capacitor unit may be generally 1.5 μm to 2 μm.
Specifically, the etching of the second passivation layer 12 of the capacitor unit can be realized by a common technical means in the technical field, and generally, the second passivation connection hole 13 of the capacitor unit is located right above the first leading-out connector 11 of the upper electrode, so that the end of the first leading-out connector 11 of the upper electrode can be in a fully exposed state.
Step 1-13, depositing an electrode leading-out connecting layer 14 on the second passivation protective layer 12 of the capacitor unit, wherein the upper electrode leading-out connecting layer 14 covers the second passivation protective layer 12 of the capacitor unit and can be filled in the second passivation protective connecting hole 13 of the capacitor unit, the upper electrode leading-out connecting layer 14 can be in contact with the upper electrode first leading-out connecting body 11, and the upper electrode leading-out connecting layer 14 can be electrically connected with the upper electrode layer 8 through the upper electrode first leading-out connecting body 11.
As shown in fig. 14, the upper electrode lead-out connection layer 14 may specifically adopt a conventional commonly used lead-out connection metal material, such as nickel, and the specific material type may be selected as needed, which is not described herein again. The thickness of the upper-electrode lead-out connection layer 14 may be generally 5 μm to 10 μm. The upper electrode lead-out connecting layer 14 can cover the capacitor unit second passivation protective layer 12, an upper electrode second lead-out connecting body can be formed by filling the capacitor unit second passivation protective connecting hole 13, and the electrode second lead-out connecting body is contacted with the upper electrode first lead-out connecting body 11, so that the upper electrode lead-out connecting layer 14 can be electrically connected with the upper electrode layer 8 through the upper electrode first lead-out connecting body 11, and the lead-out of the upper electrode layer 8 is realized.
As is apparent from the above description, the capacitor cell first passivation layer 9 and the capacitor cell second passivation layer 12 may collectively form an electrode lead-out insulating layer, and the upper electrode lead-out connecting layer 14 is supported by the electrode lead-out insulating layer.
Example 2
As shown in fig. 15 and fig. 16, which are schematic diagrams of implementation steps in embodiment 2, in fig. 15, in order to obtain a second passivation connection hole 19 of a capacitor unit simultaneously when preparing a first passivation connection hole 10 of the capacitor unit, the second passivation connection hole 19 of the capacitor unit can expose the nano forest carrier substrate 1, that is, the front surface of the capacitor substrate. Of course, the process and manner for preparing the first passivation layer 9 of the capacitor unit on the nano forest carrier substrate 1 can refer to the above description, and are not described herein again. Certainly, the first passivation protection connection hole 10 of the capacitor unit and the second passivation protection connection hole 19 of the capacitor unit can be simultaneously prepared by adopting a common technical means in the technical field, and the specific process and process conditions are well known to those skilled in the art and will not be described herein again.
As shown in fig. 16, when the first leading-out connecting body 11 of the upper electrode is filled in the first passivation protection connecting hole 10 of the capacitor unit, the leading-out connecting body 20 of the lower electrode filled in the second passivation protection connecting hole 19 of the capacitor unit can be obtained at the same time, and the leading-out connecting body 20 of the lower electrode is in ohmic contact with the nano forest carrier substrate 1, so that the electrical connection with the lower electrode layer 6 can be realized through the nano forest carrier substrate 1. Namely, the lower electrode drawing unit includes a lower electrode drawing connector 20.
The subsequent processes of preparing the capacitor unit second passivation protection layer 12, the capacitor unit second passivation protection connection hole 13 and the upper electrode lead-out connection layer 14 are consistent with the above process steps, and reference may be made to the above description. Of course, in specific implementation, the form of electrical connection between the upper electrode lead-out connecting layer 14 and the upper electrode layer 8 through the upper electrode first lead-out connector 11 can be referred to, so that the form of connection and matching between the lower electrode lead-out unit and the lower electrode lead-out connector 20 can be obtained, and details are not described here.
To sum up, in embodiment 2, the upper electrode lead-out unit and the lower electrode lead-out unit are both located on the same side of the capacitor substrate, that is, both located on the front side of the capacitor substrate. In embodiment 1, the upper electrode lead-out unit and the lower electrode lead-out unit are located on both sides of the capacitor substrate.
Example 3
As shown in fig. 17 to 27, the specific process of the embodiment includes the following steps:
step a, providing a nanometer forest support substrate 15 for forming a capacitance substrate, and arranging a support substrate mask layer 16 on the nanometer forest support substrate 15;
as shown in fig. 17, the nano forest support substrate 15 may be a silicon substrate, and the support substrate mask layer 16 is a material capable of preparing nano forests, such as PI, which may be specifically selected as needed and is not described herein again.
And b, etching the supporting substrate mask layer 16 to form a required mask layer body nanometer forest by utilizing the carrier substrate mask layer 16, wherein the height of a mask layer body nanometer column 17 in the mask layer body nanometer forest is consistent with the thickness of the supporting substrate mask layer 16, so that a required nanometer forest structure can be formed by utilizing the mask layer body nanometer forest.
Specifically, the supporting substrate mask layer 16 may be etched by using a conventional nano forest etching process to form a mask layer body nano forest after etching, where the mask layer body nano forest has a plurality of mask layer body nano pillars 17 and mask layer body nano pillar grooves 18, as shown in fig. 18. The object of step 1 can be achieved by steps a and b.
When the mask layer body nanometer forest is formed by using the supporting substrate mask layer 16 as a nanometer forest structure, the supporting substrate mask layer 16 needs to be etched, namely, the height of the mask layer body nanometer column 17 is consistent with the thickness of the etched supporting substrate mask layer 16, namely, the nanometer forest structure can be directly prepared on the nanometer forest supporting substrate 15, the nanometer forest supporting substrate 15 supports the prepared nanometer forest structure, the area corresponding to the nanometer forest supporting substrate 15 can be exposed through the mask layer body nanometer column groove 18, and therefore the electrode layer 6 can be in ohmic contact with the nanometer forest supporting substrate 15 in the following process.
And c, preparing the lower electrode layer 6 matched with the mask layer body nanometer forest, as shown in fig. 19. The specific process for preparing the lower electrode layer 6 and the nano forest cooperation of the mask layer body serving as the nano forest structure can refer to the above description, and details are not repeated here.
Step d, preparing the capacitor dielectric layer 7, and covering the capacitor dielectric layer 7 on the lower electrode layer 6, as shown in fig. 20, for the specific processes of preparing the capacitor dielectric layer 7 and matching with the lower electrode layer 6, reference may be made to the description of embodiment 1, and details are not repeated here.
After the upper electrode layer 8 is prepared in step e, the upper electrode layer 8 covers the capacitor dielectric layer 7, as shown in fig. 21, the specific preparation process can refer to the description of the above embodiment 1, and details are not repeated here.
And f, preparing to obtain a first passivation protection layer 9 of the capacitor unit, wherein the first passivation protection layer 9 of the capacitor unit covers the upper electrode layer 8, as shown in fig. 22, and the specific process refers to the above description, which is not repeated herein.
Step g, preparing the first passivation protection connection hole 10 of the capacitor unit, where the first passivation protection connection hole 10 of the capacitor unit penetrates through the first passivation protection layer 9 of the capacitor unit, as shown in fig. 23, the process of specifically preparing the first passivation protection connection hole 10 of the capacitor unit may be described with reference to the above embodiment 1, and details are not repeated here.
Step h, filling the capacitor unit first passivation protection connection hole 10 with the upper electrode first leading-out connection body 11, as shown in fig. 24, for a specific process of obtaining the upper electrode first leading-out connection body 11, reference may be made to the above description, and details are not repeated here.
Step i, disposing a second passivation layer 12 on the first passivation layer 9 of the capacitor unit, as shown in fig. 25, which may refer to the above description specifically, and will not be described herein again.
Step j, selectively masking and etching the capacitor unit second passivation layer 12 to obtain a capacitor unit second passivation connection hole 13 penetrating through the capacitor unit second passivation layer 12, where the capacitor unit second passivation connection hole 13 corresponds to the upper electrode first leading-out connector 11, as shown in fig. 26, the above description may be specifically referred to, and details are not repeated here.
And k, depositing an electrode leading-out connecting layer 14 on the capacitor unit second passivation protective layer 12, wherein the upper electrode leading-out connecting layer 14 covers the capacitor unit second passivation protective layer 12 and can be filled in the capacitor unit second passivation protective connecting hole 13, the upper electrode leading-out connecting layer 14 can be in contact with the upper electrode first leading-out connecting body 11, and the upper electrode leading-out connecting layer 14 can be electrically connected with the upper electrode layer 8 through the upper electrode first leading-out connecting body 11, as shown in fig. 27, the specific process can refer to the above description, and is not repeated here.
Claims (5)
1. A preparation method of an MEMS super capacitor based on a nano forest is characterized by comprising the following steps:
step 1, providing a capacitor substrate, and preparing a nano forest structure matched with the capacitor substrate;
step 2, preparing a needed capacitor unit body, wherein the capacitor unit body comprises a lower electrode layer, a capacitor dielectric layer and an upper electrode layer which are deposited in sequence and cover the nano forest structure, the lower electrode layer covers the nano forest structure, the capacitor dielectric layer covers the lower electrode layer, the upper electrode layer covers the capacitor dielectric layer, and the lower electrode layer is in ohmic contact with the capacitor substrate;
step 3, preparing an upper electrode leading-out unit on the capacitor unit body, wherein the upper electrode leading-out unit covers the upper electrode layer, and the upper electrode leading-out unit is electrically connected with the upper electrode layer so as to form an upper electrode of the capacitor;
in step 3, the specific process for preparing the upper electrode lead-out unit comprises the following steps:
step 3.1, depositing a first passivation protection layer of the capacitor unit, wherein the first passivation protection layer of the capacitor unit covers the upper electrode layer;
step 3.2, selectively masking and etching the first passivation protection layer of the capacitor unit to obtain a first passivation protection connecting hole of the capacitor unit, which penetrates through the first passivation protection layer of the capacitor unit, and exposing an upper electrode layer which is just corresponding to the first passivation protection connecting hole of the capacitor unit through the first passivation protection connecting hole of the capacitor unit;
step 3.3, filling an upper electrode first lead-out connector in the first passivation protection connecting hole of the capacitor unit, wherein the upper electrode first lead-out connector is electrically connected with the upper electrode layer;
step 3.4, arranging a second passivation protective layer of the capacitor unit on the first passivation protective layer of the capacitor unit;
3.5, selectively masking and etching the second passivation protection layer of the capacitor unit to obtain a second passivation protection connecting hole of the capacitor unit, which penetrates through the second passivation protection layer of the capacitor unit, wherein the second passivation protection connecting hole of the capacitor unit corresponds to the first leading-out connecting body of the upper electrode so as to expose the first leading-out connecting body of the upper electrode through the second passivation protection connecting hole of the capacitor unit;
and 3.6, depositing an upper electrode leading-out connecting layer on the second passivation protective layer of the capacitor unit, wherein the upper electrode leading-out connecting layer covers the second passivation protective layer of the capacitor unit and can be filled in the second passivation protective connecting hole of the capacitor unit, the upper electrode leading-out connecting layer can be contacted with the upper electrode first leading-out connecting body, and the upper electrode leading-out connecting layer can be electrically connected with the upper electrode through the upper electrode first leading-out connecting body.
2. The method for preparing the MEMS super capacitor based on the nano forest as claimed in claim 1, wherein the step 1 specifically comprises the following steps:
step 1.1, providing a nano forest carrier substrate for forming a capacitance substrate, and arranging a carrier substrate mask layer on the nano forest carrier substrate;
step 1.2, etching the carrier substrate mask layer to form a required substrate mask layer nanometer forest by utilizing the carrier substrate mask layer;
step 1.3, etching the nano forest carrier substrate by using the substrate mask layer nano forest as a mask to obtain a carrier substrate inner nano forest in the nano forest carrier substrate;
and 1.4, removing the nano forest of the substrate mask layer to form a required nano forest structure by using the nano forest in the carrier substrate.
3. The method for preparing the nano-forest based MEMS super capacitor as claimed in claim 1, wherein the step 1 specifically comprises the following steps:
step a, providing a nano forest support substrate for forming a capacitance substrate, and arranging a support substrate mask layer on the nano forest support substrate;
and b, etching the supporting substrate mask layer so as to form a required mask layer body nano forest by using the supporting substrate mask layer, wherein the height of a mask layer body nano column in the mask layer body nano forest is consistent with the thickness of the supporting substrate mask layer so as to form a required nano forest structure by using the mask layer body nano forest.
4. The method of claim 1, wherein deposition processes used to form the lower electrode layer, the capacitor dielectric layer, and the upper electrode layer comprise atomic layer deposition.
5. The method for preparing the nano-forest based MEMS super capacitor as claimed in any one of claims 1 to 4, further comprising a lower electrode lead-out unit electrically connected with the capacitor substrate, wherein the lower electrode lead-out unit and the upper electrode lead-out unit are located on the same side of the capacitor substrate or respectively located on two corresponding sides of the capacitor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110825193.4A CN113555228B (en) | 2021-07-21 | 2021-07-21 | Nano forest based MEMS super capacitor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110825193.4A CN113555228B (en) | 2021-07-21 | 2021-07-21 | Nano forest based MEMS super capacitor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113555228A CN113555228A (en) | 2021-10-26 |
| CN113555228B true CN113555228B (en) | 2022-06-24 |
Family
ID=78103873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110825193.4A Active CN113555228B (en) | 2021-07-21 | 2021-07-21 | Nano forest based MEMS super capacitor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113555228B (en) |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5418316B2 (en) * | 2010-03-11 | 2014-02-19 | 富士通株式会社 | MEMS device |
| CN102568817A (en) * | 2012-03-01 | 2012-07-11 | 中北大学 | MEMS (Micro Electro Mechanical System) capacitor based on three-dimensional silicon micro structure and manufacturing method thereof |
| CN105845447A (en) * | 2015-01-13 | 2016-08-10 | 苏州复纳电子科技有限公司 | Nanorod-shaped electrode, nano structure supercapacitor, and preparation method for nano structure supercapacitor |
| CN105043603A (en) * | 2015-06-04 | 2015-11-11 | 东南大学 | Capacitive pressure sensor provided with self-detection apparatus, and preparation method thereof |
| CN105293428B (en) * | 2015-10-19 | 2017-04-19 | 北京航天控制仪器研究所 | Full silicification wafer level vacuum encapsulation method and device for MEMS (Micro-Electro-Mechanical System) device |
| CN105355448B (en) * | 2015-11-25 | 2018-02-02 | 太原理工大学 | A kind of MEMS supercapacitor based on high dielectric constant film and preparation method thereof |
| CN108793065B (en) * | 2018-06-25 | 2020-09-15 | 太原理工大学 | Preparation method of MEMS (micro-electromechanical systems) supercapacitor with controllable dielectric film thickness |
| CN108717936A (en) * | 2018-06-27 | 2018-10-30 | 长鑫存储技术有限公司 | Double sided capacitor structure and preparation method thereof |
| CN110092346B (en) * | 2019-04-17 | 2022-06-07 | 西安交通大学 | Silicon-based MEMS super capacitor and preparation method thereof |
| CN111446083A (en) * | 2020-03-12 | 2020-07-24 | 复旦大学 | Silicon-based super capacitor and preparation method thereof |
-
2021
- 2021-07-21 CN CN202110825193.4A patent/CN113555228B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN113555228A (en) | 2021-10-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10497582B2 (en) | Capacitor formed in insulated pores of an anodized metal layer | |
| CN102906834B (en) | The preparation method of Electricity storage device, its preparation method, its conductive structure, use its mobile electronic device and comprise its microelectronic device | |
| JP4907594B2 (en) | Capacitor and manufacturing method thereof | |
| US9928966B2 (en) | Nanostructured electrolytic energy storage devices | |
| US9601278B2 (en) | Super-capacitor with separator and method of producing the same | |
| US10811193B2 (en) | Capacitor component | |
| CN111244065A (en) | Integrated circuit capacitor array structure, semiconductor memory and preparation method | |
| CN102569250A (en) | High-density capacitor and electrode leading-out method thereof | |
| US20160064149A1 (en) | Method of producing a super-capacitor | |
| US20160087030A1 (en) | Capacitor cell and method for manufacturing same | |
| US20220208968A1 (en) | Manufacturing method of a nanowire-based structure and capacitor array component including the structure | |
| US20130128413A1 (en) | High energy density storage material device using nanochannel structure | |
| EP3656734A1 (en) | Nanowire structure enhanced for stack deposition | |
| US7446014B2 (en) | Nanoelectrochemical cell | |
| CN113555228B (en) | Nano forest based MEMS super capacitor and preparation method thereof | |
| US11903182B2 (en) | Capacitor and manufacturing method therefor | |
| US10103218B1 (en) | Densely stacked metal-insulator-metal capacitor and method of forming the same | |
| CN113517273B (en) | Capacitor array structure, method for manufacturing the same and semiconductor memory device | |
| CN111987075A (en) | Three-dimensional capacitor structure and manufacturing method thereof | |
| US20230260712A1 (en) | Layered charge storage device with two different types of electrode materials and a protective enclosure | |
| EP4432812A1 (en) | Method of forming an integrated device with multiple capacitors by patterning a barrier after anodization | |
| CN115472433A (en) | High density capacitive device with well defined isolation regions | |
| US20220301784A1 (en) | High-density capacitive device and method for manufacturing such a device | |
| CN111863770A (en) | Three-dimensional capacitor structure and manufacturing method thereof | |
| KR20010065797A (en) | Method for forming capacitor in high capacitance memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |