CN113488098A - Counting algorithm based on FALSH memory - Google Patents
Counting algorithm based on FALSH memory Download PDFInfo
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- CN113488098A CN113488098A CN202110820057.6A CN202110820057A CN113488098A CN 113488098 A CN113488098 A CN 113488098A CN 202110820057 A CN202110820057 A CN 202110820057A CN 113488098 A CN113488098 A CN 113488098A
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- 230000001960 triggered effect Effects 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 238000009825 accumulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
- G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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Abstract
The invention discloses a counting algorithm based on a FALSH memory, relates to the technical field of memories, and aims to solve the problem that the service life is reduced due to the fact that the existing storage device erases a whole sector. The key point of the technical scheme is that reserved bytes of n sectors are sequentially set to be 0 from low to high, and when the sectors from 1 st to i (A) are in the order1+A2+……+Ai) All 0 bytes are set, i +1 th sector Ai+1The lowest position 0 of the 1 st byte in the bytes is simultaneously erased from the 1 st to the i-th sectors, and the position 0 is restarted from the lowest position of the first byte in the 1 st sector; when A of 1 st to i th sectors1、A2、……、AiAfter all 0 of each byte is set again, the A of the (i + 1) th sectori+1The 1 st byte in the bytes is 0 bit higher than the 0 bit; the erase and set operations are repeated until the bytes of the n sectors are all set to 0. The invention achieves the effect of prolonging the service life of the memory.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a counting algorithm based on a FALSH memory.
Background
In the embedded field, the FLASH memory chip has very wide application, simple hardware design and driving program, lower cost and good reliability compared with a Ferroelectric (FRAM) memory. Therefore, the FALSH storage chip is generally applied to low-cost measurement and control equipment, but the FALSH storage chip has the limitation of service life, and the service life is generally 100 ten thousand times. In embedded devices, frequent data storage is involved, such as electric meter or rain gauge pulse counting and accumulation, slot machine pulse counting and accumulation, etc., the total number of counts is often much greater than 100 ten thousand times in application, and there is a high requirement for reliability and accuracy of stored data.
The programming principle of FLASH is that only 1 can be written as 0, but 0 cannot be written as 1. Therefore, before FLASH programming, the corresponding sector must be erased, and the erasing process is a process of writing all bits to 1, changing all bytes in the sector to 0xFF, and then performing the most basic read, write and erase operations on false. This problem is to be solved, precisely because the entire sector is required for erasing, which results in a reduction in the lifetime of the FLASH memory.
Disclosure of Invention
The invention aims to provide a counting algorithm based on a FALSH memory, which achieves the effect of prolonging the service life of the memory.
The above object of the present invention is achieved by the following technical solutions:
a false memory based counting algorithm comprising the steps of:
selecting n sectors in a memory, and respectively reserving A in the n sectors1、A2、A3、……、AnA byte, erasing n sectors, and order A1、A2、A3……AnThe bytes are all 1;
the reserved bytes of the n sectors are sequentially set to 0 from low to high when the 1 st to i th sectors (A)1+A2+……+Ai) All 0 bytes are set, i +1 th sector Ai+1The lowest position 0 of the 1 st byte in each byte is simultaneously erased from the 1 st to the i th sectors, so that A of the 1 st to the i th sectors1、A2、……、AiSetting all bytes as 1, and restarting to set 0 from the lowest bit of the first byte in the 1 st sector;
when A of 1 st to i th sectors1、A2、……、AiAfter all 0 of each byte is set again, the A of the (i + 1) th sectori+1The 1 st byte in the bytes is 0 bit higher than the 0 bit;
the erase and set operations are repeated until the bytes of the n sectors are all set to 0.
The invention is further configured to: the service life of the memory being extended to the original one
And (4) doubling.
The invention is further configured to: the erasing and setting operations are performed after the memory receives the pulse signal.
The invention is further configured to: when the memory receives the pulse signal, the setting operation is triggered, or the erasing and setting operations are triggered simultaneously.
The invention is further configured to: when the memory receives the pulse signal, if the 1 st to i th sectors (A)1+A2+……+Ai) All the bytes are set to 0, and the erasing process of the 1 st to i th sectors and the (i + 1) th sector A are triggered simultaneouslyi+1The lowest position 0 operation of the 1 st byte in the byte, and the pulse signal received by the rest condition only triggers the setting operation.
The invention is further configured to: when in n sectors A1、A2、A3……AnWhen all the bytes are set to 0, n sectors are erased from sector A of sector 11The lowest order bit of the 1 st byte of the bytes starts at position 0.
In conclusion, the beneficial technical effects of the invention are as follows:
through the orderly management of the reserved bytes of the sectors, the frequency of the sector to be completely erased by the memory is reduced, the service life of the memory is greatly prolonged, and the erasing times of the memory in the life cycle of the embedded product are completely covered.
Drawings
Fig. 1 is a schematic overall structure diagram of a first embodiment of the present invention.
Detailed Description
Referring to fig. 1, the invention discloses a counting algorithm based on a false sh memory, comprising the following steps:
selecting n sectors in the memory, and respectively reserving A in the n sectors1、A2、A3、……、AnA byte, erasing n sectors, and order A1、A2、A3……AnThe bytes are all 1;
the reserved bytes of the n sectors are sequentially set to 0 from low to high when the 1 st to i th sectors (A)1+A2+……+Ai) All 0 bytes are set, i +1 th sector Ai+1The lowest position 0 of the 1 st byte in each byte is simultaneously erased from the 1 st to the i th sectors, so that A of the 1 st to the i th sectors1、A2、……、AiSetting all bytes as 1, and restarting to set 0 from the lowest bit of the first byte in the 1 st sector;
when A of 1 st to i th sectors1、A2、……、AiAfter all 0 of each byte is set again, the A of the (i + 1) th sectori+1The 1 st byte in the bytes is 0 bit higher than the 0 bit;
the erase and set operations are repeated until the bytes of the n sectors are all set to 0.
The service life of the memory being extended to the original one
And (4) doubling.
The erasing and setting operations are performed after the memory receives the pulse signal.
When the memory receives the pulse signal, the set operation is triggered, or the erasing and the set operation are triggered simultaneously.
When the memory receives the pulse signal, if the 1 st to i th sectors (A)1+A2+……+Ai) All the bytes are set to 0, and the erasing process of the 1 st to i th sectors and the (i + 1) th sector A are triggered simultaneouslyi+1The lowest position 0 operation of the 1 st byte in the byte, and the pulse signal received by the rest condition only triggers the setting operation.
When in n sectors A1、A2、A3……AnWhen all the bytes are set to 0, n sectors are erased from sector A of sector 11In a byte, the firstThe lowest order bit of 1 byte starts with position 0.
The specific implementation manner of this embodiment is:
1. reserving an 8-Bit variable u8_ First _ weight _ Bit _ Num in a First sector, erasing the First sector in advance, and setting u8_ First _ weight _ Bit _ Num to be 0 xFF;
2. reserving an 8-Bit variable u8_ Second _ weight _ Bit _ Num in the Second sector, erasing the Second sector in advance, and setting u8_ Second _ weight _ Bit _ Num to be 0 xFF;
3. when the embedded device peripheral circuit detects the pulse, the counting is started:
the First pulse comes, u8_ First _ light _ Bit _ Num is 11111111110;
the second pulse comes, u8_ First _ light _ Bit _ Num is 11111100;
the third pulse comes, u8_ First _ weight _ Bit _ Num is 11111000;
the fourth pulse comes, u8_ First _ light _ Bit _ Num is 11110000;
the fifth pulse comes, u8_ First _ weight _ Bit _ Num is 11100000;
the sixth pulse arrives, u8_ First _ light _ Bit _ Num is 11000000;
the seventh pulse comes, u8_ First _ light _ Bit _ Num is 10000000;
the eighth pulse arrives, u8_ First _ weight _ Bit _ Num is 00000000;
4. when the variable u8_ First _ weight _ Bit _ Num in the First sector is 00000000, the variable u8_ Second _ weight _ Bit _ Num in the Second sector is 11111111110, and so on, and when u8_ Second _ weight _ Bit _ Num is 000000000000, 8 is counted 8 is 64 pulses.
To summarize this: using only two FALSH sectors, each occupying only 1 byte of space, extends the FLASH life by 8 × 8 to 64 times, i.e. the total count is extended by 64 × 100 ten thousand to 6400 ten thousand. Then if two sectors, each reserving a 32-bit variable, the lifetime is extended to 32 x 32 to 1024 times, i.e. the total FLASH count is extended to 1024 x 100 ten to 102400 ten thousand times.
In the same way, according to different FALSH models and the number of sectors, the full coverage of FALSH erasing and writing times in the life cycle of the embedded product can be theoretically realized according to the dependence of software.
The embodiments of the present invention are preferred embodiments of the present invention, and the scope of the present invention is not limited by these embodiments, so: all equivalent changes made according to the structure, shape and principle of the invention are covered by the protection scope of the invention.
Claims (6)
1. A false memory based counting algorithm comprising the steps of:
selecting n sectors in a memory, and respectively reserving A in the n sectors1、A2、A3、……、AnA byte, erasing n sectors, and order A1、A2、A3……AnThe bytes are all 1;
the reserved bytes of the n sectors are sequentially set to 0 from low to high when the 1 st to i th sectors (A)1+A2+……+Ai) All 0 bytes are set, i +1 th sector Ai+1The lowest position 0 of the 1 st byte in each byte is simultaneously erased from the 1 st to the i th sectors, so that A of the 1 st to the i th sectors1、A2、……、AiSetting all bytes as 1, and restarting to set 0 from the lowest bit of the first byte in the 1 st sector;
when A of 1 st to i th sectors1、A2、……、AiAfter all 0 of each byte is set again, the A of the (i + 1) th sectori+1The 1 st byte in the bytes is 0 bit higher than the 0 bit;
the erase and set operations are repeated until the bytes of the n sectors are all set to 0.
2. A false memory based counting algorithm according to claim 1, characterized in that: the service life of the memory being extended to the original one
And (4) doubling.
3. A false memory based counting algorithm according to claim 2, characterized in that: the erasing and setting operations are performed after the memory receives the pulse signal.
4. A false memory based counting algorithm according to claim 3, characterized in that: when the memory receives the pulse signal, the setting operation is triggered, or the erasing and setting operations are triggered simultaneously.
5. A FALSH memory based counting algorithm according to claim 4, characterized in that: when the memory receives the pulse signal, if the 1 st to i th sectors (A)1+A2+……+Ai) All the bytes are set to 0, and the erasing process of the 1 st to i th sectors and the (i + 1) th sector A are triggered simultaneouslyi+1The lowest position 0 operation of the 1 st byte in the byte, and the pulse signal received by the rest condition only triggers the setting operation.
6. A FALSH memory based counting algorithm according to claim 5, characterized in that: when in n sectors A1、A2、A3……AnWhen all the bytes are set to 0, n sectors are erased from sector A of sector 11The lowest order bit of the 1 st byte of the bytes starts at position 0.
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| CN202110820057.6A CN113488098A (en) | 2021-07-20 | 2021-07-20 | Counting algorithm based on FALSH memory |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1782924A (en) * | 2004-12-03 | 2006-06-07 | 京瓷美达株式会社 | Counter device and counting method |
| CN101419838A (en) * | 2008-09-12 | 2009-04-29 | 中兴通讯股份有限公司 | Method for enhancing using life of flash |
| CN106844583A (en) * | 2017-01-10 | 2017-06-13 | 厦门雅迅网络股份有限公司 | A kind of optimization method that FAT file system is set up on NOR Flash |
| CN111009274A (en) * | 2018-10-08 | 2020-04-14 | 华邦电子股份有限公司 | Flash memory storage device and operation method thereof |
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- 2021-07-20 CN CN202110820057.6A patent/CN113488098A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1782924A (en) * | 2004-12-03 | 2006-06-07 | 京瓷美达株式会社 | Counter device and counting method |
| CN101419838A (en) * | 2008-09-12 | 2009-04-29 | 中兴通讯股份有限公司 | Method for enhancing using life of flash |
| CN106844583A (en) * | 2017-01-10 | 2017-06-13 | 厦门雅迅网络股份有限公司 | A kind of optimization method that FAT file system is set up on NOR Flash |
| CN111009274A (en) * | 2018-10-08 | 2020-04-14 | 华邦电子股份有限公司 | Flash memory storage device and operation method thereof |
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