CN113467179A - Mask, manufacturing method of array substrate and display panel - Google Patents
Mask, manufacturing method of array substrate and display panel Download PDFInfo
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- CN113467179A CN113467179A CN202110707248.1A CN202110707248A CN113467179A CN 113467179 A CN113467179 A CN 113467179A CN 202110707248 A CN202110707248 A CN 202110707248A CN 113467179 A CN113467179 A CN 113467179A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a mask, a manufacturing method of an array substrate and a display panel. Wherein, the mask includes: the device comprises a first exposure area corresponding to a channel area, a second exposure area located on one side of the first exposure area and used for forming a source electrode, a third exposure area located on the other side opposite to the first exposure area and used for forming a drain electrode, and a fourth exposure area located on one side of the third exposure area and deviated from the first exposure area, wherein the first exposure area and the fourth exposure area are semi-transparent areas. In the process of exposure and development of the mask plate, part of the light resistance can be left in the areas corresponding to the first exposure area and the fourth exposure area, and the area where the channel is to be formed and the area where the drain is to be formed are protected, so that the aperture opening ratio of pixels is improved.
Description
Technical Field
The invention relates to the technical field of display panel preparation, in particular to a mask, a manufacturing method of an array substrate and a display panel.
Background
At present, the design of an array substrate adopts a 4mask (four-pass lithography process) design, a thin film transistor (TFT switch) is formed by patterning through a photomask process, but the loss of the critical dimension of a drain electrode is large after two times of etching, usually, in order to ensure that the drain electrode is not etched and broken or the critical dimension is not too small, the design dimension value of the drain electrode is specially increased when the dimension of the drain electrode is designed, so that the aperture ratio of pixels is reduced. Moreover, for a structure in which a Post Spacer (PS) cannot stand on the TFT switch, the design space of the Post Spacer is severely compressed, which causes the Post Spacer to extend toward the pixel, further affecting the aperture ratio of the pixel; or the size of the columnar spacer is too small, thereby causing the abnormal process of the columnar spacer or the reliability problem caused by the columnar spacer.
Disclosure of Invention
The invention mainly aims to provide a mask plate, wherein the parts of the mask plate corresponding to a channel region and the outer periphery of a drain electrode are set to be semi-light-transmitting regions, so that part of light resistance can be left in the regions corresponding to a first exposure region and a fourth exposure region in the exposure and development processes, the channel region to be formed and the region where the drain electrode is to be formed are protected, the size loss of the channel region and the periphery of the drain electrode is effectively reduced, and the problems that the opening ratio is small and the size of a columnar spacer is too small due to the large design size of the drain electrode are solved.
In order to achieve the above object, the mask provided by the present invention is used for preparing an array substrate, the array substrate includes a thin film transistor, the thin film transistor includes a gate, a source, and a drain arranged at an interval, a channel region is formed between the source and the drain, and the mask includes: the device comprises a first exposure area corresponding to the channel area, a second exposure area located on one side of the first exposure area and used for forming a source electrode, a third exposure area located on the other side opposite to the first exposure area and used for forming a drain electrode, and a fourth exposure area located on one side of the third exposure area, which is far away from the first exposure area, wherein the first exposure area and the fourth exposure area are semi-transparent areas.
In an embodiment of the present application, the width of the fourth exposure area ranges from 1 μm to 2 μm;
and/or the width range of the first exposure area is 3-5 mu m.
In an embodiment of the present application, the mask further includes a fifth exposure area, and the fifth exposure area is disposed on a side of the fourth exposure area departing from the third exposure area.
In an embodiment of the present application, the first exposure region and the fourth exposure region have the same light transmittance;
and/or the fourth exposure area and the third exposure area are arranged without gaps.
In an embodiment of the present application, the third exposure area and the fourth exposure area are both disposed in a U shape, and lengths of two opposite edges of the fourth exposure area and the third exposure area are the same.
The invention also provides a method for manufacturing an array substrate by adopting the mask, which comprises the following steps:
providing a substrate, and sequentially forming a grid electrode and a grid electrode insulating layer on the substrate from bottom to top;
depositing a semiconductor layer, a first metal layer and a first light resistance layer on the grid electrode insulating layer in sequence, wherein a channel region is arranged at the position of the semiconductor layer corresponding to the grid electrode;
arranging the mask above the first photoresist layer, and exposing and developing the first photoresist layer;
and patterning the semiconductor layer and the first metal layer by using the residual first photoresist layer to form an active layer on the gate insulating layer and source and drain electrodes arranged at intervals on the active layer.
In an embodiment of the present application, the second exposure region and the third exposure region are opaque regions, the fifth exposure region is a fully transparent region, and the photoresist is a positive photoresist.
In an embodiment of the present application, the step of patterning the semiconductor layer and the first metal layer by using the remaining first photoresist layer to form an active layer on the gate insulating layer and spaced source and drain electrodes on the active layer specifically includes:
carrying out first etching to remove the first metal layer and the semiconductor layer which are not covered by the first photoresist layer;
performing an ashing process to remove the first photoresist layer of the channel region and the first photoresist layer of the fourth exposure region;
and performing second etching to remove the first metal layer and part of the semiconductor layer in the channel region and the first metal layer and the semiconductor layer in the fourth exposure region, and forming an active layer, and a source electrode and a drain electrode which are contacted with two ends of the active layer and are arranged at intervals.
In an embodiment of the present application, after the step of patterning the semiconductor layer and the first metal layer by using the remaining first photoresist layer to form an active layer on the gate insulating layer and spaced source and drain electrodes on the active layer, the method further includes:
depositing a second photoresist layer on the gate insulating layer to form a columnar spacer;
and patterning the second photoresist layer to form a columnar spacer arranged at an interval with the drain electrode.
The invention further provides a display panel which comprises a color film substrate, an array substrate and a liquid crystal layer, wherein the color film substrate and the array substrate are arranged in a box-to-box mode, and the array substrate is prepared by adopting the manufacturing method of any one of the array substrates.
In the technical scheme of the invention, the first exposure region of the mask corresponding to the channel region between the drain and the source is a semi-transparent region, and the fourth exposure region corresponding to the periphery of the drain to be formed, namely the fourth exposure region is also set as the semi-transparent region. Therefore, when the mask is used for manufacturing the array substrate, in the process of exposure and development, partial photoresist is remained in the first exposure area and the fourth exposure area, a channel area to be formed and an area to be formed with a drain electrode are protected, the etching probability is reduced, the size loss of the channel area and the peripheral edge of the drain electrode is effectively reduced, the design size value of a drain stage does not need to be increased, and the aperture opening ratio of pixels is correspondingly improved. Meanwhile, the reduction of the design size of the drain electrode also can reserve more design space for the columnar spacer, thereby avoiding the problem of abnormal manufacturing process caused by undersize of the columnar spacer or reliability caused by the columnar spacer, avoiding the extension of the columnar spacer to the direction of the pixel, and further improving the aperture opening ratio of the pixel.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic top view of a mask according to an embodiment of the present disclosure;
fig. 2 is a schematic top view illustrating the application of the mask shown in fig. 1 to an array substrate according to a first embodiment of the present disclosure;
fig. 3 is a flowchart illustrating a method for manufacturing an array substrate according to a second embodiment of the present application;
fig. 4 is a cross-sectional view of the array substrate corresponding to steps S1 and S2 in the method for manufacturing the array substrate shown in fig. 3 according to the second embodiment of the present application;
fig. 5 is a cross-sectional view of the array substrate corresponding to step S3 in the method for manufacturing the array substrate shown in fig. 3 according to the second embodiment of the present application;
fig. 6 is a flowchart illustrating a thinning step S4 in the method for manufacturing the array substrate shown in fig. 3 according to the second embodiment of the present application;
fig. 7 is a cross-sectional view of the array substrate corresponding to the thinning step S41 and the step S42 in the method for manufacturing the array substrate shown in fig. 6 according to the second embodiment of the present application;
fig. 8 is a cross-sectional view of the array substrate corresponding to the thinning step S43 in the method for manufacturing the array substrate shown in fig. 6 according to the second embodiment of the present application;
FIG. 9 is a flowchart of the second embodiment of the method for fabricating an array substrate with the addition of step S5 and step S6;
fig. 10 is a schematic top view illustrating the array substrate corresponding to steps S5 and S6 in the method for manufacturing the array substrate shown in fig. 8 according to the second embodiment of the present application;
fig. 11 is a schematic view of a display panel according to a third embodiment of the present application.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 100 | |
80 | |
| 10 | |
90 | |
| 20 | |
200 | |
| 30 | |
201 | |
| 40 | |
203 | |
| 41 | |
205 | |
| 43 | Active layer | 207 | A fourth exposure region |
| 50 | A first metal layer | 209 | A |
| 51 | |
300 | |
| 53 | Drain electrode | 400 | |
| 60 | The |
500 | |
| 70 | Columnar spacer |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The first embodiment is as follows:
the invention provides a mask 200 for manufacturing an array substrate.
Referring to fig. 1 and 2, it can be known that the array substrate includes a thin film transistor, the thin film transistor includes a gate, a source 51 and a drain 53 that are disposed at intervals, and a channel region 41 is formed between the source 51 and the drain 53. The reticle 200 includes: a first exposure region 201 corresponding to the channel region 41, a second exposure region 203 located on one side of the first exposure region 201 and used for forming the source 51, a third exposure region 205 located on the other side opposite to the first exposure region 201 and used for forming the drain 53, and a fourth exposure region 207 located on one side of the third exposure region 205 opposite to the first exposure region 201, wherein the first exposure region 201 and the fourth exposure region 207 are semi-transparent regions.
Here, in order to form the source electrode 51 and the drain electrode 53 having a desired shape and a channel region therebetween, a part of the mask 200 needs to be transparent, and a part of the mask needs to be opaque or semi-transparent. In order to increase the charging rate and display effect of the array substrate 100, the width-to-length ratio of the channel region 41 is generally designed to be as large as possible, and the opening of the channel region 41 is substantially U-shaped, so that the first exposure region 201 is U-shaped. Of course, in other embodiments, the opening of the channel region 41 may also be semicircular, rectangular, or other shapes. The second exposure region 203 corresponds to the position of the source 51, so that the second exposure region 203 is substantially rectangular, is located in the space enclosed by the channel region 41, and extends towards the opening side of the channel region 41, and the formed source 51 is conveniently connected with the data line 80. The third exposed region 205 corresponds to the position of the drain 53, so the drain 53 is also U-shaped, thereby enclosing a U-shaped channel.
The mask 200 is provided with the first exposure region 201 and the fourth exposure region 207 which are both semi-transparent regions, and no matter whether the used photoresist is a positive photoresist or a negative photoresist, after exposure and development, the photoresist corresponding to the first exposure region 201 and the fourth exposure region 207 can be partially washed off and partially left, so that the size loss of the outer peripheries of the channel region 41 and the drain 53 can be reduced in the subsequent etching process.
In the technical solution of the present invention, the first exposure region 201 of the mask 200 corresponding to the channel region 41 between the drain 53 and the source 51 is a semi-transparent region, and the fourth exposure region 207 corresponding to the periphery of the drain 53 to be formed is also set as a semi-transparent region. Thus, when the mask 200 is used to manufacture an array substrate, during the exposure and development processes, a portion of photoresist will remain in the first exposure region 201 and the fourth exposure region 207, and protect the region to be formed with the channel region 41 and the region to be formed with the drain 53, thereby reducing the etching probability, and effectively reducing the size loss of the periphery of the channel region 41 and the drain 5, so that the design size value of the drain 53 does not need to be increased, and the aperture ratio of the pixel is correspondingly increased. Meanwhile, the reduction of the design size of the drain 53 also can reserve more design space for the columnar spacer, thereby avoiding the problem of abnormal manufacturing process caused by undersize of the columnar spacer or reliability caused by the columnar spacer, avoiding the extension of the columnar spacer to the direction of the pixel, and further improving the aperture opening ratio of the pixel.
Here, the mask 200 may be a halftone mask that combines two processes completed by two exposure processes into one, and one exposure process is saved, thereby shortening a production period, improving production efficiency, and reducing production cost.
With reference to fig. 2, in another embodiment of the present disclosure, the width of the first exposure region 201 is D1, the width of the fourth exposure region 207 is D2, the first exposure region 201 is projected on the array substrate 100 corresponding to the channel region 41, and therefore the width of the corresponding channel region 41 is also D1, the fourth exposure region 207 is projected on the array substrate 100 corresponding to a region of the drain 53 on a side away from the source 51, and the width D1 of the first exposure region 201 is 3-5 μm;
and/or the width D2 of the fourth exposure area 207 is 1-2 μm.
In this embodiment, generally, the width of the channel region 41 is set to be 3-5 μm, in order to ensure the width of the channel region 41, here, the width D1 of the first exposure region 201 is set to be 3-5 μm, for example, 3 μm, 4 μm or 5 μm, matching the width of the channel region 41, the second exposure region 203 is disposed without a gap from the first exposure region 201, and the third exposure region 205 is disposed without a gap from the first exposure region 201, thereby ensuring the width of the channel region 41 and ensuring the charging rate of the array substrate 100.
Meanwhile, in order to ensure that the loss rate of the critical dimension of the side of the drain 53 away from the source 51 is reduced, the value of the width D2 of the fourth exposure region 207 cannot be too small; in order to save cost, the value of the width D2 of the fourth exposure region 207 does not need to be too large, so that the width D2 of the fourth exposure region 207 is set to be 1-2 μm, for example, 1 μm, 1.5 μm, 2 μm, etc., which can not only ensure the protection of the peripheral dimension of the drain 53 at the side away from the source 51, but also avoid the inaccuracy of the dimension of the drain 53 caused by the small etching dimension, thereby effectively ensuring the design dimension of the drain 53, reducing the occupation of the display area, and improving the aperture ratio of the pixel.
Referring to fig. 1, in another embodiment of the present application, on the basis of the first embodiment, the reticle 200 further includes a fifth exposure region 209, and the fifth exposure region 209 is disposed on a side of the fourth exposure region 207, which is away from the third exposure region 205.
In this embodiment, for convenience of processing, the semiconductor layer 40, the first metal layer 50 and the first photoresist layer 60 are uniformly disposed on the gate insulating layer 30, and for designing the mask 200, a fifth exposure region 209 is further disposed on a side of the fourth exposure region 207 away from the third exposure region 205. Here, the fifth exposure region 209 and the fourth exposure region 207 are also disposed without a gap, so that the size of the fourth exposure region 207 can be easily changed when necessary, thereby satisfying the process protection for array substrates 100 of different sizes.
In an alternative embodiment, the third exposure region 205 is disposed without a gap from the first exposure region 201, and the second exposure region 203 is disposed without a gap from the first exposure region 201. The fourth exposure region 207 is disposed on a side of the third exposure region 205 facing away from the first exposure region 201, and may have the same shape as the third exposure region 205, so that the formation size of the source and drain electrodes 51 and 53 can be secured.
Of course, in other embodiments, the fifth exposure area 209 may not be set for saving material.
Referring to fig. 1 again, on the basis of the first embodiment, in a further embodiment of the present application, the light transmittances of the first exposure region 201 and the fourth exposure region 207 are the same;
and/or the fourth exposure area 207 is arranged without a gap from the third exposure area 205.
In this embodiment, in order to ensure the etching consistency, the light transmittance of the first exposure region 201 and the light transmittance of the fourth exposure region 207 are set to be the same, so that the thicknesses of the portions of the first photoresist layer 60 after exposure and development are substantially the same, and then in the subsequent patterning process, a uniform etching rate can be obtained at the same time, so that the peripheral size of the drain 53 can be ensured while a precise channel size is obtained, the loss is reduced, the design size of the thin film transistor is reduced, and the aperture ratio of the pixel is improved.
Meanwhile, the fourth exposure region 207 and the third exposure region 205 are disposed without a gap, so that the dimension loss of the edge of the drain 53 due to the etching solution entering the gap can be avoided. Of course, in other embodiments, the fourth exposure region 207 and the third exposure region 205 may be disposed intermittently without gaps in the extending direction of the drain 53.
In an embodiment of the present application, the third exposure area 205 and the fourth exposure area 207 are both U-shaped, and the lengths of two opposite edges of the fourth exposure area 207 and the third exposure area 205 are the same.
In this embodiment, in order to ensure the dimensions of each position of the drain 53, when the channel is U-shaped, the third exposure region 205 and the fourth exposure region 207 are also configured as U-shaped structures, and the inner length of the fourth exposure region 207 is consistent with the peripheral length of the third exposure region 205, so that the peripheral edge of the drain 53 is protected by the first photoresist layer 60, and the peripheral dimension of the drain 53 is not etched in the first etching process, thereby ensuring the critical peripheral dimension of the drain 53, reducing the dimension loss at all positions of the drain 53, and reserving more space for designing pixels.
Example two:
referring to fig. 2, fig. 3 and fig. 4, the present invention further provides a method for manufacturing an array substrate by using the mask of any of the above embodiments, the method including the following steps:
step S1: a substrate 10 is provided, and a gate electrode 20 and a gate insulating layer 30 are sequentially formed on the substrate 10 from bottom to top.
Referring to fig. 2, it can be understood that the array substrate 100 has a multi-layer structure, and each layer of the structure is formed by stacking a coating, exposing, developing and etching process layer by layer, and can be completed by four photolithography (4MASK) processes. Specifically, the array substrate 100 includes a substrate 10, the substrate 10 provides a basic carrier, and the substrate 10 is transparent, and the material of the substrate may be a transparent glass plate or a quartz plate, which is not limited herein, and does not affect the penetration of the backlight source. Since the substrate 10 is not conductive, a medium for displaying, such as liquid crystal, needs to be driven by electrons for movement and arrangement, the array substrate 100 further includes conductive Data lines 80 (DL), scan lines 90 (SL), thin film transistors (TFT switches), Pixel Electrodes (PE), and the like. Looking down the array substrate 100, the data lines 80 and the scan lines 90 are arranged in a crossed manner to divide the array substrate 100 into a plurality of pixel regions, each of the regions is provided with a corresponding pixel electrode and a corresponding thin film transistor, the data lines 80 and the scan lines 90 are opaque, so that the portions of the data lines and the scan lines form a non-display region of the pixel regions, the thin film transistors are also arranged in the non-display region, and the pixel electrodes form a display region of the pixel regions.
First, a gate 20 is formed on a substrate 10 by a first photolithography process, which includes depositing a second metal layer on the substrate 10, and patterning the second metal layer through a mask to form the gate 20 on the substrate 10. Here, the process of patterning through the mask is to deposit photoresist on the second metal layer, expose and develop the photoresist after being covered by the mask, and then form the gate 20 by etching, and at the same time, form the scan line 90 on the same layer as the gate 20, the scan line 90 is connected to the gate 20, so as to provide the on/off voltage for the thin film transistor. The material of the second metal layer is an opaque conductive metal material, such as one or a combination of molybdenum, titanium, chromium, and aluminum, which is not limited herein. Then, a gate insulating layer 30 is deposited on the surfaces of the substrate 10, the gate electrode 20 and the data line 80, wherein the material of the gate insulating layer 30 may be one or more of silicon oxide and silicon nitride.
Step S2: a semiconductor layer 40, a first metal layer 50 and a first photoresist layer 60 are sequentially deposited on the gate insulating layer 30, and a channel region 41 is formed in a position of the semiconductor layer 40 corresponding to the gate 20.
In this case, as is clear from the second photolithography step, the thin film transistor further includes an active layer 43 and source and drain electrodes 51 and 53 connected to both ends of the active layer 43 and spaced apart from each other, and the active layer 43 is formed of a semiconductor material, and the semiconductor layer 40 may be formed of a material such as amorphous silicon or polycrystalline silicon. The material of the first metal layer 50 may be the same as that of the second metal layer, for example, titanium, chromium, etc., and the semiconductor layer 40, the first metal layer 50 and the first photoresist layer 60 are sequentially deposited on the surface of the gate insulating layer 30, and the layout areas of the three layers may be the same. The channel region 41 for forming the channel may be marked corresponding to the position of the gate electrode 20 in advance when the semiconductor layer 40 is deposited, thereby facilitating the subsequent placement of the reticle 200.
Referring to fig. 5, step S3: the mask 200 is disposed above the first photoresist layer 60, and the first photoresist layer 60 is exposed and developed.
Here, the mask 200 may be disposed above the first photoresist layer 60 such that the first exposure region 201 corresponds to the channel region 41 of the semiconductor layer 40. When the first photoresist layer 60 is a positive photoresist, the first photoresist layer 60 corresponding to the transparent region can be changed in properties by exposure to light, and can be washed away after development, while the first photoresist layer 60 corresponding to the opaque region can be left. According to this characteristic, the first exposure region 201 of the mask 200 corresponding to the channel region 41 is set as a semi-transparent region, and after exposure and development, the first photoresist layer 60 corresponding to the first exposure region 201 can be partially washed away and partially left, so that the size loss of the channel region 41 can be reduced in the subsequent etching process. The second exposure region 203 corresponding to the source 51 and the third exposure region 205 corresponding to the drain 53 are required to be opaque regions, so that the corresponding first photoresist layer 60 can be left. The fifth exposed region 209 is a fully transparent region, so that the first photoresist layer 60 in the fifth exposed region 209 can be washed away by development after receiving light. Meanwhile, in order to also protect the outer peripheral dimension of the drain electrode 53, the fourth exposure region 207 is also set as a semi-transparent region, so that after exposure and development, the first photoresist layer 60 corresponding to the remaining portion is on the outer peripheral edge of the first metal layer 50 where the drain electrode 53 is to be formed. The second exposure region 203 and the third exposure region 205 are opaque regions, the fifth exposure region 209 is a fully transparent region, and the first photoresist layer 60 is a positive photoresist.
Of course, in other embodiments, when the first photoresist layer 60 is a negative photoresist, the second exposure region 203 and the third exposure region 205 are transparent regions, and the fifth exposure region 209 is an opaque region.
Referring to fig. 6 to 8, step S4: the semiconductor layer 40 and the first metal layer 50 are patterned by using the remaining first photoresist layer 60, and an active layer 43 on the gate insulating layer 30 and spaced source and drain electrodes 51 and 53 on the active layer 43 are formed.
Here, the patterning process needs to go through two etching processes, and the specific steps are as follows:
s41: performing a first etching to remove the first metal layer 50 and the semiconductor layer 40 uncovered by the first photoresist layer 60; here, the portion uncovered by the first photoresist layer 60 is the exposed portion, and when the first metal layer 50 and the semiconductor layer 40 are both formed over the entire pixel unit, the covered area of the mask 200 does not refer to the peripheral area of the fourth exposure region 207, so that the first metal layer 50 and the semiconductor layer 40 located at the periphery of the fourth exposure region 207 can be removed by the etching solution during the first etching.
S42: performing an ashing process to remove the first photoresist layer 60 in the channel region 41 and the first photoresist layer 60 in the fourth exposure region 207; the ashing process is a plasma ashing process selected to remove the first photoresist layer 60 in the channel region 41 and the fourth exposed region 207, i.e., the first photoresist layer 60 left after development.
S43: and performing second etching to remove the first metal layer 50 and a part of the semiconductor layer 40 of the channel region 41 and the first metal layer 50 and the semiconductor layer 40 of the fourth exposure region 207, and forming an active layer 43, and a source electrode 51 and a drain electrode 53 which are in contact with two ends of the active layer 43 and are arranged at intervals. The etching here may be selected from dry etching, which removes the first metal layer 50 corresponding to the first exposed region 201 and partially removes the semiconductor layer 40 corresponding to the first exposed region 201, and simultaneously removes the first metal layer 50 and the semiconductor layer 40 corresponding to the fourth exposed region 207, exposing the outer periphery of the drain electrode 53.
Of course, it is finally necessary to remove the first photoresist layer 60 completely remaining corresponding to the opaque region, so as to form the final active layer 43 on the gate insulating layer 30, and the spaced apart source and drain electrodes 51 and 53 on the active layer 43.
In the manufacturing method of the array substrate according to the technical solution of the present invention, the gate electrode 20 and the gate insulating layer 30 are formed, the semiconductor layer 40, the first metal layer 50 and the first photoresist layer 60 are laid, and a mask 200 is provided, wherein the mask 200 corresponds to a first exposure region 201 of the channel region 41 of the semiconductor layer 40 and is a semi-transparent region, and corresponds to a periphery of the drain electrode 53 to be formed, that is, the fourth exposure region 207 is also set as a semi-transparent region. Thus, during the exposure and development process, a portion of the first photoresist layer 60 remains in the first exposure region 201 and the fourth exposure region 207, and the semiconductor layer 40 and the first metal layer 50 are protected, so that during the patterning process of the semiconductor layer 40 and the first metal layer 50, the size loss of the channel region 41 and the periphery of the drain 53 can be effectively reduced, and therefore, the design size value of the drain does not need to be increased, and the aperture ratio of the pixel is correspondingly increased. Meanwhile, the reduction of the design size of the drain 53 also can reserve more design space for the columnar spacer, thereby avoiding the problem of abnormal manufacturing process caused by undersize of the columnar spacer or reliability caused by the columnar spacer, avoiding the extension of the columnar spacer to the direction of the pixel, and further improving the aperture opening ratio of the pixel.
Referring to fig. 9 and 10, in an embodiment of the present invention, after the step S4 of patterning the semiconductor layer 40 and the first metal layer 50 by using the remaining first photoresist layer 60 to form the active layer 43 on the gate insulating layer 30 and the spaced source and drain electrodes 51 and 53 on the active layer 43, the method further includes:
s5: depositing a second photoresist layer on the gate insulating layer 30 to form a pillar spacer 70;
s6: the second photoresist layer is patterned to form a pillar spacer 70 spaced apart from the drain electrode 53.
In this embodiment, after the thin film transistor is formed, a passivation layer is further deposited on the source electrode 51, the drain electrode 53 and the gate insulating layer 30, and the passivation layer is patterned by a photomask process to form a via hole penetrating through the passivation layer, wherein the via hole can expose a portion of the drain electrode 53; then, a transparent conductive layer is formed on the passivation layer, and the transparent conductive layer is patterned by a photo-masking process to form a pixel electrode having a specific shape, which is electrically contacted with the drain electrode 53 through the via hole, thereby providing a capacitance for liquid crystal movement to the display region corresponding to the display region of the pixel unit. Here, the material of the passivation layer may be a combination of one or more of silicon oxide and silicon nitride. The material of the transparent conductive layer is Indium Tin Oxide (ITO).
Meanwhile, in order to improve the structural stability of the display panel, a columnar spacer 70 is disposed around the thin film transistor, the material of the columnar spacer 70 is photoresist, a second photoresist layer to be formed into the columnar spacer 70 is deposited on the gate insulating layer 30, and the second photoresist layer is patterned to form the columnar spacer 70 supporting the array substrate 100 and the color filter substrate 10. Compared with the pixel electrode, the column spacer 70 is also located in the non-display area, parallel to the thin film transistor, and at a constant interval with the thin film transistor, because the design size of the drain 53 in the thin film transistor can be reduced, that is, the lateral size is reduced, the size of the column spacer 70 in the direction of the interval with the thin film transistor can be increased, in order to ensure the design proportion of the column spacer 70, the size of the column spacer 70 in the direction toward the pixel electrode can be reduced, thereby avoiding the process abnormality caused by the column spacer 70 being too small, and improving the product reliability. Meanwhile, occupation of a pixel display area is reduced, the aperture opening ratio can be further improved, and the display effect is improved.
Example three:
referring to fig. 11, the present invention further provides a display panel 300, where the display panel 300 includes a color film substrate 400, an array substrate 100 and a liquid crystal layer 500, the color film substrate 400 and the array substrate 300 are arranged in a box-to-box manner, and the array substrate 100 is prepared by using the manufacturing method of the array substrate according to any of the above embodiments. Since the display panel 300 includes all technical solutions of all the embodiments, at least all the advantages brought by the technical solutions of the embodiments are provided, and are not described in detail herein.
Referring to fig. 7 and 8, the array substrate 100 includes a substrate 10, and a gate 20, an active layer 43, a drain 53, and a source 51 sequentially disposed on the substrate 10, and both the channel region 41 and the drain 53 of the semiconductor layer 40 are protected by the semi-transparent region of the mask 200, so that the size loss of the two is reduced, the accuracy of the design size is improved, a larger display area is reserved, the aperture ratio of the array substrate 100 is improved, and the display effect of the display panel is improved.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. The utility model provides a mask for preparation array substrate, array substrate includes thin film transistor, thin film transistor includes grid, source electrode and the drain electrode that the interval set up, be formed with the channel region between source electrode and the drain electrode, its characterized in that, the mask includes:
the device comprises a first exposure area corresponding to the channel area, a second exposure area located on one side of the first exposure area and used for forming a source electrode, a third exposure area located on the other side opposite to the first exposure area and used for forming a drain electrode, and a fourth exposure area located on one side of the third exposure area, which is far away from the first exposure area, wherein the first exposure area and the fourth exposure area are semi-transparent areas.
2. The reticle of claim 1, wherein the fourth exposure field has a width in a range of 1 to 2 μ ι η;
and/or the width range of the first exposure area is 3-5 mu m.
3. The reticle of claim 1, further comprising a fifth exposure area disposed on a side of the fourth exposure area facing away from the third exposure area.
4. The reticle of claim 1, wherein the first exposure region and the fourth exposure region have the same optical transmittance;
and/or the fourth exposure area and the third exposure area are arranged without gaps.
5. The mask of claim 1, wherein the third exposure area and the fourth exposure area are both U-shaped, and the lengths of two opposite edges of the fourth exposure area and the third exposure area are consistent.
6. A method for fabricating an array substrate using the mask as claimed in any one of claims 1 to 5, the method comprising the steps of:
providing a substrate, and sequentially forming a grid electrode and a grid electrode insulating layer on the substrate from bottom to top;
depositing a semiconductor layer, a first metal layer and a first light resistance layer on the grid electrode insulating layer in sequence, wherein a channel region is arranged at the position of the semiconductor layer corresponding to the grid electrode;
arranging the mask above the first photoresist layer, and exposing and developing the first photoresist layer;
and patterning the semiconductor layer and the first metal layer by using the residual first photoresist layer to form an active layer on the gate insulating layer and source and drain electrodes arranged at intervals on the active layer.
7. The method of claim 6, wherein the second and third exposed regions are opaque regions, the fifth exposed region is a fully transparent region, and the first photoresist layer is made of a positive photoresist.
8. The method for manufacturing the array substrate according to claim 6, wherein the step of patterning the semiconductor layer and the first metal layer by using the remaining first photoresist layer to form an active layer on the gate insulating layer and spaced source and drain electrodes on the active layer comprises:
carrying out first etching to remove the first metal layer and the semiconductor layer which are not covered by the first photoresist layer;
performing an ashing process to remove the first photoresist layer of the channel region and the first photoresist layer of the fourth exposure region;
and performing second etching to remove the first metal layer and part of the semiconductor layer in the channel region and the first metal layer and the semiconductor layer in the fourth exposure region, and forming an active layer, and a source electrode and a drain electrode which are contacted with two ends of the active layer and are arranged at intervals.
9. The method for manufacturing the array substrate according to any one of claims 6 or 8, wherein after the step of patterning the semiconductor layer and the first metal layer by using the remaining first photoresist layer to form an active layer on the gate insulating layer and spaced source and drain electrodes on the active layer, the method further comprises:
depositing a second photoresist layer on the gate insulating layer to form a columnar spacer;
and patterning the second photoresist layer to form a columnar spacer arranged at an interval with the drain electrode.
10. A display panel, comprising a color film substrate, an array substrate and a liquid crystal layer, wherein the color film substrate and the array substrate are arranged in a box-to-box manner, and the array substrate is prepared by the method for manufacturing the array substrate according to any one of claims 6 to 9.
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| CN113467179B (en) | 2022-06-03 |
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