CN113421942A - Photodetection transistor, method for manufacturing the same, and photodetection method using the same - Google Patents

Photodetection transistor, method for manufacturing the same, and photodetection method using the same Download PDF

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CN113421942A
CN113421942A CN202110521681.6A CN202110521681A CN113421942A CN 113421942 A CN113421942 A CN 113421942A CN 202110521681 A CN202110521681 A CN 202110521681A CN 113421942 A CN113421942 A CN 113421942A
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transistor
gate electrode
layer
top gate
current
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CN113421942B (en
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张盛东
周晓梁
廖聪维
范昌辉
林清平
严建花
李建桦
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Peking University Shenzhen Graduate School
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    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
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    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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Abstract

The application provides a photoelectric detection transistor, which comprises a substrate, a bottom gate electrode, a bottom gate dielectric layer, an active layer, a top gate dielectric layer and a top gate electrode, wherein the substrate, the bottom gate electrode, the bottom gate dielectric layer, the active layer, the top gate dielectric layer and the top gate electrode are stacked layer by layer; the active layer comprises a semiconductor material with a light memory function, the active layer comprises a channel and source and drain electrodes, and a top gate electrode of the photoelectric detection transistor is made of a transparent conductive material; the source and drain electrodes are obtained by carrying out plasma treatment on the active layer material in the corresponding area. The application also discloses a corresponding method for preparing the photoelectric detection transistor and utilizing the light sensitivity of the photoelectric detection transistor.

Description

Photodetection transistor, method for manufacturing the same, and photodetection method using the same
Technical Field
The present invention relates to a photodetector, and more particularly, to a photodetector having a memory function, a method of manufacturing the same, and a corresponding photodetection method.
Background
Photodetectors and image sensors play an extremely important role in numerous medical electronics, consumer electronics, and military electronics. For example, X-ray images are the gold criterion for diagnosing various diseases such as orthopedics, lung diseases, heart and cerebral vessels and the like; fingerprint identification has become a standard security lock for smart phones; hyperspectral and multispectral camera shooting are important modern military detection means. In these applications, high-sensitivity, high-resolution photodetectors and image sensors for weak optical signals and transient optical signals have been the focus of research.
The existing image sensor technologies are largely classified into imaging technologies based on a Charge Coupled Device (CCD) and a Complementary Metal Oxide (CMOS) transistor, and flat panel detection imaging technologies based on an amorphous silicon (a-Si) Photodiode (PD) and an a-Si transistor (TFT), which are currently mainstream X-ray image sensing technologies. However, the number of photons detected by the photodiode is positively correlated with the area of the photodiode, so that a contradiction exists between high resolution and high sensitivity, and the improvement of the detection resolution is limited. The poor sensitivity of the photodiode also limits its ability to detect weak, transient optical signals.
Photo TFTs are another alternative photo-sensing device compared to photodiodes and are advantageous in some respects. The photoelectric TFT has photoconductive amplification capacity, and is beneficial to improving the sensitivity; meanwhile, the size of the photocurrent is related to the shape of the channel region of the device, thereby being beneficial to the compromise of sensitivity and resolution. Due to these advantages, photo TFTs have been an important research direction for photo sensor devices.
When the device is applied to ultra-low dose X-ray detection, ultra-weak light detection in military equipment and the like, the detection capability of the device depends on the sensitivity of the light sensing device and the level of dark-state current of the light sensing device. By utilizing the optical memory effect, the optical sensing device can continuously maintain the optical response characteristic after the optical signal disappears, so that the optical pulse width or the light intensity is equivalently increased, and the detection of ultrashort pulse light or extremely weak light is realized. However, the optical memory effect may have an additive superposition effect, resulting in a superposition of sensitivities. Therefore, if the optical memory information cannot be erased or reset effectively after the detection is finished, the optical sensing device cannot complete continuous and stable detection.
Disclosure of Invention
Aiming at the problems in the prior art, the application provides a photoelectric detection transistor which comprises a substrate, a bottom gate electrode, a bottom gate dielectric layer, an active layer, a top gate dielectric layer and a top gate electrode which are stacked layer by layer; the active layer comprises a semiconductor material with a light memory function, the active layer comprises a channel and source and drain electrodes, and a top gate electrode of the photoelectric detection transistor is made of a transparent conductive material; the source and drain electrodes are obtained by carrying out plasma treatment on the active layer material in the corresponding area.
Particularly, in the integration stage, the voltages of the bottom gate electrode and the top gate electrode of the photoelectric detection transistor are different, the detection transistor is in an off-state working area, and the channel current of the detection transistor is far larger than the dark-state current; the integration phase comprises an exposure photon phase and a subsequent optical memory maintenance sub-phase; the dark state current is the current in the channel when the photodetection transistor is operating in the off state operating region before the exposure sub-phase.
In particular, the voltages of the bottom gate electrode and the top gate electrode of the photo-detection transistor are the same during the reading phase after the end of the integration phase and before the reading phase begins, so that the photo-detection transistor is in the off-state working region and the channel current thereof is substantially equal to the dark-state current.
In particular, during the reset phase, the voltages of the bottom gate electrode and the top gate electrode of the photo-detection transistor are such that the detection transistor is in the on-state operating region.
In particular, the semiconductor material with the optical memory function comprises a metal oxide semiconductor.
In particular, the photodetection transistor further comprises a passivation layer at least on the top gate electrode, and a scintillator located above the passivation layer and the source-drain electrode layer.
The application also provides a method for preparing the photoelectric detection transistor, which comprises the steps of forming a bottom gate electrode layer on a substrate, and forming the bottom gate electrode through patterning; forming a first dielectric layer on the substrate and the bottom gate electrode; forming an active layer comprising materials with optical memory function on the first dielectric layer once or in sequence, and forming the active region of the detection transistor through patterning; forming a second dielectric layer on the active region and the first dielectric layer; forming a top gate electrode of a transparent conductive material above the second dielectric layer corresponding to the active region; forming a source-drain region in the active region not covered by the top gate electrode; forming a passivation layer on the top gate electrode, the active region and the first dielectric layer; and forming a through hole and a source drain electrode layer electrically connected with the source drain region on the passivation layer.
In particular, the forming of the source and drain regions in the active region not covered by the top gate electrode includes forming the source and drain regions using argon plasma treatment.
In particular, the method further comprises forming a scintillator layer on the passivation layer and the source drain electrode layer.
The application also provides a method for sensing light by using the double-gate photoelectric detection transistor, wherein the active layer material of the double-gate photoelectric detection transistor comprises a material with a light memory function, the method comprises the steps of applying illumination to the double-gate photoelectric detection transistor in an exposure sub-stage in an integration stage, canceling the illumination in a light memory keeping sub-stage in a subsequent integration stage, respectively applying different electric potentials to a bottom gate electrode and a top gate electrode of the double-gate photoelectric detection transistor in the whole integration stage, enabling the double-gate photoelectric detection transistor to be in an off-state working area, enabling the channel current of the double-gate photoelectric detection transistor to be far larger than the dark-state current, and enabling the dark-state current to be the current in the channel of the detection transistor in the off-state working area before the exposure sub-stage; and applying the same voltage to the bottom gate electrode and the top gate electrode of the double-gate detection transistor in a reading stage after the integration stage is finished and before the reading stage is started, so that the double-gate photoelectric detection transistor is in an off-state working area and the channel current of the double-gate photoelectric detection transistor is basically equal to the dark-state current.
In particular, the voltage applied to the top gate electrode of the dual gate photodetection transistor is higher than the voltage applied to the bottom gate electrode of the dual gate photodetection transistor during the entire integration phase.
In particular, the method further comprises applying a voltage to a bottom gate electrode and a top gate electrode of the dual-gate photodetection transistor during a reset phase to place the dual-gate photodetection transistor in an on-state operating region.
The present application further provides a photodetector comprising a scan control circuit and a readout circuit, and a pixel array coupled thereto comprising a photodetector transistor as described in any of the preceding.
In the application, the TFT transistor with the double-gate structure is used as a switching TFT transistor and a detection TFT transistor in a pixel circuit of the detector, so that the pixel of the detector has higher stability, and the reliability and the service life of the detector are improved.
In the present application, the detection transistor made of the material with the optical memory function has very low dark state current, which is beneficial to obtaining low noise current of the detection panel. The mobility of the detection transistor using a material having a light memory function as an active layer is higher than that of a-Si: the H TFT is higher by more than one order of magnitude, and the driving capability of the double-grid TFT transistor is stronger. The switching transistor using the material with the optical memory function as the active layer has stronger current driving capability, and is beneficial to realizing high resolution and high detection frame frequency.
In the application, the double-gate detection transistor is used as a photosensitive element, and the two gates are respectively and independently controlled, so that the photoresponse characteristic of the detection transistor can be improved to the greatest extent, and the preparation of a detector with high sensitivity and high signal-to-noise ratio is facilitated. In addition, by applying reset signals to the two grids, the influence of illumination on the characteristics of the detection transistor during detection can be better eliminated, the characteristics of the device are reset to an initial state, and the long-term stable work of the detection transistor is ensured.
In the application, the detection transistor is firstly returned to the turn-off working area after the integration stage, and the reset operation is carried out after the reading operation is finished, so that the interference to the storage integration unit is avoided, and the detection accuracy is improved.
By adopting the manufacturing method introduced in the application, the switching TFT transistor and the detecting TFT transistor can be simultaneously prepared, and the problems of the traditional a-Si: the high cost of both the switching TFT and the photodiode in the H-detection panel is a problem due to the need for step-by-step fabrication.
Drawings
Embodiments of the present application will be described in further detail below with reference to the attached drawing figures, wherein:
FIG. 1 is a schematic diagram of an operation mode of a probe transistor with an optical memory function;
FIG. 2 is a schematic diagram of a conventional single-gate detection transistor and the dual-gate detection transistor shown in the present application;
FIG. 3a is a graph comparing the characteristics of a single-gate detection transistor reset without illumination and after illumination;
fig. 3b is a graph comparing the characteristics of the dual-gate detection transistor after being reset without light and after being illuminated.
FIG. 4 is a diagram illustrating the photosensitive characteristics of a dual gate photo-detection transistor according to one embodiment of the present application;
FIG. 5 is a diagram illustrating the current of a dual gate detection transistor in a dark state as a function of the top gate voltage according to one embodiment of the present application;
FIG. 6 is a graph illustrating current versus voltage for a dual gate sense transistor according to one embodiment of the present application;
FIG. 7 is a timing diagram and corresponding characteristic graph of the operation of a dual gate sense transistor according to one embodiment of the present application;
FIG. 8a is a schematic diagram of a photodetector pixel circuit according to an embodiment of the present application;
fig. 8b is a timing diagram illustrating the operation of the pixel circuit of the photo-detector of fig. 8 a.
FIGS. 9a-i are partial schematic flow diagrams illustrating fabrication of a photodetector according to one embodiment of the present application;
10a-g are partial schematic views of a photodetector formed in accordance with another embodiment of the present application;
FIG. 11 illustrates a partial schematic view of a photodetector formed in accordance with yet another embodiment of the present application;
12a-c are partial schematic diagrams illustrating formation of a photodetector including a capacitor according to various embodiments of the present application; and
FIG. 13 is a schematic view of a photodetector according to one embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The transistors in this application may be bipolar transistors or field effect transistors. The transistor comprises a control electrode, a first electrode and a second electrode, wherein the first electrode or the second electrode is coupled to a control metal layer, the first electrode and the second electrode are coupled to an active layer with an optical memory function, and a dielectric layer is arranged between the control metal layer and a semiconductor layer. The detection transistor has an active layer with an optical memory function, and the conductivity of the active layer is modulated by the input light to change. When the transistor is a bipolar transistor, the control electrode refers to a base electrode of the bipolar transistor, the first electrode refers to a collector electrode or an emitter electrode of the bipolar transistor, and the corresponding second electrode refers to the emitter electrode or the collector electrode of the bipolar transistor; when the transistor is a field effect transistor, the control electrode refers to a gate electrode of the field effect transistor, the first electrode may be a drain electrode or a source electrode of the field effect transistor, and the corresponding second electrode may be a source electrode or a drain electrode of the field effect transistor. In an N-type transistor, the voltage of the drain should be greater than or equal to the voltage of the source, so the position of the source and the drain will vary with the bias state of the transistor. Since a transistor used in a display is generally a Thin Film Transistor (TFT), the embodiment of the present application does not take a MOS thin film transistor as an example for description, and a drain and a source of the transistor in the embodiment of the present application may vary according to a bias state of the transistor.
The application proposes that the pixel circuit of the photodetector is based on a photosensitive unit with a light memory function, such as a photodetector transistor, to improve the imaging quality under the condition of transient and low-dose light input. The optical memory function means that in the exposure stage, the photosensitive unit receives input light and generates photo-generated current; after the exposure is finished, the photosensitive unit still keeps the photo-generated current for a preset time period even if the incident light is removed.
Studies have shown that materials having an optical memory function and being capable of serving as an active layer or a photosensitive functional layer include metal oxide semiconductors among inorganic semiconductors (for example, indium zinc oxide IZO has a high photoelectric response intensity and a good optical memory function due to a narrow forbidden band width and a high oxygen vacancy concentration), and some organic semiconductors and the like. Specifically, under the action of external light, the photosensitive unit with the optical memory function can generate photo-generated carriers like other types of photosensitive units, and further has the conductance or current modulated by input light. But in contrast, photosensitive cells based on such materials have significant optical memory due to lattice relaxation processes. For example, it takes an extremely long time for recombination of photogenerated carriers in a metal oxide semiconductor detection transistor to disappear, and thus the light generation current can be maintained for a long time in such a light sensing unit. For another example, in a reverse biased mos photodiode, the photo current can last for more than several hours, which is far longer than the time required for photo readout detection. Under the action of light, the resistance of the metal oxide semiconductor photosensitive resistor changes and the metal oxide semiconductor photosensitive resistor has the capability of continuously keeping the resistance state.
In the scheme in the application, the optical memory property of a metal oxide semiconductor or an organic semiconductor material is utilized to enhance the photoelectric conversion capability of the photosensitive unit and improve the signal-to-noise ratio and the sensitivity of the photoelectric detector. In the application that the incident photoelectric signal is weak or the irradiation time is short, for example, in the X-ray medical imaging equipment, the optical memory characteristic of the metal oxide semiconductor photosensitive unit is utilized, so that the X-ray exposure time is reduced, the damage to the human body is avoided, and meanwhile, a clear image can be ensured to be obtained.
FIG. 1 is a schematic diagram of an operation mode of a photo-detection transistor with an optical memory function. In conventional silicon-based TFT processes, transistors are rarely used as photosensitive elements. This is because the active layer of the TFT is thin and thus the effect of the photoresponse is not good. It is common to employ a photodiode as a photosensitive element, and an active layer of the photodiode is not formed together with a switching TFT but is formed by a separate process to ensure that a sufficiently thick active layer can be formed exclusively for the photodiode.
However, after a material having an optical memory function is used as the active layer, the optical response characteristics of the photodetection transistor are not affected even if the active layer is thin due to the special property of the optical memory function.
As shown in fig. 1, in the dark state, the output current of the detecting transistor is the dark-state current Idk; upon irradiation with incident light, the output current of the detection transistor rises to Iph 0. When the incident light stops irradiating, the output current of the detection transistor is Iph1, which is reduced compared with Iph0, but the reduction amplitude is limited, and basically, the photo-generated current is considered to be kept unchanged before and after the exposure period. The reduction of Iph1 compared to Iph0, and the reduction of Iph1 over time, are dependent on the optical memory of the device. Thus, the phases of integrating the photo-generated current can be considered to include an illumination or exposure sub-phase and an optical memory retention sub-phase.
Fig. 2 is a schematic diagram of a conventional single-gate detection transistor and the double-gate detection transistor shown in the present application. For the detection transistor, the off-state operating region of the transistor is always in the integration phase. Because there is no photo-generated current in the detection transistor in the dark state, the off-state leakage current is relatively small; under the condition of light irradiation, the off-state current of the detection transistor is obviously increased due to the photo-generated current, so that the light signal is detected by utilizing the difference before and after the light irradiation.
For the detection transistor, in the exposure sub-stage in the integration stage, the adjustment of the light detection sensitivity can be realized by controlling the control electrode, namely the gate voltage (Vg), and in the optical memory retention sub-stage after the illumination is finished, the leakage current can be amplified by adjusting the gate voltage. The gate voltage Vg is therefore set at a level that places the detection transistor in the off-state operating region throughout the integration phase. The adjustment of the sensitivity of the detection transistor to the light detection and the amplification effect of the photo-generated current through Vg are directly related to the control capability of the gate to the channel layer. The single-gate detection transistor is limited by the limited control capability of the single-gate device on the active layer, and the light detection sensitivity adjustment and the photo-generated current amplification capability of the single-gate detection transistor are not ideal.
After the integration phase is finished, due to the optical memory effect, the detection transistor needs to be reset before the detection of a new frame is started. For the photo-detection transistor, the reset is to adjust the gate voltage Vg to exceed the threshold voltage of the detection transistor, turning on the detection transistor, thereby allowing ionized oxygen vacancies to recombine with electrons. Specifically, due to the existence of the optical memory effect, the conductive carriers generated by photoexcitation in the channel of the photo-detection transistor and the charged particles or carriers not participating in the conduction (the heterogeneous charges of the conductive carriers, such as ionized oxygen vacancies) cannot be rapidly recombined to return to the initial dark state, the former causes the off-state current not to return to the dark state, and the latter introduces charges in the channel to cause the threshold voltage Vth of the detection transistor to become negative. Applying a positive pulse voltage Vg (for example, Vg is 10V, and the pulse time is 10ns) to the gate of the photo-detection transistor can accelerate the recombination speed of photo-generated charges, thereby achieving the effect of eliminating the optical memory and completing the reset. But the reset effect also depends on the gate's ability to control the channel layer. After a positive voltage is applied to the gate of the single-gate photodetection transistor, the off-state leakage current can be restored to the initial dark state level, but the threshold voltage Vth of the single-gate photodetection transistor cannot be completely restored.
In contrast, the double-gate photo-detection transistor can utilize the coupling effect between two gates to more effectively control the channel layer, thereby more effectively realizing the adjustment of the photosensitivity and the photo-generated current amplification of the double-gate photo-detection transistor by controlling the voltage (Vtg, Vbg) of the two gates, and better resetting the double-gate photo-detection transistor after the integration stage is finished. According to one embodiment, in the embodiment of the present application, by applying different voltages to the top gate and the bottom gate (or the first and the second control electrodes) of the dual-gate photo-detection transistor, respectively, it is realized that better photo-response sensitivity and photo-generated current amplification effect can be achieved.
In the reset stage after the detection is finished, a positive voltage pulse can be simultaneously applied to the two grids of the double-grid light detection transistor to enable the transistor to be conducted, so that the threshold voltage and the off-state dark-state current of the double-grid light detection transistor return to the initial state before the light sensing.
Fig. 3a is a graph comparing the characteristics of a single-gate detection transistor reset without illumination and after illumination. Fig. 3b is a graph comparing the characteristics of the dual-gate detection transistor after being reset without light and after being illuminated. In these two figures, the transistor has a channel width W of 100 μm, a length L of 20 μm, an illumination wavelength of 350nm, and an illumination power of 500 μ W/cm2. The so-called erase in the figure is also reset.
As can be seen from the figure, after applying a gate voltage pulse with Vg of +10V and a time of 1s to the gate, the single-gate detection transistor cannot completely erase the effect caused by the optical memory effect, so that the threshold voltage has a negative drift. In the dual-gate detection transistor, after a gate voltage pulse with a positive voltage, for example, a voltage of Vtg-Vbg +10V for 1s, is simultaneously applied to the two gates, the device characteristics can be fully restored to the initial characteristics, and the optical memory effect is effectively erased.
FIG. 4 is a diagram illustrating the photosensitive characteristics of a dual gate photo-detection transistor according to an embodiment of the present application. In the figure, the channel width W of the photodetector transistor is 100 μm, the length L is 20 μm, the wavelength of light is 350nm, and the power of light is 500. mu.W/cm2The top gate voltage is always 0V, the bottom gate voltage is Vgs (i.e., BG mode) on the horizontal axis, and the detection transistor current Ids on the vertical axis. It can be seen that in the off-state working region of the double-gate photodetector, the difference between the leakage current in the absence of illumination and the leakage current after the illumination is at least two orders of magnitude.
Fig. 5 is a diagram illustrating the current of a dual gate photodetector transistor in a dark state as a function of the top gate voltage according to an embodiment of the present application. The influence of the voltage Vtg applied to the top gate and the voltage Vbg applied to the bottom gate on the response characteristics of the double-gate detection transistor having the same properties and the light signal having the same properties as those described above is shown in the figure. When the device is operated in a bottom gate mode (BG mode), that is, the top gate is an auxiliary electrode and is fixed in voltage, and the bottom gate voltage is scanned, it can be seen that the photoresponse characteristic can be significantly changed by changing the fixed voltage Vtg of the top gate to-10V, 0V, 10V.
It can be seen that the level of the dark state leakage current is substantially the same when the transistor is in the off state, regardless of the change in the voltages of the top and bottom gates. However, as the top gate voltage is gradually increased, the threshold voltage of the double gate transistor is also gradually decreased, and a negative value may occur.
FIG. 6 is a graph illustrating current versus voltage for a dual gate sense transistor according to one embodiment of the present application. Wherein the transistor properties and applied illumination signal properties targeted are the same as before. As can be seen from the figure, when the dual-gate photo-detection transistor is in the off-state operating region, the higher the top gate voltage Vtg is, the larger the off-state leakage current generated by illumination is, i.e., the more sensitive the response to illumination is. This is because the material with optical memory function has direct correlation between the size of the light induced current (or sensitivity) and the separation state of the photogenerated carriers (e.g. electrons) and particles (e.g. ionized oxygen vacancies) that do not participate in the conduction in the channel after the material is irradiated with light. The vertical electric field induced in the channel by the positive top gate voltage facilitates separation of the two. The double-gate detection transistor can more effectively control the distribution and the size of an electric field in the whole active layer through the coupling control action of the two gates on the channel layer. In an embodiment, as the top gate voltage increases, the magnitude of the longitudinal electric field in the channel increases, which is more beneficial to the separation of two kinds of particles, so that a conductive layer with higher carrier (electron) concentration is formed in the active layer close to the top gate dielectric side. Thus, the higher the top gate voltage, the greater the photo-generated current.
Of course, according to other embodiments, the bottom gate voltage may be set higher than the top gate voltage, and the effect of the detection sensitivity may be improved as well. The roles of the two gates in a double gate device are interchangeable with each other.
In order to improve the sensitivity in the integration stage, it is sufficient to ensure that the voltages of the two gates are different and that the detection transistor is not turned on and still in the off-state operating region. According to one embodiment, a positive voltage may be applied to the top gate and a negative voltage may be applied to the bottom gate to obtain as high photoresponse sensitivity as possible.
Fig. 7 shows a timing diagram and corresponding characteristic curves of the operation of a dual gate sense transistor according to an embodiment of the present application. In this embodiment, the size of the probe transistor may be, for example, 100 microns, and 15 microns. The drain voltage Vd may be always set to, for example, 10V, and the source voltage Vs may be always set to, for example, 0V.
In the dark state, both gate electrode voltages Vtg and Vbg may be, for example, -20V, and the detection transistor is in the off state, where the off-state leakage current may be at a level of, for example, 10-11A。
The integration phase may include an illumination or exposure sub-phase and a photo-memory retention sub-phase after illumination. During the exposure sub-phase, a positive voltage Vtg, e.g., 10V, may be applied to the top gate of the dual gate detection transistor to facilitate and amplify the generation of the photo-generated current. At this time, the detection transistor is still in an off state, but the off-state leakage current can reach 10 under the influence of light irradiation-4A or higher.
In the photomemory holding sub-phase after the end of the light irradiation, the top gate voltage Vtg may be continuously held at the positive voltage, for example, 10V for a period of time, thereby maintaining substantially the same photomemory current as the photocurrent using the photomemory effect. At this point, the detection transistor is still in the off state and the leakage current is substantially the same as the photo-generated current level.
Subsequently, both the top-gate Vtg and the bottom-gate voltage Vbg of the dual-gate detection transistor may be adjusted to a negative voltage, e.g., -20V, thereby temporarily depleting and driving the photogenerated carriers, i.e., electrons, to the source and drain terminals. At this time, the sense transistor is still in the off state, but the off-state leakage current is restored to the level of the dark-state leakage current in the case where the above-described top-gate and bottom-gate voltages Vtg and Vbg are the same negative voltage. However, it is noted that the sense transistor is not reset or the optical memory effect is not erased.
When the detection transistor with the optical memory function is reset, the detection transistor needs to be switched from an off state to an on state, so that ionized oxygen vacancies and electrons generated by illumination can be recombined, and the function of erasing photo-generated current is achieved. For example, as shown in fig. 6, the detection transistor is always in the off-state operation region on the left side of the curve, and the detection transistor is in the on-state operation region on the right side of the curve. By off-state operating region is meant that by setting the voltages of the two gates, the (leakage) current in the channel of the detection transistor, i.e. the dark-state current, is very small in the absence of light or exposure to light, although the level of this leakage current is dependent on specific properties of the device, such as the active layer material, the device dimensions, etc. The transistor shown in FIG. 6 has a dark current of 10-11And A is left and right. During the integration phase, the detection transistor is still in the off-state working region, and the current in the channel can be much larger than the dark-state current and can be at least 10 times higher than the dark-state current2Or more, e.g. 10 during the integration phase as shown in fig. 7-5And A is left and right. In the reset stage, the detection transistor works in an on-state working area by setting the voltages of the two grid electrodes under the condition of no illumination or exposure, and the current in the channel of the detection transistor in the on-state working area is far larger than that of the dark-state currentHorizontal, can be at least 10 higher than the dark state current2Or more, as shown in FIG. 6, the current in the channel of the sense transistor in the on-state operating region may reach 10-3And A is left and right. Thus, what is called much greater or much less than at least 10 difference in the present application2An order of magnitude.
Fig. 8a is a schematic diagram of a pixel circuit of a light detector according to an embodiment of the present application, and fig. 8b is a timing diagram illustrating an operation of the pixel circuit of the light detector in fig. 8 a. As shown in fig. 8a, the pixel circuit may include a probe transistor T1, a memory cell, and a switching transistor T2, wherein T1 and T2 may both be double gate transistors, but may shield the T2 transistor from light during manufacturing.
As shown, a first pole of the photo-detection transistor T1 may be configured to receive a high level, e.g., Vdd, and a second pole thereof may be coupled to a storage element, e.g., a capacitor CpxUpper plate of (1), capacitor CpxMay be configured to receive a reference potential Vref or a low level Vss. The first gate/top gate and the second gate/bottom gate of T1 are configured to receive two control voltages Vtg-1 and Vbg-1, respectively. A first pole of the switching transistor T2 may be coupled to a second pole of T1 or to a capacitor CpxA second pole of the switching transistor T2 as an output of the detector pixel for reading the detection signal, and a first and a second control pole of the switching transistor T2 coupled together configured to receive Vtg-2 or Vbg-2.
In the dark state, as shown in fig. 8b, there is a dark current in the detection transistor off, which is of very low order of magnitude. In the dark state, the detection transistor T1 and the switch transistor T2 are both off, and the respective gate voltages (e.g., Vtg-1, Vbg-1, Vtg-2, Vbg-2) are negative, e.g., -20V.
In the illumination sub-phase of the integration phase, the detection transistor T1 generates photo-generated current under the illumination of light and simultaneously provides C with the photo-generated currentpxCharging, the magnitude of the photo-generated current is much larger than the dark current in T1. The voltage of the top gate of the detection transistor T1 at this stage is a positive voltage, for example, 10V.
After the illumination sub-phase is over, the top gate voltage Vtg-1 of the detection transistor T1 is kept at a positive voltage, e.g., 10V. In the optical memory retention sub-phase of the integration phase, the T1 transistor is under the action of the optical memory effect, so that Ids in the transistor is still kept at the level which is basically the same as the photo-generated current.
After a sufficiently long integration period, the top gate voltage Vtg-1 of the probe transistor T1 returns to a negative value, e.g., -20V, thereby returning the off-state leakage current of the probe transistor T1 to a dark state level, but without resetting T1 to eliminate the photo memory effect. This is so because, in the circuit shown in fig. 8a, if the sense transistor T1 is reset immediately after the end of the integration phase, a relatively large current will flow through the sense transistor T1, which in turn will give the capacitor CpxCharging and thus the accuracy of the readout signal of the circuit is affected.
During the readout phase, the top and bottom gate voltages Vtg-2 and Vbg-2 of the switching transistor T2 are both set to a positive voltage such that T2 is turned on, e.g., 10V, thereby reading the detected signal out of the pixel circuit.
After the readout phase is completed, the top-gate and bottom-gate voltages Vtg-1 and Vbg-1 of the detection transistor T1 are both set to a positive voltage so that T1 is turned on, thereby erasing the optical memory effect and realizing the reset operation for T1. Although a relatively large current flows through the transistor T1 in this stage, the accuracy of detection is not adversely affected since the read operation is completed.
FIGS. 9a-i are schematic flow diagrams illustrating portions of a method for fabricating a photodetector according to an embodiment of the present application. Which includes photo-transistors or detection transistors for detecting or capturing optical signals, and switching transistors or non-detection transistors for forming other circuits of the detector array. A basic principle is that it is desirable that the photo-transistor or the detection transistor has a relatively good photo-response, while at the same time it is undesirable that the current in the switching transistor is influenced by the optical signal.
As shown in fig. 9a, a bottom gate electrode layer 902 may first be formed on a substrate 901. According to one embodiment, the light illumination may come from the top-gate direction, in which case the bottom gate electrode layer 902 may be an opaque material. According to other embodiments, the substrate 901 may be made of a transparent material, the light irradiation may be from the bottom gate direction, the bottom gate electrode materials of the detection transistor and the switching transistor are made of different materials, the bottom gate electrode of the detection transistor may be made of a transparent material, and the bottom gate electrode of the switching transistor may be made of an opaque material.
As shown in fig. 9b, the bottom gate electrode layer 902 may be patterned to form a bottom gate electrode 9021 of the probe transistor and a bottom gate electrode 9022 of the switch transistor, respectively.
As shown in fig. 9c, a bottom gate dielectric layer 903 is formed on the substrate 901, the bottom gate electrode 9021 of the probe transistor, and the bottom gate electrode 9022 of the switch transistor.
As shown in fig. 9d, an active layer 904 of a material having a light memory function is formed on the bottom gate dielectric layer and patterned to form a probe transistor active region 9041 and a switch transistor active region 9042 which are separated from each other. According to other embodiments, different active layers having optical memory function may be formed for the detection transistor and the switching transistor, respectively, for example, an active layer material with a smaller photo-generated current may be used as the switching transistor, and an active layer material with a larger photo-generated current may be used as the detection transistor. After the respective active regions are formed, the subsequent steps are also performed collectively.
As shown in fig. 9e, a top gate dielectric layer 905 is formed over the probing transistor active region 9041 and the switching transistor active region 9042 and the bottom gate dielectric layer 903.
As shown in fig. 9f, a probe transistor top gate electrode 906 and a switch transistor top gate electrode 907 are formed on top gate dielectric layer 905, over probe transistor active region 9041 and over switch transistor active region 9042, respectively. According to one embodiment, the probing transistor top gate electrode 906 may be a transparent material and the switching transistor top gate electrode 907 may be an opaque material.
As shown in fig. 9g, the top gate dielectric layer 905 is patterned using the top gate electrodes 906 and 907 as a mask to form separate top gate dielectric layers 9051 and 9052 to expose the active layers 9041 and 9042.
According to one embodiment, the resistance of the active layer not covered by the gate electrode may be reduced by using a plasma (e.g., Ar plasma) bombardment treatment, a hydrogen (H) doping treatment, a metal reaction treatment, or the like, so as to form conductive source and drain regions, and the top gate electrode and the top gate dielectric protect the channel region during the above treatment for forming the source and drain regions, so as to form sub-aligned source and drain regions.
As shown in fig. 9h, a passivation layer 908 is formed on the top gate electrodes 906 and 907, as well as the active regions 9041 and 9042 and the bottom gate dielectric layer 903, and the passivation layer 908 is patterned to form source-drain electrode layers 909 that are in contact with the source drains of the probe transistor and the switch transistor.
As shown in fig. 9i, a scintillator layer 910 may be formed on the passivation layer 908 and the source-drain electrode layer 909, so that the detection transistor can be used for X-ray detection. Of course the illumination may also come from the bottom-gate direction, the bottom-gate electrode of the switching transistor being opaque, in which case the scintillator layer may then be provided below the substrate.
Figures 10a-10g illustrate partial schematic views of a photodetector formed in accordance with another embodiment of the present application. Most of the steps are similar to those in fig. 9, but a non-self-aligned process may be used when forming the top gate electrodes 1006 and 1007. As shown in fig. 10d, a metal layer 1009 may be formed on the patterned active regions 10042 and 10041 and patterned to form source and drain electrodes of two transistors. As shown in fig. 10e, a top gate dielectric layer 1005 may be formed. As shown in fig. 10f, a top gate electrode 1006 of a detection transistor made of a transparent material may be formed on the top gate dielectric layer 1005. As shown in fig. 10g, a top gate electrode 1007 comprising a non-transparent material may be formed on the top gate dielectric layer.
Figure 11 illustrates a partial schematic view of a photodetector formed in accordance with yet another embodiment of the present application. Most steps are similar to those in fig. 9, but in the same step, the top gate electrodes 11061 and 11062 are formed and both made of a transparent material, and then the top gate electrode 1107 made of a non-transparent material is formed on the top gate electrode 11062 of the switching transistor, so that the active region of the switching transistor is shielded.
12a-c are partial schematic views illustrating fabrication of a photodetector including a capacitor according to one embodiment of the present application. Wherein the part comprises a double-gate switching transistor (which may be a detection transistor or a non-detection switching transistor) and a storage capacitor for forming the detector.
According to one embodiment, as shown in fig. 12a, the bottom gate electrode 12021 of the switch transistor and the metal layer 12023 may be used as the bottom plate of the capacitor, the active layer 12041 may be used as the top plate of the capacitor, and the bottom gate dielectric layer of the dual gate transistor may be used as the dielectric layer of the capacitor.
According to another embodiment, as shown in fig. 12b, the metal 12007 on the same layer as the top gate electrode of the dual-gate transistor may be used as the upper plate of the capacitor, the active layer 12041 may be used to form the lower plate of the capacitor, and the metal 12053 on the same layer as the top gate dielectric layer of the dual-gate transistor may be used as the dielectric layer of the capacitor.
According to yet another embodiment, as shown in fig. 12c, the two parallel connections formed in fig. 12a and 12b form a total capacitor, and the two capacitors can be connected in parallel by connecting 12007 and 12023 with the same potential through a metal interconnection layer 12093.
FIG. 13 is a schematic view of a photodetector according to one embodiment of the present application. As shown, the detector may include at least an array of detector pixels, scan control circuitry, and readout circuitry. Wherein the method described herein may be employed to form both the detector pixel array and other circuit portions. Also, the detector pixel array may comprise one or more double gate photo detection transistors as described earlier in this application.
The light referred to in this application may be visible light, invisible light, or may be other rays, etc.
The above-described embodiments are provided for illustrative purposes only and are not intended to be limiting, and various changes and modifications may be made by those skilled in the art without departing from the scope of the present disclosure, and therefore, all equivalent technical solutions should fall within the scope of the present disclosure.

Claims (13)

1. A photodetection transistor includes
The device comprises a substrate, a bottom gate electrode, a bottom gate dielectric layer, an active layer, a top gate dielectric layer and a top gate electrode which are stacked layer by layer; the active layer comprises a semiconductor material with a light memory function, the active layer comprises a channel and source and drain electrodes, and a top gate electrode of the photoelectric detection transistor is made of a transparent conductive material;
the source and drain electrodes are obtained by carrying out plasma treatment on the active layer material in the corresponding area.
2. The photodetection transistor according to claim 1, wherein during the integration phase, the bottom gate electrode and the top gate electrode of the photodetection transistor are at different voltages and the photodetection transistor is in an off-state operating region and its channel current is much larger than the dark-state current; the integration phase comprises an exposure photon phase and a subsequent optical memory maintenance sub-phase; the dark state current is the current in the channel when the photodetection transistor is operating in the off state operating region before the exposure sub-phase.
3. The photodetector transistor of claim 1, wherein the voltages of the bottom gate electrode and the top gate electrode of the photodetector transistor are the same during a read phase after the end of the integration phase and before the start of the read phase, such that the photodetector transistor is in an off-state operating region and its channel current is substantially equal to the dark-state current.
4. The photodetection transistor according to claim 1, wherein during a reset phase, voltages of a bottom gate electrode and a top gate electrode of the photodetection transistor cause the detection transistor to be in an on-state operating region.
5. The photodetection transistor according to claim 1, wherein the semiconductor material having an optical memory function comprises a metal oxide semiconductor.
6. The photodetector transistor of claim 1, further comprising a passivation layer on at least the top gate electrode, and a scintillator over the passivation layer and the source and drain electrode layers.
7. A method of making a photodetecting transistor comprising
Forming a bottom gate electrode layer on the substrate, and forming the bottom gate electrode through patterning;
forming a first dielectric layer on the substrate and the bottom gate electrode;
forming an active layer comprising materials with optical memory function on the first dielectric layer once or in sequence, and forming the active region of the detection transistor through patterning;
forming a second dielectric layer on the active region and the first dielectric layer;
forming a top gate electrode of a transparent conductive material above the second dielectric layer corresponding to the active region;
forming a source-drain region in the active region not covered by the top gate electrode;
forming a passivation layer on the top gate electrode, the active region and the first dielectric layer; and
and forming a through hole and a source drain electrode layer electrically connected with the source drain region on the passivation layer.
8. The method of claim 7, wherein said forming source and drain regions in an active area not covered by a top gate electrode comprises forming said source and drain regions using an argon plasma process.
9. The method of claim 7 or 8, further comprising forming a scintillator layer on the passivation layer and the source drain electrode layer.
10. A method of sensing light using a dual gate photodetector transistor having an active layer material comprising a material with an optical memory function, the method comprising:
applying illumination to the double-gate photodetector transistor in an exposure sub-stage in an integration stage, canceling the illumination in a photoresistance maintaining sub-stage in a subsequent integration stage, respectively applying different electric potentials to a bottom gate electrode and a top gate electrode of the double-gate photodetector transistor in the whole integration stage, and enabling the double-gate photodetector transistor to be in an off-state working area and the channel current of the double-gate photodetector transistor to be far larger than the dark-state current, wherein the dark-state current is the current in the channel of the detection transistor in the off-state working area before the exposure sub-stage; and
and applying the same voltage to the bottom gate electrode and the top gate electrode of the double-gate photoelectric detection transistor in a read stage after the integration stage and before the read stage starts, so that the double-gate photoelectric detection transistor is in an off-state working area and the channel current of the double-gate photoelectric detection transistor is basically equal to the dark-state current.
11. The method of claim 10, wherein a voltage applied to a top gate electrode of the dual gate photodetection transistor is higher than a voltage applied to a bottom gate electrode of the dual gate photodetection transistor throughout an integration phase.
12. The method of claim 10, further comprising
And in the resetting stage, the voltage is applied to the bottom gate electrode and the top gate electrode of the double-gate photoelectric detection transistor, so that the double-gate photoelectric detection transistor is in an on-state working area.
13. A photodetector comprising a scan control circuit and a readout circuit, and coupled thereto a pixel array comprising a photodetector transistor as claimed in any one of claims 1 to 6.
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