CN113363254B - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN113363254B CN113363254B CN202110616464.5A CN202110616464A CN113363254B CN 113363254 B CN113363254 B CN 113363254B CN 202110616464 A CN202110616464 A CN 202110616464A CN 113363254 B CN113363254 B CN 113363254B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 73
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000005468 ion implantation Methods 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000000576 coating method Methods 0.000 claims abstract description 7
- 239000011248 coating agent Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 34
- 230000004888 barrier function Effects 0.000 claims description 27
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 238000002513 implantation Methods 0.000 claims description 14
- KDYFGRWQOYBRFD-UHFFFAOYSA-N Succinic acid Natural products OC(=O)CCC(O)=O KDYFGRWQOYBRFD-UHFFFAOYSA-N 0.000 claims description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 10
- 239000003513 alkali Substances 0.000 claims description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 4
- -1 argon ions Chemical class 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000002791 soaking Methods 0.000 claims 3
- KDYFGRWQOYBRFD-NUQCWPJISA-N butanedioic acid Chemical compound O[14C](=O)CC[14C](O)=O KDYFGRWQOYBRFD-NUQCWPJISA-N 0.000 claims 1
- 238000005192 partition Methods 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 8
- 230000005669 field effect Effects 0.000 description 8
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 239000001384 succinic acid Substances 0.000 description 5
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/7605—Making of isolation regions between components between components manufactured in an active substrate comprising AIII BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
The application provides a semiconductor device and a preparation method thereof, which relate to the technical field of semiconductors, and the method comprises the following steps: an epitaxial structure is formed on a substrate through epitaxial growth, the epitaxial structure comprises an epitaxial layer and a cap layer, a window area is defined by coating a photoresist, exposing and developing to form a patterned photoresist, then the cap layer exposed in the window area is etched, so that the epitaxial layer below the cap layer is exposed in the window area, and then the epitaxial layer exposed in the window area is subjected to ion implantation to form an isolation area, so that the cap layer forms a physical partition at the position of the window area, the problem that leakage current of an active device through the isolation area and other areas is increased due to the fact that the cap layer is of a heavily doped structure after the isolation area is manufactured by the cap layer ion implantation is avoided, meanwhile, the isolation area can be utilized to further insulate and isolate the active device, and leakage current of the active device and other areas is effectively limited.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
The second-generation semiconductor material has better application prospect as a current research hot spot, and a semiconductor device manufactured by using the second-generation semiconductor material has better performance. In semiconductor device applications, isolation regions are fabricated to suppress leakage currents generated in the device in order to improve device performance.
In order to achieve the purposes of surface protection and ohmic contact, the conventional semiconductor device is usually formed with a heavily doped cap layer, and when leakage current is suppressed, an isolation region is formed on the cap layer, but because the cap layer originally belongs to a heavily doped structure, the device can still generate leakage current through the isolation region in use, so that the problem of larger leakage current of the device is caused.
Disclosure of Invention
The application aims to overcome the defects in the prior art and provide a semiconductor device and a preparation method thereof, so as to solve the problem that the current leakage of the conventional semiconductor device is large in use.
In order to achieve the above purpose, the technical scheme adopted by the embodiment of the application is as follows:
In one aspect of the embodiment of the present application, a method for manufacturing a semiconductor device is provided, including: epitaxially growing an epitaxial structure on a substrate, wherein the epitaxial structure comprises an epitaxial layer and a cap layer which are sequentially formed on the substrate; forming a patterned photoresist on the cap layer to define a window region; etching the cap layer in the window area to terminate in the epitaxial layer; and performing ion implantation on the epitaxial layer in the window area to form an isolation region.
Optionally, forming a patterned photoresist on the cap layer to define the window region includes: coating a photoresist on the cap layer, wherein the thickness of the photoresist is 2.3 μm to 2.7 μm; the photoresist is exposed and developed to define a window area, and then baked to form a patterned photoresist.
Optionally, the epitaxial layer comprises a buffer layer, a channel layer and a barrier layer which are sequentially formed, and the cap layer comprises a first n-type doping layer; or, the epitaxial layer comprises a buffer layer, a channel layer and a barrier layer which are sequentially formed, the cap layer comprises a second n-type doped layer and a first n-type doped layer which are sequentially formed, and the doping concentration of the first n-type doped layer is greater than that of the second n-type doped layer.
Optionally, the cap layer includes a second n-type doped layer and a first n-type doped layer formed in sequence, and etching the cap layer in the window region to terminate in the epitaxial layer includes: the first n-type doped layer and the second n-type doped layer are sequentially etched in the window region using citric acid or succinic acid and terminate at the barrier layer.
Optionally, performing ion implantation on the epitaxial layer in the window region to form the isolation region includes: under the conditions that the implantation energy is 190KeV to 250KeV and the implantation dosage is 4E11ion/cm 2 to 1E12ion/cm 2, argon ions are adopted to carry out ion implantation from the surface of the barrier layer to the substrate direction in the window area so as to form isolation areas on the barrier layer, the channel layer and the buffer layer, wherein the depth of the isolation areas is 0.55 mu m to 0.65 mu m.
Optionally, after ion implantation is performed on the epitaxial layer in the window region to form the isolation region, the method further includes: forming source electrodes and drain electrodes which are arranged at intervals on the cap layer; etching the cap layer to expose the epitaxial layer between the source electrode and the drain electrode; a gate is formed on the epitaxial layer exposed between the source and drain to form a first active device.
Optionally, after forming a gate on the epitaxial layer exposed between the source and the drain to form the first active device, the method further includes: and forming a second active device on the cap layer, wherein the first active device is isolated from the second active device by an isolation region.
Optionally, after forming a gate on the epitaxial layer exposed between the source and the drain to form the first active device, the method further includes: etching the cap layer to expose the epitaxial layer; an epitaxial resistor is formed on the epitaxial layer, wherein the epitaxial resistor is isolated from the first active device by an isolation region.
Optionally, after forming a gate on the epitaxial layer exposed between the source and the drain to form the first active device, the method further includes: a passive device is formed on the isolation region.
In another aspect of the embodiments of the present invention, a semiconductor device is provided, which is manufactured by using any one of the above semiconductor device manufacturing methods.
The beneficial effects of the application include:
The application provides a semiconductor device and a preparation method thereof, wherein the method comprises the following steps: an epitaxial structure is formed on a substrate through epitaxial growth, the epitaxial structure comprises an epitaxial layer and a cap layer, a window area is defined by coating a photoresist, exposing and developing to form a patterned photoresist, then the cap layer exposed in the window area is etched, so that the epitaxial layer below the cap layer is exposed in the window area, and then the epitaxial layer exposed in the window area is subjected to ion implantation to form an isolation area, so that the cap layer forms a physical partition at the position of the window area, the problem that leakage current of an active device through the isolation area and other areas is increased due to the fact that the cap layer is of a heavily doped structure after the isolation area is manufactured by the cap layer ion implantation is avoided, meanwhile, the isolation area can be utilized to further insulate and isolate the active device, and leakage current of the active device and other areas is effectively limited.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;
fig. 2 is a schematic diagram of a state of a semiconductor device according to an embodiment of the present application;
FIG. 3 is a schematic diagram showing a second state of a semiconductor device according to an embodiment of the present invention;
FIG. 4 is a third schematic diagram illustrating a state of a semiconductor device according to an embodiment of the present invention;
Fig. 5 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
FIG. 6 is a second schematic diagram of a semiconductor device according to an embodiment of the present invention;
fig. 7 is a third schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
Fig. 8 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;
Fig. 9 is a schematic diagram of a semiconductor device according to an embodiment of the present invention.
Icon: 10-substrate; 20-an epitaxial layer; 21-a buffer layer; 22-a channel layer; a 23-barrier layer; 24-isolation region; 30-cap layer; 31-a second n-type doped layer; 32-a first n-type doped layer; 40-patterning the photoresist; 51-source; 52-drain; 53-gate; 60-a second active device; a 70-epi resistor; 80-passive devices.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. It should be noted that, under the condition of no conflict, the features of the embodiments of the present application may be combined with each other, and the combined embodiments still fall within the protection scope of the present application.
For the purpose of surface protection and ohmic contact, a heavily doped cap layer is usually formed on the existing semiconductor device, and an active device is usually fabricated on the cap layer. In order to isolate the active device to achieve the purpose of inhibiting the leakage current of the active device, an isolation region is usually manufactured on the cap layer around the active device, but because the cap layer belongs to a heavily doped structure, even if the isolation region can reduce the leakage current of the active device, the active device still can generate leakage current with other regions through the isolation region in use, so that the problem of larger leakage current of the active device still exists. The application provides the semiconductor device and the preparation method thereof, so that the active device forms a physical partition on the cap layer, and then the leakage current of the active device is effectively reduced in use.
In one aspect of an embodiment of the present invention, a method for manufacturing a semiconductor device is provided, and the method for manufacturing the semiconductor device will be schematically described with reference to fig. 1:
S100: and epitaxially growing an epitaxial structure on the substrate, wherein the epitaxial structure comprises an epitaxial layer and a cap layer which are sequentially formed on the substrate.
As shown in fig. 2, a substrate 10 is provided, and the substrate 10 may be a substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon carbide, germanium, silicon germanium, gallium arsenide, and the like. An epitaxial structure of a semiconductor device is fabricated on the substrate 10, that is, at least one epitaxial layer 20 and a cap layer 30 are formed on the substrate 10 by epitaxial growth, wherein the epitaxial layer 20 is formed on the surface of the substrate 10 and the cap layer 30 is formed on the surface of the epitaxial layer 20. The epitaxial growth of the epitaxial layer 20 and the cap layer 30 may be performed by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or other processes, which are not limited by the present application, and may be reasonably selected according to practical requirements.
S200: a patterned photoresist is formed over the cap layer to define a window region.
As shown in fig. 2, after the epitaxial layer 20 and the cap layer 30 are formed on the substrate 10 through S010, a photoresist is coated on the surface of the cap layer 30, and the patterned photoresist 40 is formed through processes such as exposure, development, etc., wherein the patterned photoresist 40 has a window region, i.e., a portion of the cap layer 30 located under the patterned photoresist 40 is exposed in the window region. The number and shape of the window regions are not limited in the present application, for example, the patterned photoresist 40 in fig. 2 has a ring-shaped window region, but in other embodiments, two, three, etc. may be provided, and the shape may be square ring, strip, etc.
S300: the cap layer is etched in the window region to terminate in the epitaxial layer.
After a window region is formed on the photoresist, a portion of the cap layer 30 located in the window region is exposed, a portion of the cap layer 30 located around the window region is covered by the patterned photoresist 40, and then the device structure is etched, as shown in fig. 3, in the etching process, the cap layer 30 covered by the patterned photoresist 40 is not affected, but the cap layer 30 located in the window region is gradually etched, and by using the epitaxial layer 20 below the cap layer 30 as a barrier layer, the etching is terminated in the epitaxial layer 20, so that the cap layer 30 in the window region is removed, so that the cap layer 30 covered by the photoresist around the window region forms a physical partition in the window region, and meanwhile, the epitaxial layer 20 located below the cap layer 30 is exposed in the window region, so that the subsequent ion implantation on the epitaxial layer 20 is facilitated. In the present embodiment, the etching method is not limited, and may be, for example, photolithography, dry etching, wet etching, or the like.
By removing the cap layer 30 in the window region, the cap layer 30 forms a physical partition at the window region, so that a channel of leakage current is formed between the heavily doped cap layer 30 and other regions after the active device is subsequently manufactured on the cap layer 30 is blocked, leakage current formed between the active device and other regions is reduced, and the phenomenon that the leakage current of the active device may increase through the isolation region 24 and other regions on the cap layer 30 due to the heavily doped structure of the cap layer 30 after insulating ion implantation of the cap layer 30 is avoided.
S400: and performing ion implantation on the epitaxial layer in the window area to form an isolation region.
As shown in fig. 3, after the cap layer 30 in the window area is removed by etching in S030, the underlying epitaxial layer 20 is exposed in the window area, and then the insulating ion implantation is performed on the device structure, as shown in fig. 4, in the ion implantation process, the cap layer 30 covered by the patterned photoresist 40 is not affected, while the epitaxial layer 20 in the window area forms an isolation region 24, i.e., an insulating region, i.e., a passive region (and, at the same time, an active region and a passive region are also formed), from the surface of the epitaxial layer 20 toward the substrate 10, where the isolation region 24 may penetrate through the epitaxial layer 20 in a direction perpendicular to the substrate 10, i.e., extend to the substrate 10, or may not penetrate through the epitaxial layer 20 in a direction perpendicular to the substrate 10, i.e., not extend to the substrate 10, as shown in fig. 4. After the epitaxial layer 20 in the window region is subjected to ion implantation to form the isolation region 24, a further insulating and isolating effect can be achieved on the active regions on both sides of the isolation region 24 through the isolation region 24, so that after an active device is manufactured and formed on the active region in a subsequent process, the active device can be insulated and isolated, and leakage current between the active device and other regions (other active regions) can be effectively limited in use.
In performing ion implantation, the depth of the isolation region 24 may be controlled by controlling parameters of ion implantation, such as implantation energy, implantation time, implantation concentration, and the like.
The purpose of the above-described fabrication of the isolation regions 24 by ion implantation is to provide isolation properties to specific regions, such as the formation of an insulator in the epitaxial layer 20 in the window region by implantation of insulating ions.
Optionally, a patterned photoresist 40 is formed on the cap layer 30 to define a window region through S200, and referring to fig. 2, the steps include: the photoresist is coated on the cap layer 30, and the coating method can be spin coating, so that the surface of the photoresist is relatively flat. The photoresist pattern applied may be SPR518 and the thickness of the photoresist may be 2.3 μm to 2.7 μm, for example, 2.3 μm, 2.5 μm, 2.7 μm, etc., and it should be noted that the thickness of the photoresist may affect the width of the region to be subsequently implanted with ions in epitaxial layer 20, and the ions may extend into the active device region, thereby affecting the effective active device region. After the photoresist coating is completed, exposing the photoresist to form a photoacid at the exposed position, removing the photoresist through the reaction of an alkaline developer and the photoacid, so that the photoresist is patterned, namely, a window area is formed at the corresponding position, the cap layer 30 is exposed in the window area, and then baking the photoresist with the pattern to harden the photoresist, thereby forming a patterned photoresist 40, and using the hardened patterned photoresist 40 to enhance the adhesiveness of the photoresist, thereby facilitating the subsequent ion implantation.
Before the photoresist is coated on the surface of the cap layer 30, the device structure with the epitaxial structure formed on the substrate 10 can be cleaned firstly, the device can be soaked in alkali liquor for cleaning for 15S, the alkali liquor can be NH 4 OH, and the ratio of the alkali liquor to the photoresist is 1:50, so that the adhesion between the surface of the cleaned cap layer 30 and the photoresist is better.
Alternatively, as shown in fig. 2 to 9, the epitaxial layer 20 in the present application may include the buffer layer 21, the channel layer 22 and the barrier layer 23, the cap layer 30 may include only the first n-type doped layer 32, the cap layer 30 may also include the second n-type doped layer 31 and the first n-type doped layer 32, wherein when the cap layer 30 includes the second n-type doped layer 31 and the first n-type doped layer 32, the buffer layer 21 may be formed on the surface of the substrate 10 by epitaxial growth, the channel layer 22 may be epitaxially grown on the buffer layer 21, the barrier layer 23 may be epitaxially grown on the channel layer 22, the second n-type doped layer 31 may be epitaxially grown on the barrier layer 23, and the doping concentration of the first n-type doped layer 32 may be greater than that of the second n-type doped layer 31, for example: the doping concentration of the second n-type doped layer 31 is 5E17atom/cm 3 to 2E18 atom/cm 3, and the doping concentration of the first n-type doped layer 32 is 3E18 atom/cm 3 to 6E18 atom/cm 3, so that higher breakdown voltage can be maintained, and the device performance is improved; when the cap layer 30 includes only the first n-type doped layer 32, the first n-type doped layer 32 may be formed directly on the barrier layer 23 after the barrier layer 23 is formed, and the doping concentration of the first n-type doped layer 32 in this embodiment may be set with reference to the first n-type doped layer 32 in the previous embodiment.
The channel layer 22 in the embodiment of the present application may be an AlGaAs layer, the barrier layer 23 may be an InGaP layer, the second n-type doped layer 31 may be a lightly doped second n+ GaAs layer, and the first n-type doped layer 32 may be a heavily doped first n+ GaAs layer.
The AlGaAs layer may be 75 a to 100a thick, for example: 75. a, 80 a, 90 a, 100a, etc.
The InGaP layer may be 260 a to 360 a thick, for example: 260. a, 290 a, 310 a, 330 a, 350 a, 360 a, etc.
The thickness of the second n+ GaAs layer may be 250 a to 350 a, for example: 250. a, 270 a, 290 a, 310 a, 330 a, 350 a, etc.
The thickness of the first n+ GaAs layer may be 400 a to 500 a, for example: 400. a, 420 a, 440 a, 460 a, 480 a, 500 a, etc.
Alternatively, when the cap layer 30 is etched in the window region and is terminated to the epitaxial layer 20 by S300, citric acid or succinic acid may be used as an etching solution, and the etching manner may be wet etching, and during etching, the whole device structure is soaked in the etching solution, and the etching time may be 35S, and during etching, since the first n-type doped layer 32 is exposed in the window region, the etching solution etches the first n-type doped layer 32 first, and then etches the second n-type doped layer 31 under the first n-type doped layer 32, and since the citric acid or succinic acid etching solution etches the GaAs cap layer 30, the InGaP barrier layer 23 has a better barrier property, that is, the citric acid or succinic acid etching solution has a higher etching selectivity when etching the GaAs material cap layer 30 to the InGaP barrier layer 23, so that the cap layer 30 can be sufficiently etched and removed, and at the same time, the overetching of the barrier layer 23 can be avoided.
The etching depth of the citric acid or succinic acid etching solution is not limited in the present application, and may be, for example, 450 a to 650 a (450 a, 550 a, 650 a, etc.), so long as the cap layer 30 can be removed more thoroughly and terminated in the epitaxial layer 20, so that the cap layer 30 forms a good physical partition in the window region.
Alternatively, when the epitaxial layer 20 is ion-implanted in the window region to form the isolation region 24 through S400, the following may be performed: at an implantation energy of 190KeV to 250KeV and an implantation dose of 4E11ion/cm 2 to 1E12ion/cm 2, ar 2+ is implanted into the device coated with the patterned photoresist 40, the cap layer 30 covered by the patterned photoresist 40 is not affected during the ion implantation, and the epitaxial layer 20 in the window region is implanted with Ar 2+ such that the epitaxial layer 20 forms an isolation region 24, i.e., a passive region (and simultaneously, an active region and a passive region are also formed) from the surface toward the substrate 10, thereby forming an isolation region 24 on the InGaP layer, alGaAs layer and the buffer layer 21 when the epitaxial layer 20 includes the buffer layer 21, the channel layer 22 and the barrier layer 23, wherein the depth of the isolation region 24 may be 0.55 μm to 0.65 μm, e.g., 0.55 μm, 0.6093 μm, 0.65 μm, etc., such that the isolation region 24 extends through the InGaP layer and the AlGaAs layer to at least a portion of the buffer layer 21 when the isolation region 24 does not extend to the substrate 10, thereby reducing the performance of the device.
Optionally, as shown in fig. 5, the foregoing embodiment forms a physical partition on the cap layer 30, forms the isolation region 24 on the epitaxial layer 20, thereby defining a passive region and an active region on the epitaxial structure, where the active region is isolated by the passive region, and further forms a first active device, such as a field effect transistor device (PHEMT), on the cap layer 30 of the active region, and forms the source 51 and the drain 52 spaced apart from each other on the cap layer 30 of the active region when forming the field effect transistor device, so that the source 51 and the drain 52 form ohmic contacts with the cap layer 30, and it should be noted that those skilled in the art should know that the source 51 and the drain 52 of the same active device should be located on the same side of the passive region, i.e. should not have the passive region between the source and the drain of the same active device. The cap layer 30 between the source electrode 51 and the drain electrode 52 is etched to form a recess between the source electrode 51 and the drain electrode 52, the bottom of the recess being the epitaxial layer 20, i.e. the epitaxial layer 20 is exposed between the source electrode 51 and the drain electrode 52, and then the gate electrode 53 is formed in the recess such that the gate electrode 53 forms a schottky contact with the epitaxial layer 20, thus forming the first active device. In fabricating the source electrode 51, the drain electrode 52 and the gate electrode 53 of the field effect transistor device, a yellow light process may be completed using photoresist coating/exposure/development, respectively; then evaporating source electrode 51 metal, drain electrode 52 metal and grid electrode 53 metal respectively; then, the source 51, the drain 52 and the gate 53 of the field effect transistor are obtained after photoresist stripping. Of course, the first active device may also be an enhancement mode field effect transistor (E-mode FET), a depletion mode field effect transistor (D-mode FET), an epitaxial resistor (EPI resistor), or the like.
After forming the isolation region 24 on the epitaxial layer 20 by forming a physical partition on the cap layer 30 in S300, the patterned photoresist 40 on the cap layer 30 may be stripped, which may be removed by an NMP solution, before the active device is fabricated on the active region in S400.
The position of the window region of the patterned photoresist 40 defines the position of the subsequent etching cap layer 30, and also defines the position of the ion implantation of the epitaxial layer 20, that is, the position of the inactive region, and according to the device structure to be manufactured, the inactive region and the active region located in the inactive region can be formed at the edge of the epitaxial structure; it is also possible to form one active region (hereinafter referred to as a first active region for convenience of description) inside the inactive region after the inactive region is formed in the epitaxial structure, and to form another active region (hereinafter referred to as a second active region for convenience of description) outside the inactive region, as shown in fig. 5.
In the first embodiment: as shown in fig. 5, a passive region is formed on the epitaxial structure by etching, injecting insulating ions, and a first active region located inside the passive region and a second active region located outside the passive region, wherein the first active region and the second active region are insulated and isolated by an isolation region 24 on the epitaxial layer 20 and by a physical isolation on the cap layer 30, by which a first active device, such as a PHEMT device, can be fabricated in the first active region first, and then a second active device 60 can be fabricated on the cap layer 30 of the second active region, as shown in fig. 6, and the second active device 60 can be an enhancement-mode field effect transistor (E-mode FET) or a depletion-mode field effect transistor (D-mode FET), and of course, as shown in fig. 7, the second active device can also be an EPI resistor (EPI resistor), or the like. At this time, the first active device and the second active device 60 may be physically separated by the cap layer 30 in the inactive region, so as to reduce the leakage current therebetween, and at the same time, the isolation region 24 formed in the inactive region by the epitaxial layer 20 may further limit the leakage current between the first active device and the second active device 60, so as to effectively improve the performance of the overall device.
In a second embodiment: the difference from the first embodiment is that after the first active device is formed, as shown in fig. 8, the cap layer 30 of the second active region is removed by etching, so that the epitaxial layer 20 of the second active region is exposed, and at this time, an epitaxial resistor 70 (EPI resistor) may also be fabricated on the epitaxial layer 20 of the second active region, so that the first active device and the epitaxial resistor 70 may be physically separated by the cap layer 30 in the inactive region, thereby reducing the leakage current between the first active device and the epitaxial resistor 70, and at the same time, the leakage current between the first active device and the epitaxial resistor 70 may be further limited by the isolation region 24 formed by the epitaxial layer 20 in the inactive region, so as to effectively improve the performance of the whole device.
In a third embodiment: as shown in fig. 5, a passive region is formed on the epitaxial structure by etching, injecting insulating ions, and an active region adjacent to the passive region, wherein the active region is insulated on the epitaxial layer 20 by the isolation region 24 and insulated on the cap layer 30 by physical isolation, by which a first active device may be fabricated in the active region, as shown in fig. 9, and then a passive device 80 may be fabricated in the passive region, i.e., the passive device 80 may be an inductor, a resistor, a capacitor, or the like, fabricated on the isolation region 24. In this way, the first active device and the passive device 80 can be insulated and isolated by the isolation region 24, so that leakage current between the first active device and the passive device 80 is limited, and performance of the whole device is effectively improved.
In the fourth embodiment: the passive device 80 is fabricated in the passive region on the basis of the device formed in the first embodiment, so that the first active device and the second active device 60 can reduce the leakage current between the two through the physical partition formed on the cap layer 30 and the isolation region 24 formed on the epitaxial layer 20, and in addition, the passive device 80 and the first active device and the second active device 60 can be isolated through the isolation region 24 respectively, thereby limiting the leakage current between the passive device 80 and the first active device and the second active device 60 respectively, and effectively improving the performance of the whole device.
In the fifth embodiment: on the basis of the device structure formed in the second embodiment, the passive device 80 is manufactured in the passive region, so that the first active device and the epitaxial resistor 70 can reduce the leakage current between the first active device and the epitaxial resistor through the physical isolation of the cap layer 30 and the isolation region 24 of the epitaxial layer 20, and in addition, the passive device 80 is isolated from the first active device and the epitaxial resistor 70 through the isolation region 24 in an insulating manner, thereby limiting the leakage current between the passive device 80 and the first active device and the epitaxial resistor 70 respectively, and effectively improving the performance of the whole device.
In another aspect of the embodiments of the present invention, there is provided a semiconductor device manufactured by any one of the above semiconductor device manufacturing methods, as shown in fig. 5, including: the substrate 10 and the epitaxial structure arranged on the substrate 10, the epitaxial structure comprises an epitaxial layer 20 and a cap layer 30 which are sequentially arranged on the substrate 10, an isolation region 24 is formed on the epitaxial layer 20, and a groove communicated with the isolation region 24 is formed on the cap layer 30, so that the cap layer 30 positioned on two sides of the groove can form a physical partition at the groove to realize insulation isolation, leakage current of an active device manufactured on the cap layer 30 and other regions is reduced when the epitaxial structure is used, and meanwhile, the epitaxial layer 20 can be insulated and isolated through the isolation region 24, so that leakage current of the active device is further reduced.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A method of manufacturing a semiconductor device, the method comprising:
Epitaxially growing an epitaxial structure on a substrate, wherein the epitaxial structure comprises an epitaxial layer and a cap layer which are sequentially formed on the substrate;
soaking the substrate growing with the epitaxial structure in alkali liquor for cleaning for 15S, wherein the alkali liquor is NH 4 OH, and the ratio is 1:50;
Forming a patterned photoresist on the cap layer to define a window region;
Etching the cap layer in the window area to terminate in the epitaxial layer;
ion implantation is carried out on the epitaxial layer in the window area so as to form an isolation area;
The cap layer is a GaAs cap layer, the thickness of the photoresist is 2.3-2.7 mu m, the epitaxial layer comprises a buffer layer, a channel layer and a barrier layer which are sequentially formed, under the conditions that the implantation energy is 190-250 KeV and the implantation dosage is 4E11ion/cm 2 -1E 12ion/cm 2, argon ions are adopted to carry out ion implantation on the surface of the barrier layer in the window area towards the substrate direction so as to form isolation areas on the barrier layer, the channel layer and the buffer layer, and the depth of the isolation areas is 0.55-0.65 mu m;
The cap layer comprises a second n-type doped layer and a first n-type doped layer which are formed in sequence, and the doping concentration of the first n-type doped layer is greater than that of the second n-type doped layer;
The doping concentration of the second n-type doped layer is 5E17atom/cm 3 to 2E18 atom/cm 3, and the doping concentration of the first n-type doped layer is 3E18 atom/cm 3 to 6E18 atom/cm 3.
2. The method of manufacturing a semiconductor device according to claim 1, wherein forming a patterned photoresist on the cap layer to define a window region comprises:
Coating a photoresist on the cap layer;
and exposing and developing the photoresist to define a window area, and baking to form the patterned photoresist.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the cap layer includes a second n-type doped layer and a first n-type doped layer formed in sequence, and etching the cap layer in the window region terminates in the epitaxial layer includes:
And sequentially etching the first n-type doped layer and the second n-type doped layer in the window area by adopting citric acid or succinic acid, and ending at the barrier layer.
4. A method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein after ion implantation of the epitaxial layer in the window region to form an isolation region, the method further comprises:
Forming source electrodes and drain electrodes which are arranged at intervals on the cap layer;
etching the cap layer to expose the epitaxial layer between the source electrode and the drain electrode;
and forming a gate electrode on the epitaxial layer exposed between the source electrode and the drain electrode to form a first active device.
5. The method of manufacturing a semiconductor device according to claim 4, wherein after the forming a gate electrode on the epitaxial layer exposed between the source electrode and the drain electrode to form a first active device, the method further comprises:
And forming a passive device on the isolation region.
6. A semiconductor device manufactured by the manufacturing method of the semiconductor device according to any one of claims 1 to 5.
7. A method of manufacturing a semiconductor device, the method comprising: epitaxially growing an epitaxial structure on a substrate, wherein the epitaxial structure comprises an epitaxial layer and a cap layer which are sequentially formed on the substrate; soaking the substrate growing with the epitaxial structure in alkali liquor for cleaning for 15S, wherein the alkali liquor is NH 4 OH, and the ratio is 1:50; forming a patterned photoresist on the cap layer to define a window region; etching the cap layer in the window area to terminate in the epitaxial layer; ion implantation is carried out on the epitaxial layer in the window area so as to form an isolation area;
After ion implantation of the epitaxial layer in the window region to form an isolation region, the method further comprises: forming source electrodes and drain electrodes which are arranged at intervals on the cap layer; etching the cap layer to expose the epitaxial layer between the source electrode and the drain electrode; forming a gate electrode on the epitaxial layer exposed between the source electrode and the drain electrode to form a first active device;
After the forming a gate on the epitaxial layer exposed between the source and the drain to form a first active device, the method further comprises: etching the cap layer to expose the epitaxial layer; forming an epitaxial resistor on the epitaxial layer, wherein the epitaxial resistor is isolated from the first active device by the isolation region;
The cap layer comprises a second n-type doped layer and a first n-type doped layer which are formed in sequence, and the doping concentration of the first n-type doped layer is greater than that of the second n-type doped layer;
The cap layer is a GaAs cap layer, the thickness of the photoresist is 2.3-2.7 mu m, the epitaxial layer comprises a buffer layer, a channel layer and a barrier layer which are sequentially formed, under the conditions that the implantation energy is 190-250 KeV and the implantation dosage is 4E11ion/cm 2 -1E 12ion/cm 2, argon ions are adopted to carry out ion implantation on the surface of the barrier layer in the window area towards the substrate direction so as to form isolation areas on the barrier layer, the channel layer and the buffer layer, and the depth of the isolation areas is 0.55-0.65 mu m;
The doping concentration of the second n-type doped layer is 5E17atom/cm 3 to 2E18 atom/cm 3, and the doping concentration of the first n-type doped layer is 3E18 atom/cm 3 to 6E18 atom/cm 3.
8. A semiconductor device manufactured by the manufacturing method of the semiconductor device according to claim 7.
9. A method of manufacturing a semiconductor device, the method comprising: epitaxially growing an epitaxial structure on a substrate, wherein the epitaxial structure comprises an epitaxial layer and a cap layer which are sequentially formed on the substrate; soaking the substrate growing with the epitaxial structure in alkali liquor for cleaning for 15S, wherein the alkali liquor is NH 4 OH, and the ratio is 1:50; forming a patterned photoresist on the cap layer to define a window region; etching the cap layer in the window area to terminate in the epitaxial layer; ion implantation is carried out on the epitaxial layer in the window area so as to form an isolation area;
After ion implantation of the epitaxial layer in the window region to form an isolation region, the method further comprises: forming source electrodes and drain electrodes which are arranged at intervals on the cap layer; etching the cap layer to expose the epitaxial layer between the source electrode and the drain electrode; forming a gate electrode on the epitaxial layer exposed between the source electrode and the drain electrode to form a first active device;
After the forming a gate on the epitaxial layer exposed between the source and the drain to form a first active device, the method further comprises: forming an epitaxial resistor on the cap layer, wherein the first active device is isolated from the epitaxial resistor by the isolation region;
The cap layer comprises a second n-type doped layer and a first n-type doped layer which are formed in sequence, and the doping concentration of the first n-type doped layer is greater than that of the second n-type doped layer;
The cap layer is a GaAs cap layer, the thickness of the photoresist is 2.3-2.7 mu m, the epitaxial layer comprises a buffer layer, a channel layer and a barrier layer which are sequentially formed, under the conditions that the implantation energy is 190-250 KeV and the implantation dosage is 4E11ion/cm 2 -1E 12ion/cm 2, argon ions are adopted to carry out ion implantation on the surface of the barrier layer in the window area towards the substrate direction so as to form isolation areas on the barrier layer, the channel layer and the buffer layer, and the depth of the isolation areas is 0.55-0.65 mu m;
The doping concentration of the second n-type doped layer is 5E17atom/cm 3 to 2E18 atom/cm 3, and the doping concentration of the first n-type doped layer is 3E18 atom/cm 3 to 6E18 atom/cm 3.
10. A semiconductor device manufactured by the manufacturing method of the semiconductor device according to claim 9.
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