CN112614525B - Low-power-consumption phase change memory write driving circuit capable of improving resistance consistency - Google Patents
Low-power-consumption phase change memory write driving circuit capable of improving resistance consistency Download PDFInfo
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- CN112614525B CN112614525B CN202011486054.5A CN202011486054A CN112614525B CN 112614525 B CN112614525 B CN 112614525B CN 202011486054 A CN202011486054 A CN 202011486054A CN 112614525 B CN112614525 B CN 112614525B
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- 238000002955 isolation Methods 0.000 claims abstract description 48
- 238000009966 trimming Methods 0.000 claims description 13
- 230000000630 rising effect Effects 0.000 claims description 9
- 230000003111 delayed effect Effects 0.000 claims description 3
- 230000001960 triggered effect Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 9
- 230000005540 biological transmission Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 238000003708 edge detection Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0038—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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Abstract
The invention relates to a low-power consumption phase change memory write driving circuit for improving resistance consistency, wherein a reference voltage or current generated by a reference generating circuit is provided for a current mirror isolation circuit; the oscillator generates a clock signal for the sequential circuit; the write signal processing circuit judges the relation between the write enabling signal and the clock signal and provides the enabling signal to the pulse control circuit directly or after time delay; the current mirror isolation circuit provides bias for the current source circuit under the control of the current mirror switch circuit; the pulse control circuit is used for controlling the current pulse amplitude, the current pulse duration, the current pulse step number and the step time generated by the current source circuit; the current source circuit generates corresponding write current pulses according to the bias provided by the current mirror isolation circuit and the control signal generated by the pulse control circuit. The invention can optimize the first write current pulse waveform after the memory is electrified and reduce the power consumption as much as possible.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a low-power-consumption phase-change memory write driving circuit for improving resistance consistency.
Background
The core of the phase change memory writing driving circuit and the system is that the driving current generated by the driving current generating circuit is input to the phase change unit selected by the address decoding circuit, so that the phase change unit is converted between crystalline state and amorphous state to store 0 and 1. The prior art mainly focuses on controlling the amplitude, duration, current pulse step number and step time of a current pulse signal; or on trimming the write current of the memory, the problem of poor write consistency caused by slow rising edge of the first write operation due to no pre-charge of the bias voltage of the current source circuit in the first write operation after the memory is electrified is solved.
Disclosure of Invention
The invention aims to solve the technical problem of providing a low-power-consumption phase-change memory write driving circuit for improving the consistency of resistance, optimizing the first write current pulse waveform of a memory after power-on, and reducing the power consumption as much as possible.
The technical scheme adopted for solving the technical problems is as follows: provided is a low power consumption phase change memory write driving circuit for improving resistance consistency, comprising: the device comprises an oscillator, a writing signal processing circuit, a current mirror isolation circuit, a current mirror switch circuit, a pulse control circuit and a current source circuit;
the oscillator is respectively connected with the write signal processing circuit and the pulse control circuit and is used for generating a clock signal with fixed frequency;
the current mirror switch circuit is connected with the pulse control circuit and used for controlling the opening and closing of the current mirror isolation circuit;
the current mirror isolation circuit generates a current source bias voltage VWB to the current source circuit;
the write signal processing circuit is respectively connected with the oscillator and the pulse control circuit and is used for comparing an externally input write enable signal WE_with a clock signal generated by the oscillator and generating an enable signal WEP_according to a comparison result to be provided for the pulse control circuit so as to ensure the pre-charging time of the current mirror isolation circuit;
the pulse control circuit is triggered by the enable signal WEP_and generates control signals by using clock signals generated by the oscillator and the logic circuit to control the opening and closing of different branches in the current source circuit;
the current source circuit generates write current pulses according to the bias voltage VWB provided by the current mirror isolation circuit and the control signal provided by the pulse control circuit.
The current mirror switch circuit uses a write enable signal WE_to control the opening and closing of the current mirror isolation circuit when the memory is powered on and performs first write operation; and during the subsequent writing operation, using the writing pulse enabling WPLS output by the pulse control circuit to control the opening and closing of the current mirror isolation circuit.
When a first write enable signal WE_input from the outside after the memory is electrified comes, the write signal processing circuit compares the write enable signal WE_with a clock signal; if the write enable signal WE_comes along the falling edge, the clock signal is in a low level, and the write enable signal WE_is delayed to generate an enable signal WEP_to the pulse control circuit; if the CLK is high when WE_falling edge arrives, the write enable signal WE_is taken as the enable signal WEP_.
The current mirror isolation circuit is connected with the reference generation circuit and is used for generating a reference signal, and the current mirror isolation circuit generates a current source bias voltage VWB according to the reference signal so as to reduce the influence of charge feed-through caused by control switches of different branches in the current source circuit on the bias voltage VWB.
The write signal processing circuit is a circuit formed by a logic circuit, a transmission gate, a trigger, a latch or a register.
The current mirror switching circuit is a circuit formed by a logic circuit, a transmission gate, a trigger, a latch or a register.
The pulse control circuit comprises a counter circuit, a comparator circuit, a frequency divider circuit and a logic trimming circuit; the counter circuit is used for calculating the number of rising edges or falling edges of clock signals, and the comparator is used for comparing the output of the counter with a set pulse time length trimming signal and determining the opening time length of control signals of different branches in the current source circuit; the frequency divider circuit is used for generating a plurality of clock signals with different frequencies to adjust the step time of the current pulse; and the logic trimming circuit determines the opening number of control signals of different branches in the current source circuit according to the set pulse height trimming signal.
The pulse control circuit simultaneously provides a write pulse enabling signal WPLS for the write signal processing circuit and the current mirror switching circuit, so that the write signal processing circuit and the current mirror switching circuit only carry out write enabling signal WE_delay for the first write operation after the memory is powered on, the switch of the current mirror isolation circuit is controlled by using the write enabling signal WE_and the write enabling signal WE_delay is not carried out for the subsequent write operation, and the switch of the current mirror isolation circuit is controlled by the write pulse enabling signal WPLS.
Drawings
FIG. 1 is a block diagram of an embodiment of the present invention;
FIG. 2 is a circuit diagram of a write signal processing circuit in an embodiment of the invention;
FIG. 3 is a circuit diagram of a current mirror switching circuit in an embodiment of the invention;
FIG. 4 is a timing diagram of a prior art write circuit with WPLS controlling the switching of the current mirror isolation circuit;
FIG. 5 is a timing diagram of a WE_control current mirror isolation circuit switch;
FIG. 6 is a timing diagram of a first write operation of a current mirror isolation circuit switch after power up of a memory in accordance with an embodiment of the present invention;
FIG. 7 is a timing diagram of the first two write operations after power up of the memory for a current mirror isolation circuit switch according to an embodiment of the present invention;
FIG. 8 is a graph of simulation results of average power consumption during a write operation by WE_controlled current mirror isolation circuit switches;
FIG. 9 is a graph of simulation results of average power consumption at the time of a write operation in accordance with the present invention.
Detailed Description
The embodiment of the invention relates to a low-power consumption phase-change memory write driving circuit for improving resistance consistency, which is shown in fig. 1 and comprises the following components: the write circuit comprises a write signal processing circuit, a current mirror isolation circuit, a current mirror switch circuit, a reference generating circuit, an oscillator, a current source circuit and a pulse control circuit. The reference generating circuit is connected with the current mirror isolation circuit, the oscillator is respectively connected with the writing signal processing circuit and the pulse control circuit, the current mirror isolation circuit is connected with the current source circuit, and the pulse control circuit is respectively connected with the writing signal processing circuit, the current mirror switching circuit and the current source circuit. In the writing operation process, the current source circuit outputs the generated current pulse or voltage pulse to the phase change unit selected by the decoding control circuit.
The oscillator is used for generating a clock signal CLK with a fixed frequency.
The reference generating circuit is used for generating a reference voltage or current which is irrelevant to parameters such as power supply, process, temperature and the like.
The write signal processing circuit is used for comparing an externally input write enable signal WE_with a clock signal CLK generated by the oscillator, generating an enable signal WEP_according to a comparison result and providing the enable signal WEP_for the pulse control circuit, ensuring the precharge time of the current mirror isolation circuit and realizing the optimization of a first write current pulse waveform after the memory is electrified.
In this embodiment, the write signal processing circuit compares the write enable signal we_with the clock signal CLK when the first write enable signal we_externally input after the memory is powered on comes; if the falling edge of the write enable signal we_arrives, the clock signal CLK is at a low level, that is, the interval between the falling edge of the write enable signal we_and the rising edge of the upcoming clock signal CLK is shorter, and the time requirement of the current mirror isolation circuit for precharging the bias voltage VWB during the first write operation after powering up the memory cannot be met, and the write signal processing circuit delays the write enable signal we_to generate the enable signal wep_to the pulse control circuit; if the falling edge of the write enable signal we_arrives, the clock signal CLK is at a high level, that is, the interval between the falling edge of the write enable signal we_and the rising edge of the upcoming clock signal CLK is longer, so that the time requirement of the current mirror isolation circuit for precharging the bias voltage VWB during the first write operation after the memory is powered on, or the second and subsequent write operations after the memory is powered on can be met, the write signal processing circuit does not perform a delay operation, so that the enable signal wep_is identical to the write enable signal we_.
The write signal processing circuit is a circuit formed by a logic circuit, a transmission gate, a trigger, a latch or a register. Fig. 2 is a diagram showing a write signal processing circuit according to the present embodiment, in which POR is a power-on reset signal, and WENE is a write enable signal we_falling edge detection signal.
The pulse control circuit is triggered by an enable signal WEP_provided by the write signal processing circuit, and utilizes a clock signal CLK generated by an oscillator and control signals S <0>, S <1>, … … and S < n > generated by a logic circuit to control the opening and closing of different branches of the current source circuit so as to realize the control of current pulse amplitude, current pulse duration, current pulse step number and descending step time.
The pulse control circuit of the present embodiment includes a counter circuit, a comparator circuit, a frequency divider circuit, and a logic trimming circuit. The counter calculates the number of rising edges or falling edges of clock signals, the output of the comparator compares the output of the counter with a set pulse time length trimming signal to determine the opening time length of control signals S <0>, S <1>, … … and S < n >, the frequency divider generates a plurality of clock signals with different frequencies to trim the current pulse step time, and the logic trimming circuit determines the opening number of the control signals S <0>, S <1>, … … and S < n > according to the set pulse height trimming signal, so that the control of different current pulse amplitude, current pulse duration, current pulse step number and descending step time is realized.
The pulse control circuit provides a write pulse enable signal WPLS to the write signal processing circuit and the current mirror switching circuit, so that the write signal enable circuit and the current mirror switching circuit only carry out write enable signal WE_delay and use WE_to control switching of the current mirror isolation circuit for the first write operation after the memory is powered on, the write enable signal WE_is not delayed in the subsequent write operation, and the write pulse enable signal WPLS controls switching of the current mirror, and power consumption is reduced as much as possible while optimizing the first write current pulse waveform after the memory is powered on.
The current mirror switch circuit is used for controlling the opening and closing of the current mirror isolation circuit. In this embodiment, the current mirror switching circuit controls the switch of the current mirror isolation circuit with the write enable signal we_during the first write operation after the memory is powered on, and the subsequent write operation controls the switch of the current mirror isolation circuit with the write pulse enable WPLS output by the pulse control circuit. Fig. 3 is a circuit diagram of a current mirror switching circuit of the present embodiment.
The current mirror isolation circuit is used for generating a current source bias voltage VWB according to the reference provided by the reference generation circuit so as to remarkably reduce the influence of charge feed-through caused by S <0>, S <1>, … … and S < n > switches on the bias voltage VWB.
The current source circuit generates corresponding write current pulses according to the bias voltage VWB provided by the current mirror isolation circuit and control signals S <0>, S <1>, … … and S < n > provided by the pulse control circuit, and voltage initialization pulses are generated by VRST signal control.
As shown in FIG. 4, the current mirror isolation circuit switch is controlled by WPLS in the conventional write circuit, and the current flowing through the phase change cell for the first write operation after the memory is powered up rises slowly, resulting in poor write consistency. As shown in fig. 5, when we_controls the current mirror isolation circuit switch and we_falling edge is closer to CLK rising edge, there is still a problem that the current flowing through the phase change cell for the first write operation after the memory is powered up rises slower, resulting in poor write consistency.
In the current mirror isolation circuit switch of the embodiment, after the memory is powered on, the first write operation is controlled by WE_and the relationship between WE_and CLK is judged, as shown in FIG. 6, if the WE_falling edge is close to the CLK rising edge, WEP_is generated after time delay and is provided for the pulse control circuit, so that the precharge time is ensured, and the first write current pulse rises faster after the memory is powered on; subsequent write operations are controlled by WPLS, reducing the current mirror isolation circuit on-time compared to we_control, reducing power consumption. As shown in fig. 7 below, the current rises rapidly in the first write operation after power-up, and the phase change cell write uniformity is better.
FIG. 8 is average power consumption during a write operation by WE_control of the current mirror isolation circuit switch; fig. 9 is average power consumption at the time of write operation in the present embodiment. As can be seen from comparison, the average power consumption of the present embodiment during writing operation is significantly lower than the average power consumption during writing operation by we_controlled current mirror isolation circuit switch.
It should be noted that the rising edges, falling edges, high levels, low levels in this embodiment are merely for convenience of description and simplicity of description, and are not indicative or implying that the apparatus or element in question must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present application.
Claims (8)
1. A low power consumption phase change memory write drive circuit for improving resistance uniformity, comprising: the device comprises an oscillator, a writing signal processing circuit, a current mirror isolation circuit, a current mirror switch circuit, a pulse control circuit and a current source circuit; the oscillator is respectively connected with the write signal processing circuit and the pulse control circuit and is used for generating a clock signal with fixed frequency;
the current mirror switch circuit is connected with the pulse control circuit and used for controlling the opening and closing of the current mirror isolation circuit;
the current mirror isolation circuit generates a current source bias voltage VWB to the current source circuit;
the write signal processing circuit is respectively connected with the oscillator and the pulse control circuit and is used for comparing an externally input write enable signal WE_with a clock signal generated by the oscillator and generating an enable signal WEP_according to a comparison result to be provided for the pulse control circuit so as to ensure the pre-charging time of the current mirror isolation circuit;
the pulse control circuit is triggered by the enable signal WEP_and generates control signals by using clock signals generated by the oscillator and the logic circuit to control the opening and closing of different branches in the current source circuit;
the current source circuit generates write current pulses according to the bias voltage VWB provided by the current mirror isolation circuit and the control signal provided by the pulse control circuit.
2. The write driver circuit of a low power phase change memory for improved resistance uniformity of claim 1, wherein said current mirror switching circuit uses a write enable signal we_to control the turn-on and turn-off of said current mirror isolation circuit during a first write operation after memory power-up; and during the subsequent writing operation, using the writing pulse enabling WPLS output by the pulse control circuit to control the opening and closing of the current mirror isolation circuit.
3. The write driving circuit of a low power phase change memory for improving resistance uniformity according to claim 1, wherein said write signal processing circuit compares a write enable signal we_with a clock signal when a first write enable signal we_externally inputted after a memory is powered on comes; if the write enable signal WE_comes along the falling edge, the clock signal is in a low level, and the write enable signal WE_is delayed to generate an enable signal WEP_to the pulse control circuit; if the CLK is high when WE_falling edge arrives, the write enable signal WE_is taken as the enable signal WEP_.
4. The write driver circuit of claim 1, wherein the current mirror isolation circuit is coupled to a reference generation circuit, the reference generation circuit configured to generate a reference signal, the current mirror isolation circuit configured to generate a current source bias voltage VWB based on the reference signal to reduce an effect of charge feed-through caused by control switches of different branches of the current source circuit on the bias voltage VWB.
5. The low power consumption phase change memory write driver circuit of claim 1, wherein the write signal processing circuit is a circuit formed by logic circuits, pass gates, flip-flops, latches or registers.
6. The low power consumption phase change memory write driver circuit of claim 1, wherein said current mirror switching circuit is a circuit formed by logic circuits, pass gates, flip-flops, latches or registers.
7. The low power consumption phase change memory write driver circuit of claim 1, wherein the pulse control circuit comprises a counter circuit, a comparator circuit, a frequency divider circuit, and a logic trimming circuit; the counter circuit is used for calculating the number of rising edges or falling edges of clock signals, and the comparator is used for comparing the output of the counter with a set pulse time length trimming signal and determining the opening time length of control signals of different branches in the current source circuit; the frequency divider circuit is used for generating a plurality of clock signals with different frequencies to adjust the step time of the current pulse; and the logic trimming circuit determines the opening number of control signals of different branches in the current source circuit according to the set pulse height trimming signal.
8. The write driving circuit for a low power phase change memory according to claim 1, wherein the pulse control circuit supplies a write pulse enable signal WPLS to both the write signal processing circuit and the current mirror switching circuit simultaneously, causes the write signal processing circuit and the current mirror switching circuit to delay the write enable signal we_only for a first write operation after the memory is powered up and controls switching of the current mirror isolation circuit using the write enable signal we_without delaying the write enable signal we_for a subsequent write operation, and controls switching of the current mirror isolation circuit by the write pulse enable signal WPLS.
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| CN202011486054.5A CN112614525B (en) | 2020-12-16 | 2020-12-16 | Low-power-consumption phase change memory write driving circuit capable of improving resistance consistency |
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