CN109509835B

CN109509835B - Method for manufacturing phase change memory

Info

Publication number: CN109509835B
Application number: CN201811516556.0A
Authority: CN
Inventors: 杨子澔; 张明丰
Original assignee: Beijing Times Full Core Storage Technology Co ltd
Current assignee: Beijing Times Full Core Storage Technology Co ltd
Priority date: 2018-12-12
Filing date: 2018-12-12
Publication date: 2022-09-23
Anticipated expiration: 2038-12-12
Also published as: CN109509835A

Abstract

A method of fabricating a phase change memory, comprising: forming a structure comprising: a bottom electrode; a dielectric layer located above the bottom electrode; an isolation layer located above the dielectric layer and having an opening penetrating through the isolation layer; and a polysilicon layer located within the opening; forming a first hole and a second hole respectively penetrating through the polysilicon layer and the dielectric layer, wherein the second hole is positioned below the first hole; forming a protective layer in the first hole and the second hole and above the polysilicon layer; performing a chemical mechanical polishing process, or performing a dry etching process and a chemical mechanical polishing process to remove a portion of the passivation layer, the isolation layer and the polysilicon layer, expose the dielectric layer, and leave the passivation layer in the second hole; removing the protective layer in the second hole to expose the second hole; and depositing a heating material into the second hole. The method can avoid the danger caused by using tetramethylammonium hydroxide solution, and can avoid the damage of the holes in the dielectric layer, so that the holes have good dimensional stability.

Description

Method for manufacturing phase change memory

Technical Field

The present disclosure relates to a method of manufacturing a phase change memory.

Background

Electronic products (such as mobile phones, tablet computers and digital cameras) often have memory devices for storing data. Conventional memory devices can store information via storage nodes on memory cells. Phase change memories use the resistance states (e.g., high resistance and low resistance) of memory elements to store information. The memory element may have a material that is switchable between different phase states, e.g., crystalline and amorphous. The different phase states cause the memory cell to have resistance states with different resistance values for representing different values of stored data.

The current process for fabricating phase change memory devices includes a typical keyhole transfer method. In detail, the method forms a polysilicon layer with a keyhole structure (or a void) on the dielectric layer, then transfers the keyhole structure to the dielectric layer by etching, forms a small-sized hole in the dielectric layer, and then removes the remaining polysilicon layer.

However, in the step of removing the remaining polysilicon layer, a solution with a very high selectivity ratio for the polysilicon layer and the surrounding material, such as a tetramethylammonium hydroxide (TMAH) solution, is usually used for wet etching to avoid damaging the holes, which may cause the size of the holes to change and affect the performance of the phase change memory. However, the tetramethylammonium hydroxide solution is extremely toxic and highly lethal, and poses great danger to operators.

Disclosure of Invention

The present disclosure provides a method for fabricating a phase change memory, which removes a polysilicon layer by other process steps without using a tetramethylammonium hydroxide solution. The method can avoid the danger caused by using tetramethylammonium hydroxide solution, and can also avoid the damage of the holes in the dielectric layer, so that the holes have good dimensional stability.

The present disclosure provides a method of manufacturing a phase change memory, comprising: forming a structure comprising: a bottom electrode; a dielectric layer located above the bottom electrode; an isolation layer located above the dielectric layer and having an opening penetrating through the isolation layer; and a polysilicon layer located within the opening; forming a first hole and a second hole respectively penetrating through the polysilicon layer and the dielectric layer, wherein the second hole is positioned below the first hole; forming a protective layer in the first hole and the second hole and above the polysilicon layer; performing a chemical mechanical polishing process, or performing a dry etching process and a chemical mechanical polishing process, to remove a portion of the passivation layer, the isolation layer and the polysilicon layer, and expose the dielectric layer, and leave the passivation layer in the second hole; removing the protective layer in the second hole to expose the second hole; and depositing a heating material into the second hole.

According to embodiments of the present disclosure, a polysilicon layer of a structure has a void within an opening.

According to some embodiments of the present disclosure, the steps of performing the dry etching process and the chemical mechanical polishing process include: performing a dry etching process on the protection layer to expose the isolation layer and the polysilicon layer; and performing a chemical mechanical polishing process to remove the exposed isolation layer, the exposed polysilicon layer and the protective layer in the first hole, expose the dielectric layer, and leave the protective layer in the second hole.

According to several embodiments of the present disclosure, an upper surface of the exposed isolation layer is coplanar or substantially coplanar with an upper surface of the exposed polysilicon layer.

According to several embodiments of the present disclosure, the upper surface of the exposed polysilicon layer is coplanar or substantially coplanar with the upper surface of the protection layer within the first hole.

According to some embodiments of the present disclosure, the CMP process is performed using only the slurry for CMP of the isolation layer.

According to several embodiments of the present disclosure, the step of removing the passivation layer in the second hole uses dry etching, wet etching or a combination thereof.

According to several embodiments of the present disclosure, the step of depositing the heating material further comprises depositing the heating material over the dielectric layer.

According to a number of embodiments of the present disclosure, a method also includes: after the step of depositing the heating material, another chemical mechanical polishing process is performed to remove the heating material located above the dielectric layer and expose the dielectric layer to form a heater in the dielectric layer, wherein a top surface of the heater is flush with a top surface of the dielectric layer.

According to a number of embodiments of the present disclosure, the method further comprises: a top electrode and a phase change element are formed over the heater.

Drawings

The foregoing and other objects, features, advantages and embodiments of the disclosure will be apparent from the following more particular description of the embodiments, as illustrated in the accompanying drawings in which:

FIGS. 1-10 illustrate cross-sectional views of a method of fabricating a phase change memory at various stages of fabrication, according to several embodiments of the present disclosure.

Detailed Description

Various embodiments or examples of the disclosure are provided below to achieve different technical features of the provided subject matter. The elements and design of the following embodiments are presented to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the present disclosure. For example, the description discloses forming a first feature over a second feature, including embodiments in which the first feature and the second feature are formed in direct contact, and also including embodiments in which additional features are formed between the first feature and the second feature, i.e., the first feature and the second feature are not in direct contact. Moreover, throughout the various examples, repeated reference symbols and/or usage of words may be used. These repeated symbols or words are provided for simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or the described structures.

Furthermore, spatially relative terms, such as "lower," "upper," and the like, are used for convenience in describing the relative relationship of one element or feature to another element or feature in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The present disclosure provides a method for fabricating a phase change memory, which uses other process steps to remove the polysilicon layer, instead of using tetramethylammonium hydroxide solution to remove the polysilicon layer. The method can avoid the danger caused by using tetramethylammonium hydroxide solution, and can also avoid the damage of the holes in the dielectric layer, so that the holes have good dimensional stability. Embodiments of methods for fabricating phase change memory are described below.

FIGS. 1-10 illustrate cross-sectional views of a method of fabricating a phase change memory at various stages of fabrication, according to several embodiments of the present disclosure. As shown in fig. 1, a structure is obtained that includes a bottom electrode 110, a dielectric layer 112, an isolation layer 114, and a polysilicon layer 116. A dielectric layer 112 is located over the bottom electrode 110. Isolation layer 114 is situated over dielectric layer 112, and isolation layer 114 has an opening O1 through the isolation layer 114. Polysilicon layer 116 is located within opening O1.

In some embodiments, as shown in FIG. 1, the structure further comprises another dielectric layer 103 and a lower connection element 105. The dielectric layer 103 may be a single layer or a multi-layer structure. In some embodiments, the dielectric layer 103 is made of an oxide, nitride, oxynitride or combination thereof, such as silicon oxide, silicon nitride, silicon oxynitride or combination thereof. In some embodiments, the dielectric layer 103 has an opening through the dielectric layer 103, and the lower connecting element 105 and the bottom electrode 110 are located in the opening.

In some embodiments, the lower connection element 105 comprises a metal, a metal compound, or a combination thereof, such as titanium, tantalum, tungsten, aluminum, copper, molybdenum, platinum, titanium nitride, tantalum carbide, tantalum silicon nitride, tungsten nitride, molybdenum oxynitride, ruthenium oxide, titanium aluminum nitride, tantalum carbonitride, other suitable materials, or a combination thereof. In some embodiments, the bottom electrode 110 is coupled to an active device (not shown) through the lower connecting element 105. In several embodiments, the bottom electrode 110 comprises tungsten, titanium nitride, tantalum nitride, titanium aluminum nitride, tantalum aluminum nitride, or combinations thereof.

In some embodiments, as shown in FIG. 1, the dielectric layer 103, the lower connecting element 105 and the bottom electrode 110 are formed first, and then the dielectric layer 112 is formed over the bottom electrode 110 and the dielectric layer 103. In some embodiments, the dielectric layer 112 comprises an oxide, nitride, oxynitride or combinations thereof, such as silicon oxide, silicon nitride, silicon oxynitride or combinations thereof. In some embodiments, the dielectric layer 112 is made of silicon nitride, but is not limited thereto, and may be made of other dielectric materials, such as silicon oxide. In some embodiments, the dielectric layer 112 is formed using a thin film deposition process. In some embodiments, the thickness of the dielectric layer 112 is between 500 nm and 1500 nm.

In some embodiments, after forming dielectric layer 112, an isolation material is deposited over dielectric layer 112. In some embodiments, the isolation material comprises an oxide, nitride, oxynitride or combination thereof, such as silicon oxide, silicon nitride, silicon oxynitride or combination thereof. In some embodiments, the isolation material comprises silicon oxide, but is not limited thereto. Then, a photolithography process is performed on the isolation material to form the isolation layer 114 having an opening O1, as shown in fig. 1. In some embodiments, the width of the opening O1 is greater than or equal to the width of the bottom electrode 110. In some embodiments, the ratio of the thickness of the isolation layer 114 to the thickness of the dielectric layer 112 is between 1.3 and 2.

In some embodiments, polysilicon layer 116 is then conformally formed within opening O1, as shown in fig. 1. In some embodiments, polysilicon layer 116 is formed by chemical vapor deposition. The polysilicon layer 116 may also be formed by atomic layer deposition, physical deposition, low pressure chemical vapor deposition, or high density plasma chemical vapor deposition. In some embodiments, polysilicon layer 116 has void V1 (also referred to as a keyhole structure) located within opening O1. The keyhole structure may then be transferred down to dielectric layer 112.

Then, as shown in fig. 1 to 2, a hole is formed through the polysilicon layer 116 and the dielectric layer 112 to expose the upper surface of the bottom electrode 110. In detail, as shown in fig. 2, a first hole H1 and a second hole H2 are formed through the polysilicon layer 116 and the underlying dielectric layer 112, respectively. The second hole H2 is located below the first hole H1. In some embodiments, the first hole H1 and the second hole H2 are formed through the polysilicon layer 116 and the dielectric layer 112 by an etching process, which includes reactive ion etching, high density plasma etching or a combination thereof.

In some embodiments, as shown in fig. 2, the maximum width of the first hole H1 is greater than the maximum width of the second hole H2. In some embodiments, the width of the first hole H1 is less than the width of the polysilicon layer 116. In some embodiments, the first hole H1 has a wide region H11 and a narrow region H12, and the narrow region H12 is located below the wide region H11 and connects the second holes H2. In some embodiments, the wide region H11 is funnel-shaped, and the narrow region H12 and the second hole H2 are column-shaped. In some embodiments, wide region H11 has an angle of rotation θ that is greater than 89 degrees. In some embodiments, the width of the second hole H2 is between 10 nm and 30 nm.

As shown in fig. 2 to 3, a passivation layer 118 is formed in the first hole H1 and the second hole H2 and above the polysilicon layer 116. In some embodiments, the protective layer 118 comprises an inorganic material, an organic material, or a combination thereof. The protective layer 118 comprising an inorganic material may be formed, for example, by chemical vapor deposition or other suitable deposition processes. The inorganic material may comprise silicon carbide, a silicate salt, a siloxane, Spin-On Glass (Spin-On Glass), or a combination thereof. The protective layer 118 comprising an organic material may be formed, for example, by spin-on coating or other suitable coating processes. The organic material may comprise a photoresist.

As shown in fig. 3 to 4, a dry etching process or a chemical mechanical polishing process is performed on the passivation layer 118 to expose the isolation layer 114 and the polysilicon layer 116. In some embodiments, the dry etching process uses a process gas comprising argon, oxygen, trifluoromethane, carbon tetrafluoride, or combinations thereof. In some embodiments, the CMP process uses a slurry for CMP of the passivation layer 118. In some embodiments, the upper surface of the exposed isolation layer 114 is coplanar or substantially coplanar with the upper surface of the exposed polysilicon layer 116. In some embodiments, the upper surface of the exposed polysilicon layer 116 is coplanar or substantially coplanar with the upper surface of the protection layer 118 located within the first hole H1.

As shown in fig. 4 to 5, a chemical mechanical polishing process is performed to remove the exposed isolation layer 114, the exposed polysilicon layer 116 and the passivation layer 118 in the first hole H1, expose the dielectric layer 112, and leave the passivation layer 118 in the second hole H2. The protection layer 118 remaining in the second hole H2 can protect the second hole H2 from the change in the size of the second hole H2. In some embodiments, the CMP process is performed using a slurry that is used to CMP the isolation layer 114. In some embodiments, the CMP process is performed using only the slurry used to CMP the isolation layer 114. This is because the polysilicon layer 116 and the passivation layer 118 lose their supportable sidewalls during the cmp process of the isolation layer 114, so that the protruding polysilicon layer 116 and the passivation layer 118 are automatically stripped during the process. Thus, no extra slurry is required for chemical mechanical polishing the polysilicon layer 116 and/or the passivation layer 118.

As shown in fig. 5 to 6, the passivation layer 118 in the second hole H2 is removed to expose the second hole H2 and the upper surface of the bottom electrode 110. In some embodiments, the passivation layer 118 in the second hole H2 is removed by dry etching, wet etching or a combination thereof. In some embodiments, the passivation layer 118 in the second hole H2 is removed by dry etching. In some embodiments, the processing gas used in the dry etching process for removing the passivation layer 118 in the second hole H2 includes argon, oxygen, trifluoromethane, carbon tetrafluoride, or a combination thereof.

As shown in fig. 6-7, the heating material 120' is deposited into the second hole H2. In some embodiments, a heating material 120' is also deposited over the dielectric layer 112, as shown in FIG. 7. In some embodiments, the heating material 120' is formed by atomic layer deposition, physical vapor deposition, or a combination thereof. In some embodiments, the heating material 120' comprises titanium nitride, tantalum nitride, titanium, or combinations thereof. One or more layers of heating material may be formed. In some embodiments, three layers of heating material are formed, from bottom to top, tantalum nitride, titanium nitride, and tantalum nitride.

It is noted that the isolation layer 114 has been removed as shown in fig. 4-5, and thus, as shown in fig. 6-7, it is relatively easy to deposit the heating material 120' into the second hole H2 because the ratio of the depth (i.e., the thickness of the dielectric layer 112) to the width (i.e., the width of the second hole H2) of the hole filling process is small. In some embodiments, the aspect ratio of the second hole H2 is between 2.5 and 3.5. If the isolation layer 114 is not removed as shown in fig. 4, the subsequent deposition of the heating material 120' into the second hole H2 is more difficult because the ratio of the depth (i.e., the sum of the thickness of the isolation layer 114 and the thickness of the dielectric layer 112) to the width (i.e., the width of the second hole H2) of the hole filling process is too large.

As shown in fig. 7-8, another cmp process is performed to remove the heating material 120' over the dielectric layer 112 and expose the dielectric layer 112 to form the heater 120 in the dielectric layer 112. The top surface of heater 120 is flush with the top surface of dielectric layer 112. In some embodiments, the chemical mechanical polishing process described herein may use only the slurry used to remove the heating material 120' (containing metal).

As shown in fig. 8-9, a phase change material 130 'and a top electrode material 130' are formed over the heater 120 to electrically connect to the heater 120. In some embodiments, a phase change material 130 ' is formed blanket over the dielectric layer 112 and a top electrode material 140 ' is formed blanket over the phase change material 130 ', followed by photolithography and etching to form the phase change element 130 and the top electrode 140, as shown in fig. 9-10. In some embodiments, the top electrode 140 comprises titanium, titanium nitride, tantalum nitride, titanium aluminum nitride, tantalum aluminum nitride, or combinations thereof.

As can be seen from the above, the method for fabricating a phase change memory according to the present disclosure removes the polysilicon layer by other process steps (see fig. 3 to 5) instead of directly removing the polysilicon layer using a tetramethylammonium hydroxide solution. Therefore, the danger caused by using the tetramethylammonium hydroxide solution and the environmental pollution caused by the tetramethylammonium hydroxide solution can be avoided, and the damage of the second hole can be avoided through the protective layer positioned in the second hole, so that the second hole has good dimensional stability.

On the other hand, referring to fig. 4-7, since the isolation layer is removed first, the process of depositing the phase change material into the second hole is relatively easy, which is advantageous for manufacturing the second hole (also called contact) with smaller size in the future.

The foregoing briefly addresses the features of the various embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of fabricating a phase change memory, comprising:

forming a structure comprising:

a bottom electrode;

a dielectric layer located above the bottom electrode;

an isolation layer located above the dielectric layer and having an opening penetrating through the isolation layer; and

a polysilicon layer located in the opening;

forming a first hole and a second hole respectively penetrating through the polysilicon layer and the dielectric layer, wherein the second hole is positioned below the first hole;

forming a protective layer in the first hole and the second hole and above the polysilicon layer;

dry etching the protective layer to expose the isolation layer and the polysilicon layer;

performing a chemical mechanical polishing process to remove the exposed isolation layer, the exposed polysilicon layer and the protective layer in the first hole, expose the dielectric layer and leave the protective layer in the second hole, wherein the step of performing the chemical mechanical polishing process is to use only a polishing slurry for chemically and mechanically polishing the isolation layer;

removing the protective layer in the second hole to expose the second hole; and

depositing a heating material into the second hole.

2. A method of manufacturing a phase change memory as claimed in claim 1, wherein said polysilicon layer of said structure has a void located within said opening.

3. A method of manufacturing a phase change memory as claimed in claim 1, wherein the exposed upper surface of said isolation layer is coplanar or substantially coplanar with the exposed upper surface of said polysilicon layer.

4. The method of claim 1, wherein an upper surface of the exposed polysilicon layer is coplanar or substantially coplanar with an upper surface of the passivation layer within the first hole.

5. A method of manufacturing a phase change memory as claimed in claim 1, wherein the step of removing the passivation layer in the second hole is performed by dry etching, wet etching or a combination thereof.

6. A method of manufacturing a phase change memory as claimed in claim 1 wherein said step of depositing said heating material further comprises depositing said heating material over said dielectric layer.

7. A method of manufacturing a phase change memory as claimed in claim 6, further comprising:

after the step of depositing the heating material, another chemical mechanical polishing process is performed to remove the heating material over the dielectric layer and expose the dielectric layer to form a heater in the dielectric layer, wherein a top surface of the heater is flush with a top surface of the dielectric layer.

8. A method of fabricating a phase change memory as claimed in claim 7, further comprising:

a top electrode and a phase change element are formed over the heater.