CN107978337B - High-speed circuit structure suitable for automatic test of random access memory and test method thereof - Google Patents
High-speed circuit structure suitable for automatic test of random access memory and test method thereof Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
- G11C29/16—Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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Abstract
The invention discloses a high-speed circuit structure suitable for automatic test of a random access memory and a test method thereof, wherein the structure comprises the following components: a phase-locked loop unit; a clock generation unit; the state machine control unit is used for internal state machine control, converting an external instruction into an internal operation time sequence, generating an internal control signal to control external communication and configuration information, and transmitting related information to the internal unit; the pipeline driving unit is used for realizing pipeline control of the operation of other units according to the requirement of an external instruction; the control signal generating unit is used for configuring an enable signal and a read-write control signal of the memory; an address signal generating unit for generating an address signal for operating the memory to the memory; a data result processing unit for generating data written in the memory; the output data processing unit is used for comparing the output data and the written data of the memory; and the result recording unit is used for recording and outputting the comparison result of the output data processing unit.
Description
Technical Field
The invention relates to the technical field of memory test, in particular to a high-speed circuit structure suitable for automatic test of a random access memory and a test method thereof.
Background
The testability design of various memories in an SOC (System-on-a-Chip) Chip is a key design work, and a self-test circuit for realizing the function is an important component of a modern SOC Chip and plays a key role in reducing the test cost and improving the analysis capability of the memory failure problem. For different memory types or different test requirements, different test algorithms can be adopted by the self-test circuit, a common algorithm is a MARCH algorithm, and the MARCH algorithm can be divided into 4N, 15N, 22N and the like according to different operation processing times of the memory. Different kinds of memory defect types existing in the memory can be identified through different MARCH algorithms, so that the specific process failure reason can be determined. In most applications, March4N (ALL0/ALL1 and CKBD/ICKBD), 15N and 22N are selected as a test algorithm of a memory, common process defects can be screened out, and therefore chip product reliability is improved.
At present, the general process of memory testability design is as follows: firstly, determining the failure type in the production process to be evaluated according to the information such as the type, the structure, the capacity, the bit width and the like of a memory, thereby determining the type of a test algorithm to be used, realizing the test algorithm through a circuit and integrating the test algorithm into an independent test circuit. Meanwhile, as the performance of the chip is improved, the evaluation of the read-write speed of the memory is also a requirement for the self-test circuit. A typical memory self-test circuit (MBIST) is connected to the memory DUT to be tested via a memory enable signal EN, a read/write control signal WE, address signals ADR [ WA-1:0], data signals D [ WD-1:0] (input) and data signals Q [ WD-1:0] (output), as shown in FIG. 1. However, the disadvantages of conventional design for testability are: the custom-designed test algorithm has long development period, large verification amount and high cost; the test circuit solidifies test excitation, and cannot replace the test vector in time according to the encountered problems, so that possible failure reasons beyond expectation cannot be judged; through module expansion, the test circuit is huge, and the chip cost is influenced. Therefore, there is a need for a self-test circuit that is compatible with multiple vector tests and performance evaluations.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a high-speed circuit structure suitable for automatic test of a random access memory and a test method thereof.
To achieve the above and other objects, the present invention provides a high-speed circuit structure suitable for automatic testing of random access memory, comprising:
a phase-locked loop unit for generating an internal clock;
the clock generating unit is used for converting the internal clock generated by the phase-locked loop unit into an internal operation clock and a data capturing clock;
the state machine control unit is used for controlling an internal state machine, converting an external instruction into an internal operation time sequence, generating an internal control signal to control external communication and configuration information, and transmitting related information to the internal unit;
the pipeline driving unit is used for realizing the operation pipeline control of the data signal generating unit, the address signal generating unit, the control signal generating unit and the output data processing unit according to the requirement of an external instruction;
the control signal generating unit is used for configuring an enable signal EN and a read-write control signal WE of the memory;
an address signal generating unit for generating an address signal ADR [ WA-1:0] for operating the memory and transmitting the address signal ADR [ WA-1:0] to the memory;
a data result processing unit for generating data D [ WD-1:0] written to the memory;
an output data processing unit for comparing the output data Q [ WD-1:0] and the write data D [ WD-1:0] of the memory, thereby providing result comparison reference information;
and the result recording unit is used for recording the comparison result of the output data processing unit and providing the comparison result to the outside of the chip.
Further, the state machine control unit generates an internal control signal according to the enable signal CE and the configuration signal CONF to control external communication and configuration information, and switches among the IDLE state IDLE, the test state RUN, and the feedback state RESP.
Further, when an enable signal CE is received to be 1, the state machine control unit controls the state machine to switch from an IDLE state IDLE to a test state RUN, the system automatically sends out test excitation to the memory internally according to a configuration signal CONF and compares the output result of the memory, and when the test is finished, the state machine control unit controls the state machine to switch to a feedback state RESP and feeds back the test result to the outside; when the enable signal CE is deactivated in the test state RUN and the feedback state RESP, the feedback signal is deactivated and the state machine resumes the initial IDLE state.
Further, after the test is completed, when the configuration signal CONF is 0 in the feedback state RESP, if the feedback signal FBK output by the result recording unit is 0, the operation is normal, otherwise, an error occurs.
Further, the test is performed by different MARCH algorithms through the configuration signal CONF ═ 4/5/6/7, and the error number of each test item is checked according to the feedback signal FBK output by the result recording unit.
Furthermore, the pipeline driving unit adopts a pipeline mode to read and write the memory and compare the results.
Further, the operation of the pipeline mode on the memory can be divided into three stages of operand generation, memory operation and read result comparison.
Further, the operand generation is designed in a 3-stage pipeline mode, the memory operation is completed by 1 cycle, and the read result comparison is designed in a 3-stage pipeline mode.
Further, the pipeline driving unit controls other modules following the steps of:
(1) initializing internal registers im and iop;
(2) judging whether the MD [ im ] value is 1, if so, enabling the address module to initialize the address to be all0, otherwise, setting the address to be all 1;
(3) judging the data of OP [ im ] [ iop ]:
when MD [ im ] ═ 1, when OP [ im ] [ iop ] [0] is 1, the control signal generation unit enables the write enable signal WE to be set to be 1, and otherwise, the write enable signal WE is set to be 0;
when MD [ im ] is equal to 0, when the checkerboard flag MCK is 0, the checkerboard flag MCK is a standard March algorithm, if OP [ im ] [ iop ] [1] is 1, the data control module sets D to be all1, otherwise, sets all 0; when the checkerboard flag MCK is 1, dividing the address into a sub-line address BADR and a bit line address WADR, combining an internal sub-line and a bit line combination operation, if OP [ im ] [ iop ] [1] is 1, setting data D to be 1 when BADR [0] is equal to WADR [0], otherwise, setting data D to be 0; if OP [ im ] [ iop ] [1] is 0, when BADR [0] is equal to WADR [0], setting data D to be 0, otherwise, setting data D to be 1;
(4) the clock generation unit generates a memory operation clock signal;
(5) after judging the MD [ im ] value, judging whether the address is all0 or all1, if not, reducing or increasing the address by 1, and continuing the steps (3) and (4);
(6) if the address reaches all0 or all1, judging whether the iop is still less than OPC [ im ], if so, automatically increasing the iop by 1, and repeating the steps (2) to (5);
(7) if iop is equal to OPC [ im ], indicating that the current March operation is finished, judging whether im is smaller than MC, if so, self-increasing 1 by im, repeating (2) to (6), and continuing the next March calculation;
(8) if im is equal to MC, the March algorithm is completely finished, and the current test is exited.
In order to achieve the above object, the present invention further provides a method for testing a high-speed circuit structure suitable for automatic testing of a random access memory, comprising the steps of:
the method comprises the following steps that firstly, a state machine control unit is used for controlling an internal state machine, an external instruction is converted into an internal operation time sequence, an internal control signal is generated to control external communication and configuration information, and relevant information is transmitted to an internal unit;
step two, the pipeline driving unit realizes the operation pipeline control of the data signal generating unit, the address signal generating unit, the control signal generating unit and the output data processing unit according to the external instruction requirement;
and step three, the data signal generating unit, the address signal generating unit, the control signal generating unit and the output data processing unit realize the automatic test of the memory under the control of the state machine control unit and the pipeline driving unit, and the test result is output through the result recording unit.
Compared with the prior art, the high-speed circuit structure suitable for the automatic test of the random access memory and the test method thereof can realize the continuity test and the configurable automatic test of the random access memory by configuring the MARCH algorithm, enhance the flexibility of self test and judge various process defects of the random access memory according to the adjusted test scheme.
Drawings
FIG. 1 is a prior art connection diagram of a self-test circuit;
FIG. 2 is a circuit diagram of a high-speed circuit structure suitable for automatic testing of random access memory according to the present invention;
FIG. 3 is a diagram illustrating state switching of a state machine control unit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of internal control logic in an embodiment of the present invention;
FIG. 5 is a schematic diagram of a memory pipeline design according to an embodiment of the present invention;
FIG. 6 is a diagram of an operand generation pipeline in an embodiment of the present invention;
FIG. 7 is a logic diagram for operand generation in accordance with an embodiment of the present invention;
FIG. 8 is a flow chart of the steps of a method for testing a high speed circuit structure suitable for automatic testing of random access memories according to the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
Before the present invention is introduced, a common representation method of the MARCH algorithm adopted in the present invention is explained: the basic element of the MARCH algorithm, called MARCH element (hereinafter abbreviated ME), is a single traversal of all memory cells of the memory. According to the traversal direction of the address, each ME can be divided into three types of forward traversal, reverse traversal and traversal in any direction, wherein any direction can be regarded as forward or reverse address traversal arbitrarily selected for the ME element. For each address, each ME operation comprises a series of operations (hereinafter OP) for a single address, which may be generally referred to as write 0, read 0, write 1, read 1 (hereinafter labeled w0, r0, w1, r 1). The labeling method of MARCH algorithm is as follows: the algorithm is contained by braces { … }, each ME uses comma intervals, the ME elements are represented in the form ↓ (…), where ↓representsthe addressing order, which includes ↓ (forward traversal), ↓ (reverse traversal), and
(traversal in any direction), within the parenthesis (…) is a series of combined operations of OP, including w0 (write 0), w1 (write 1), r0 (read 0), andr1 (read 1).
FIG. 2 is a circuit diagram of a high-speed circuit structure suitable for automatic testing of random access memory according to the present invention. As shown in fig. 2, a high-speed circuit structure suitable for automatic testing of random access memory according to the present invention comprises: a phase-locked loop unit (PLL)10, a clock generation unit (CKG)20, a state machine control unit (FSM)30, a pipeline driving unit (PD)40, a data signal generation unit (DG)50, an address signal generation unit (AG)60, a control signal generation unit (CG)70, an output data processing unit (DC)80, and a result recording unit (RM) 90.
Wherein a phase locked loop unit (PLL)10 is used to generate an internal clock; a clock generation unit (CKG)20 for converting an internal clock generated by the PLL into an internal operation clock and a data capture clock; a state machine control unit (FSM)30, which is a controller for internal state machine control, and converts an external instruction into an internal operation timing, generates internal control signals external communication and configuration information, and transmits related information to the internal unit; the pipeline driving unit (PD)40 is used to implement operation pipeline control of the data signal generating unit (DG)50, the address signal generating unit (AG)60, the control signal generating unit (CG)70, the output data processing unit (DC)80 according to the external instruction requirement, thereby increasing the processing speed; a control signal generation unit (CG)70 for configuring an enable signal EN and a read/write control signal WE of the memory; an address signal generation unit (AG)60 for generating an address signal ADR [ WA-1:0] for memory operations and transmitting to the memory; a data result processing unit (DG)50 for generating data D [ WD-1:0] to be written to the memory; an output data processing unit (DC)80 for comparing the output data Q [ WD-1:0] and the write data D [ WD-1:0] of the memory, thereby providing result comparison reference information; the result recording unit (RM)90 is used to record the comparison result of the output data processing unit (DC)80 and provide it to the outside of the chip.
As shown in fig. 3, the state machine control unit 30 of the present invention has 3 states, which are an IDLE state IDLE, a test state RUN, and a feedback state RESP. When the mobile terminal is in the IDLE state IDLE, the inside is in a waiting state and does not do any operation; when receiving the enable signal CE equal to 1, the state machine control unit 30 controls the state machine to switch from the IDLE state IDLE to the test state RUN, and the system automatically sends out a test stimulus to the memory internally according to the configuration signal CONF and compares the result with the memory to output the result. When the test is finished, the state machine control unit 30 controls the state machine to switch to the feedback state RESP, and feeds back the test result to the outside. When the enable signal is deasserted (CE ═ 0) at the test state RUN and the feedback state RESP, the feedback signal outputs 0 and the state machine restores the initial IDLE state. When the enable signal is high, when the enable signal is in a test state RUN, the feedback signal is 1, the running state is identified, the test is completed, when the enable signal is still high, the enable signal is in a feedback state RESP, when the configuration signal CONF is 0, if the feedback signal FBK is 0, the operation is normal, and if the feedback signal FBK is 2, an error occurs; when the CONF is adjusted to 4/5/6/7, the number of errors per test item can be checked correspondingly.
FIG. 4 is a diagram of the internal automatic test logic design of the present invention. When the enable signal CE is set to '1', the test state RUN is entered, and the configuration signal CONF is first determined as follows:
when a configuration signal CONF is 0/4, starting an All0/All1 test (a March algorithm indicates { [ (w0), [ (r0), [ (w1), ] and ] (r1) }), judging a test result after the All0/All1 test is completed, recording failure times and a current test vector when failure occurs, judging the failure times when the All0/All1 test is completed, switching to a feedback state RESP when the failure times reaches an upper storage limit, feeding back test failure information to the outside, judging the configuration signal CONF again when the All0/All1 test is passed, and switching to the feedback state RESP if the configuration signal CONF is 4 (performing the All0/All1 test alone), and feeding back test success information to the outside;
if the configuration signal CONF is not 4, automatically testing the checkerboard and the inverse checkerboard CKBD/ICKBD, namely writing 0 'or 1' cross data into word lines and bit lines of the memory, judging test results after the checkerboard and inverse checkerboard CKBD/ICKBD test is finished, recording failure times and current test vectors when failure occurs, judging the failure times when the checkerboard and inverse checkerboard CKBD/ICKBD test is finished, switching to a feedback state RESP when the failure times record reaches an upper storage limit, feeding back test failure information to the outside, judging the configuration signal CONF again when the checkerboard and inverse checkerboard CKBD/ICKBD test is passed, and switching to the feedback state RESP and feeding back test success information to the outside if the configuration signal CONF is 5 (singly carrying out the checkerboard and inverse checkerboard CKBD/ICKBD test);
if the configuration signal CONF is not 5, the March15N test is automatically carried out, namely March
Judging a test result after the March15N test is finished, recording failure times and a current test vector when the March15N test is failed, judging the failure times when the March15N test is finished, switching to a feedback state RESP when the failure times record reaches a storage upper limit, feeding back test failure information to the outside, judging a configuration signal CONF again when the March15N test is passed, and switching to the feedback state RESP if the configuration signal CONF is 6 (performing the March15N test independently) and feeding back test success information to the outside;
if the configuration signal CONF is not 6, the March 22N test is automatically performed, i.e.
And after the March 22N test is finished, judging the test result, recording failure times and a current test vector when the March 22N test is failed, judging the failure times when the March 22N test is finished, switching to a feedback state RESP when the failure times record reaches a storage upper limit, feeding back test information to the outside, and switching to the feedback state RESP when the March 22N test passes, and feeding back test success information to the outside.
When the configuration signal CONF is 1/5 or 2/6, the previous 1 item or the previous 2 item can be skipped to perform the continuous test respectively, that is, when the configuration signal CONF is not 0/4, whether 1/5 is determined, if 1/5, the previous 1 item is skipped to start from the checkerboard and inverse checkerboard CKBD/ICKBD tests is determined, if not 1/5, whether 2/6 is determined, if yes, the previous 2 item is skipped to start from the March15N test, otherwise, the previous 3 item is skipped to directly perform the March 22N test. When the CONF is 4/5/6/7, All0/All1, CKBD/ICKBD, March15N and March 22N tests can be performed separately, increasing the flexibility of the test.
The invention adopts a pipeline mode to read and write the memory and compare the results, and the pipeline design is shown in figure 5. Operations on the memory can be divided into an operand generation stage (READ/WRITE operand, ROP/WOP), a memory operation (memory READ/WRITE operation, READ/WRITE), a READ result comparison 3 stages: (1) the operand generation is designed in a 3-stage pipeline mode, as shown in fig. 6, specifically, the operand generation is divided into address calculation ADRC, March/OP information calculation MOPC and operand GOP generation 3 stages, the operation signal generation can be completed once in 3 cycles, and 1 batch of operation signals can be output per cycle; (2) the memory operation is completed using 1 cycle; (3) and the read result comparison adopts 3-level pipelining design, which comprises data comparison COMP, result collection COL and comparison result record RS, the data are compared one by one according to bit groups, and a final result is obtained by adopting pipelining mode bit. The invention adopts the full-flow design, improves the overall design performance and meets the application requirement of performance test and evaluation of the high-speed memory.
The module task assignment of the present invention is shown in table 1:
TABLE 1 Module task Allocation
The address signal generating unit is responsible for address calculation and generation of an operation address; the pipeline driving module is responsible for information calculation of March/OP, generation of a memory clock and operation time sequence, and an operation data generation task and an operation signal (enabling signal) generation task are respectively responsible for running by the data signal generation unit and the control signal generation unit; the temporary storage task, the result comparison task and the result collection task of the output data of the memory are taken charge of by the output data processing unit; and sending the comparison result to a result recording unit for data recording.
The operating logic for the memory may be represented as shown in fig. 7.
When starting the test of the memory, the pipeline driving unit controls the other modules following the following steps:
(1) initializing internal registers im and iop: im is 0, iop is 0;
(2) judging whether the value of the March operation direction MD [ im ] is 1 or not, if so, enabling the address module to initialize the address to be all 0(ADR [ + ] -1 'b 0), otherwise, setting the address to be all 1(ADR [ + ] -1' b 1);
(3) judging the data of an operand OP [ im ] [ iop ]:
when MD [ im ] ═ 1, when OP [ im ] [ iop ] [0] is 1, the control signal generation unit makes the write enable signal WE set to 1(WE ═ 1 'b 1), otherwise to 0(WE ═ 1' b 0).
When the flag bit MCK is 0 when MD [ im ] ═ 0, the standard March algorithm is adopted, if OP [ im ] [ iop ] [1] is 1, the data control module sets D to be all 1(D [ + ] ═ 1 'b 1), otherwise, sets all 0(D [ ] [ ═ 1' b 0);
when the checkerboard flag MCK is 1, dividing the address into a sub-line address BADR and a bit line address WADR (configured according to a memory), combining an internal sub-line and a bit line for combination operation, if OP [ im ] [ iop ] [1] is 1, the BADR [0] is equal to the WADR [0], setting data D to be 1, otherwise, setting the data D to be 0; if OP [ im ] [ iop ] [1] is 0, when BADR [0] is equal to WADR [0], setting data D to be 0, otherwise, setting data D to be 1;
(4) the clock generation unit generates a memory operation clock signal (GEN _ SRAM _ CK);
(5) after judging the MD [ im ] value, judging whether the address is all0 or all1, if not, reducing or increasing the address by 1, and continuing the steps (3) and (4);
(6) if the address reaches all0 or all1, judging whether the iop is still less than the operation quantity OPC [ im ] of the March elements, if so, automatically increasing the iop by 1, and repeating the steps (2) to (5);
(7) if iop is equal to OPC [ im ], indicating that the current March operation is finished, judging whether im is smaller than MC, if so, self-increasing 1 by im, repeating (2) to (6), and continuing the next March calculation;
(8) if im is equal to MC, the March algorithm is completely finished, and the current test is exited.
The method can meet the requirements of several algorithms adopted in the invention through internal data configuration, can be suitable for more complex March algorithms through expansion, and is suitable for wider March test application. A plurality of flag bits are arranged inside:
(1) march algorithm general flag: march operand MC, checkerboard flag MCK
(2) March operation direction configuration bit: the number of the MD [ MC-1:0] is MC, and when the number of the MD is 1, the addresses are increased one by one from small; when the address is 0, the addresses are reduced from large one by one;
(3) the number of March operations: OPC [ MC-1:0], MC in total, wherein each OPC value is equal to the operation times of the current March on each address;
(4) OP operation configuration: OP, each March has 1 or more OP elements, each OP comprises 2 bits, and the 0 th bit is used for marking that the current operation is writing or reading; the 1 st bit is used for marking data, and the marks are written into all1 or all 0; and in combination with the checkerboard flag MCK, the write-in values of the memory for distinguishing the word line and the bit line can be realized.
The invention adopts the design of an internal integrated configuration method, and the configuration of each algorithm in operation is shown in a table 2.
Table 2 test parameter configuration
The invention is illustrated below by a specific application:
in application, for example, a 320-bit-wide and 12-bit address SRAM (word line address bit-wide is 6) needs to be tested, and only the data bit-wide parameter WD in the circuit parameters needs to be set to 320, the address bit-wide WADR is set to 12, and the word line bit-wide parameter is set to 6, and the corresponding test circuit can be implemented through a general physical implementation process of a digital chip. In the actual test process, the CONF is set to be 0, the enable signal is set to be 1, and the SRAM can be continuously tested. After completion, the test results are read by FBK.
FIG. 8 is a flow chart of the steps of a method for testing a high speed circuit structure suitable for automatic testing of random access memories according to the present invention. As shown in fig. 8, the method for testing a high-speed circuit structure suitable for automatic testing of a random access memory according to the present invention comprises the following steps:
and 803, the data signal generating unit, the address signal generating unit, the control signal generating unit and the output data processing unit realize the automatic test of the memory under the control of the state machine control unit and the pipeline driving unit, and the result recording unit outputs the test result.
Specifically, in step 801, the state machine control unit has 3 states, which are IDLE state IDLE, test state RUN, and feedback state RESP. When the mobile terminal is in the IDLE state IDLE, the inside is in a waiting state and does not do any operation; when the enable signal CE is 1, the state machine control unit controls the state machine to be switched from the IDLE state IDLE to the test state RUN, and the system automatically sends out test excitation to the memory and compares the test excitation with the memory to output a result according to the configuration signal CONF. When the test is finished, the state machine control unit 30 controls the state machine to switch to the feedback state RESP, and feeds back the test result to the outside. When the enable signal is deasserted (CE ═ 0) at the time of testing the state RUN and the feedback state RESP, the feedback signal is deasserted, and the state machine restores the initial IDLE state. In a test state RUN, a feedback signal is 1 to identify an operation state, when a test is completed and in a feedback state RESP, when a configuration signal CONF is 0, if a feedback signal FBK is 0, the operation is normal, and if the feedback signal FBK is 2, an error occurs; by CONF 4/5/6/7, the number of errors per test item can be checked.
Specifically, when the enable signal CE is set to '1', the test state RUN is entered, and the configuration signal CONF is first determined as follows:
when a configuration signal CONF is 0/4, starting an All0/All1 test (a March algorithm indicates { [ (w0), [ (r0), [ (w1), ] and ] (r1) }), judging a test result after the All0/All1 test is completed, recording failure times and a current test vector when failure occurs, judging the failure times when the All0/All1 test is completed, switching to a feedback state RESP when the failure times reaches an upper storage limit, feeding back test failure information to the outside, judging the configuration signal CONF again when the All0/All1 test is passed, and switching to the feedback state RESP if the configuration signal CONF is 4 (performing the All0/All1 test alone), and feeding back test success information to the outside;
if the configuration signal CONF is not 4, automatically testing the checkerboard and the inverse checkerboard CKBD/ICKBD, namely writing 0 'or 1' cross data into word lines and bit lines of the memory, judging test results after the checkerboard and inverse checkerboard CKBD/ICKBD test is finished, recording failure times and current test vectors when failure occurs, judging the failure times when the checkerboard and inverse checkerboard CKBD/ICKBD test is finished, switching to a feedback state RESP when the failure times record reaches an upper storage limit, feeding back test failure information to the outside, judging the configuration signal CONF again when the checkerboard and inverse checkerboard CKBD/ICKBD test is passed, and switching to the feedback state RESP and feeding back test success information to the outside if the configuration signal CONF is 5 (singly carrying out the checkerboard and inverse checkerboard CKBD/ICKBD test);
if the configuration signal CONF is not 5, the March15N test is automatically carried out, namely March
After the March15N test is finished, the test result is judged, and when the March15N test is finished, the test result is judgedWhen failure occurs, recording failure times and a current test vector, judging the failure times when the March15N test is finished, switching to a feedback state RESP when the failure times record reaches a storage upper limit, feeding back test failure information to the outside, judging a configuration signal CONF again when the March15N test passes, switching to the feedback state RESP if the configuration signal CONF is 6 (carrying out the March15N test independently), and feeding back test success information to the outside;
if the configuration signal CONF is not 6, the March 22N test is automatically performed, i.e.
And after the March 22N test is finished, judging the test result, recording failure times and a current test vector when the March 22N test is failed, judging the failure times when the March 22N test is finished, switching to a feedback state RESP when the failure times record reaches a storage upper limit, feeding back test information to the outside, and switching to the feedback state RESP when the March 22N test passes, and feeding back test success information to the outside.
When the configuration signal CONF is 1/5 or 2/6, the previous 1 item or the previous 2 item can be skipped to perform the continuous test respectively, that is, when the configuration signal CONF is not 0/4, whether 1/5 is determined, if 1/5, the previous 1 item is skipped to start from the checkerboard and inverse checkerboard CKBD/ICKBD tests is determined, if not 1/5, whether 2/6 is determined, if yes, the previous 2 item is skipped to start from the March15N test, otherwise, the previous 3 item is skipped to directly perform the March 22N test. When the CONF is 4/5/6/7, All0/All1, CKBD/ICKBD, March15N and March 22N tests can be performed separately, increasing the flexibility of the test.
In step 802, the pipeline driving unit performs reading and writing and result comparison on the memory in a pipeline manner, and the pipeline design is shown in fig. 5. Operations on the memory can be divided into an operand generation stage (READ/WRITE operand, ROP/WOP), a memory operation (memory READ/WRITE operation, READ/WRITE), a READ result comparison 3 stages: (1) the operand generation is designed in a 3-stage pipeline mode, as shown in fig. 6, specifically, the operand generation is divided into address calculation ADRC, March/OP information calculation MOPC and operand GOP generation 3 stages, the operation signal generation can be completed once in 3 cycles, and 1 batch of operation signals can be output per cycle; (2) the memory operation is completed using 1 cycle; (3) and the read result comparison adopts 3-level pipelining design, which comprises data comparison COMP, result collection COL and comparison result record RS, the data are compared one by one according to bit groups, and a final result is obtained by adopting pipelining mode bit. The invention adopts the full-flow design, improves the overall design performance and meets the application requirement of performance test and evaluation of the high-speed memory.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (8)
1. A high speed circuit structure suitable for automatic testing of random access memories, comprising:
a phase-locked loop unit for generating an internal clock;
the clock generating unit is used for converting the internal clock generated by the phase-locked loop unit into an internal operation clock and a data capturing clock;
the state machine control unit is used for controlling an internal state machine, converting an external instruction into an internal operation time sequence, generating an internal control signal to control external communication and configuration information, and transmitting related information to the internal unit;
the pipeline driving unit is used for realizing the operation pipeline control of the data signal generating unit, the address signal generating unit, the control signal generating unit and the output data processing unit according to the requirement of an external instruction; the assembly line driving unit adopts an assembly line mode and is configured to realize reading and writing of a memory and result comparison by a MARCH algorithm; the operation of the pipeline mode on the memory can be divided into an operand generation stage, a memory operation stage and a read result comparison stage;
the control signal generating unit is used for configuring an enable signal EN and a read-write control signal WE of the memory;
an address signal generating unit for generating an address signal ADR [ WA-1:0] for operating the memory and transmitting the address signal ADR [ WA-1:0] to the memory;
a data result processing unit for generating data D [ WD-1:0] written to the memory;
an output data processing unit for comparing the output data Q [ WD-1:0] and the write data D [ WD-1:0] of the memory, thereby providing result comparison reference information;
and the result recording unit is used for recording the comparison result of the output data processing unit and providing the comparison result to the outside of the chip.
2. A high-speed circuit structure suitable for automatic testing of random access memories as claimed in claim 1, characterized in that: the state machine control unit generates an internal control signal according to the enable signal CE and the configuration signal CONF to control external communication and configuration information, and switches among an IDLE state IDLE, a test state RUN and a feedback state RESP.
3. A high-speed circuit structure suitable for automatic testing of random access memories as claimed in claim 2, characterized in that: when an enable signal CE is received to be 1, the state machine control unit controls the state machine to be switched from an IDLE state IDLE to a test state RUN, the system automatically sends test excitation to the memory internally according to a configuration signal CONF and compares the output result of the memory, and when the test is finished, the state machine control unit controls the state machine to be switched to a feedback state RESP and feeds the test result back to the outside; when the enable signal CE is deactivated in the test state RUN and the feedback state RESP, the feedback signal is deactivated and the state machine resumes the initial IDLE state.
4. A high-speed circuit structure suitable for automatic testing of random access memories as claimed in claim 3, characterized in that: after the test is finished, when a configuration signal CONF is 0 in a feedback state RESP, if a feedback signal FBK output by the result recording unit is 0, the operation is normal, and otherwise, an error occurs.
5. A high-speed circuit structure suitable for automatic testing of random access memories as claimed in claim 4, characterized in that: the test is performed by different MARCH algorithms through the configuration signal CONF-4/5/6/7, and the error number of each test item is checked according to the feedback signal FBK output by the result recording unit.
6. A high-speed circuit structure suitable for automatic testing of random access memories as claimed in claim 1, characterized in that: the operand generation is designed by adopting a 3-level pipeline mode, the memory operation is completed by using 1 cycle, and the read result comparison is designed by adopting a 3-level pipeline mode.
7. A high-speed circuit configuration suitable for automatic testing of random access memories according to claim 6, characterized in that said pipeline driving unit controls the other modules following the following steps:
(1) initializing internal registers im and iop;
(2) judging whether the MD [ im ] value is 1, if so, enabling the address module to initialize the address to be all0, otherwise, setting the address to be all 1;
(3) judging the data of OP [ im ] [ iop ]:
when MD [ im ] ═ 1, when OP [ im ] [ iop ] [0] is 1, the control signal generation unit enables the write enable signal WE to be set to be 1, and otherwise, the write enable signal WE is set to be 0;
when MD [ im ] is equal to 0, when the checkerboard flag MCK is 0, the checkerboard flag MCK is a standard March algorithm, if OP [ im ] [ iop ] [1] is 1, the data control module sets D to be all1, otherwise, sets all 0; when the checkerboard flag MCK is 1, dividing the address into a sub-line address BADR and a bit line address WADR, combining an internal sub-line and a bit line combination operation, if OP [ im ] [ iop ] [1] is 1, setting data D to be 1 when BADR [0] is equal to WADR [0], otherwise, setting data D to be 0; if OP [ im ] [ iop ] [1] is 0, when BADR [0] is equal to WADR [0], setting data D to be 0, otherwise, setting data D to be 1;
(4) the clock generation unit generates a memory operation clock signal;
(5) after judging the MD [ im ] value, judging whether the address is all0 or all1, if not, reducing or increasing the address by 1, and continuing the steps (3) and (4);
(6) if the address reaches all0 or all1, judging whether the iop is still less than OPC [ im ], if so, automatically increasing the iop by 1, and repeating the steps (2) to (5);
(7) if iop is equal to OPC [ im ], indicating that the current March operation is finished, judging whether im is smaller than MC, if so, self-increasing 1 by im, repeating (2) to (6), and continuing the next March calculation;
(8) if im is equal to MC, the March algorithm is completely finished, and the current test is exited.
8. A method for testing a high-speed circuit structure suitable for automatic random access memory test according to any one of claims 1 to 7, comprising the steps of:
the method comprises the following steps that firstly, a state machine control unit is used for controlling an internal state machine, an external instruction is converted into an internal operation time sequence, an internal control signal is generated to control external communication and configuration information, and relevant information is transmitted to an internal unit;
step two, the pipeline driving unit realizes the operation pipeline control of the data signal generating unit, the address signal generating unit, the control signal generating unit and the output data processing unit according to the external instruction requirement; the assembly line driving unit adopts an assembly line mode and is configured to realize reading and writing of a memory and result comparison by a MARCH algorithm; the operation of the pipeline mode on the memory can be divided into an operand generation stage, a memory operation stage and a read result comparison stage;
and step three, the control signal generating unit, the address signal generating unit, the data result processing unit and the output data processing unit realize the automatic test of the memory under the control of the state machine control unit and the pipeline driving unit, and the result recording unit outputs the test result.
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| KR20210108466A (en) * | 2019-05-05 | 2021-09-02 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | Memory control system with sequence processing unit |
| CN113450867B (en) * | 2020-03-27 | 2022-04-12 | 长鑫存储技术有限公司 | Method for forming database for memory test and memory test method |
| CN113886166A (en) * | 2021-08-31 | 2022-01-04 | 北京时代民芯科技有限公司 | Automatic test circuit for variable bit width memory in programmable logic device |
| CN114035027A (en) * | 2021-11-10 | 2022-02-11 | 成都利普芯微电子有限公司 | MBIST circuit, driving chip, electronic equipment and testing method |
| CN117524287B (en) * | 2024-01-04 | 2024-03-22 | 合肥奎芯集成电路设计有限公司 | Memory chip self-test circuit and memory chip self-test method |
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