CN107731733B - Filling method for groove epitaxy - Google Patents
Filling method for groove epitaxy Download PDFInfo
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- CN107731733B CN107731733B CN201711075799.0A CN201711075799A CN107731733B CN 107731733 B CN107731733 B CN 107731733B CN 201711075799 A CN201711075799 A CN 201711075799A CN 107731733 B CN107731733 B CN 107731733B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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Abstract
the invention discloses a filling method of groove epitaxy, which comprises the following steps: forming a hard mask layer formed by overlapping a first oxide layer, a second nitride layer and a third oxide layer on the surface of the semiconductor substrate; photoetching and defining a forming area of the groove, and etching to form a hard mask layer opening; forming a side wall consisting of a fourth nitride layer on the side surface of the opening of the hard mask layer; etching the semiconductor substrate to form a groove; removing the third oxide layer; forming a sacrificial oxide layer and removing; removing the second nitride layer and the side wall; and carrying out epitaxial growth to form a groove epitaxial layer to fill the groove, and enabling the groove epitaxial layer to grow only on the bottom surface and the side surface of the groove in the epitaxial growth process by utilizing the characteristic that the first oxide layer is not transversely etched. The invention can prevent the epitaxial layers in the adjacent grooves from extending to the outside of the grooves and forming a combined structure, thereby eliminating stress generated by combining the epitaxial layers of the grooves, avoiding dislocation generated by combining the epitaxial layers of the grooves and improving the performance of the device.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for filling a trench extension.
Background
As shown in fig. 1A to fig. 1G, the device structure in each step of the filling method of the existing trench epitaxy is schematically illustrated; taking the epitaxial filling of the trench of the super junction structure as an example for explanation, the existing trench epitaxial filling method includes the following steps:
As shown in fig. 1A, a semiconductor substrate such as a silicon substrate 101 is provided, an N-type epitaxial layer 102 is formed on the surface of the silicon substrate 101, and an oxide layer 103, a nitride layer 104 and an oxide layer 105 are sequentially formed on the surface of the N-type epitaxial layer 102 and stacked to form a hard mask layer; and photoetching and opening the forming area of the groove, and sequentially etching the 3-layer structure of the hard mask layer in the groove forming area to form an opening of the hard mask layer. Take an example of a specific parameter as an example: the thickness of the oxide layer 103 isThe nitride layer 104 has a thickness ofthe oxide layer 105 has a thickness of
As shown in fig. 1B, the trench 201 is formed by etching the N-type epitaxial layer 102 using the hard mask layer as a mask, and the trench of the super junction is also generally called a deep trench due to its large depth. During the etching of the trench 201, the oxide layer 105 may be somewhat worn, for example: the remaining thickness of the oxide layer 105 after etching is
As shown in fig. 1C, the oxide layer 105 is removed. Since the materials of oxide layers 103 and 105 are the same, during the process of removing oxide layer 105, some lateral etching of the side of oxide layer 103 will also occur, as shown by dashed circle 202. The nitride layer 104 is not etched due to the difference between the material of the nitride layer 104 and the oxide layer 105.
As shown in fig. 1D, a sacrificial oxide layer 203 is then formed, for example: the thickness of the sacrificial oxide layer 203 isAs shown in fig. 1E, the sacrificial oxide layer 203 is then removed. Since the material of the sacrificial oxide layer 203 is the same as that of the oxide layer 103, the oxide layer 103 is also etched laterally by a certain amount during the process of etching to remove the sacrificial oxide layer 203. The total laterally etched area of the oxide layer 103 is shown by the dashed circle 204 in fig. 1F. The total lateral etched distance of oxide layer 103 is d1, with d1 being 0.6 microns in one example.
As shown in fig. 1F, after the sacrificial oxide layer 203 is removed, the nitride layer 104 is removed.
As shown in fig. 1G, growth of the P-type epitaxial layer 106 is then performed until the trench 201 is completely filled. Only the in-process structure of the growth of P-type epitaxial layer 106 is shown in fig. 1G. It can be seen that since the oxide layer 103 is laterally etched by a certain distance d1, the N-type epitaxial layer 102 in the region where the outer periphery of the trench 201 has a width d1 is exposed without being protected by the oxide layer 103. Because the epitaxial growth process is to select the growth on the surface of the epitaxial layer and not on the surface of the oxide layer, in this way, during the epitaxial growth, the P-type epitaxial layer 106 will simultaneously grow on the side and bottom surfaces of the trench 201 and the surface of the N-type epitaxial layer 102 outside the trench 201 that is not covered by the oxide layer 103, the P-type epitaxial layer 106 formed on the surface of the N-type epitaxial layer 102 outside the trenches 201 not covered by the oxide layer 103 is thicker than the oxide layer 103, and then extends to the surface of the oxide layer 103 and grows laterally, so that the P-type epitaxial layers 106 in adjacent trenches 201 easily extend on the surface of the oxide layer 103 between the trenches 201 to contact and connect with each other to form an integral structure, such P-type epitaxial layers 106 formed on the oxide layer 103 and laterally contacting and merging with each other are prone to stress and dislocation (dislocation) and ultimately affect the device performance.
disclosure of Invention
The technical problem to be solved by the invention is to provide a filling method of trench epitaxy, which can prevent the epitaxy layer in the adjacent trench from extending to the outside of the trench and forming a merged structure, thereby eliminating stress generated by merging the epitaxy layers of the trench, avoiding dislocation generated by merging the epitaxy layers of the trench and improving the performance of a device.
In order to solve the technical problem, the filling method of the trench epitaxy provided by the invention comprises the following steps:
Step one, forming a hard mask layer formed by overlapping a first oxide layer, a second nitride layer and a third oxide layer on the surface of the semiconductor substrate.
And step two, defining a forming area of the groove by photoetching, and removing the third oxide layer, the second nitride layer and the first oxide layer in the forming area of the groove in sequence by adopting an etching process so as to form a hard mask layer opening.
And step three, forming a side wall consisting of a fourth nitride layer on the side face of the opening of the hard mask layer.
and fourthly, etching the semiconductor substrate at the bottom of the opening of the hard mask layer by taking the hard mask layer as a mask to form the groove.
And fifthly, removing the third oxide layer, and utilizing the side protection of the side wall to ensure that the first oxide layer is not etched transversely in the process of removing the third oxide layer.
And sixthly, forming sacrificial oxide layers on the side surfaces and the bottom surfaces of the grooves, then removing the sacrificial oxide layers, and utilizing the side surface protection of the side walls to ensure that the first oxide layer is not etched transversely in the process of removing the sacrificial oxide layers.
And seventhly, removing the second nitride layer and the side wall at the same time.
And step eight, performing epitaxial growth to form a groove epitaxial layer to fill the groove, and enabling the groove epitaxial layer to grow only on the bottom surface and the side surface of the groove in the epitaxial growth process by utilizing the characteristic that the first oxide layer is not etched transversely.
In a further improvement, in the first step, a first epitaxial layer is formed on the surface of the semiconductor substrate, and the trench is formed in the first epitaxial layer.
in a further improvement, the trench is a superjunction trench.
in a further refinement, the first epitaxial layer has a first conductivity type and the trench epitaxial layer has a second conductivity type.
In a further improvement, the trenches include a plurality of trenches, the trenches form epitaxial layers of the trenches to form second conductive type columns, the first epitaxial layers between the trenches form first conductive type columns, and the first conductive type columns and the second conductive type columns are alternately arranged to form a super junction structure.
The semiconductor substrate is a silicon substrate, the first epitaxial layer and the groove epitaxial layer are silicon epitaxial layers, the first oxide layer and the third oxide layer are silicon dioxide layers, and the second nitride layer and the fourth nitride layer are silicon nitride layers.
The further improvement is that the third step comprises the following sub-steps:
And 31, comprehensively depositing to form the fourth nitride layer.
And 32, performing overall etching on the nitride layer to form the side wall in a self-alignment manner on the side face of the hard mask layer opening.
in a further improvement, the first stepThe thickness of the tetranitride layer is
In a further improvement, the first oxide layer has a thickness ofthe thickness of the second nitride layer isThe thickness of the third oxide layer is
In a further improvement, the third oxide layer is partially consumed during the etching of step four.
The further improvement is that the residual thickness of the third oxide layer after the step four is finished is
In a further improvement, the first conductivity type is N-type and the second conductivity type is P-type.
In a further improvement, the first conductivity type is P-type and the second conductivity type is N-type.
The technical scheme of the invention is specially designed according to the technical problems provided by the invention, and mainly comprises the steps of adding a step of forming a side wall consisting of a fourth nitride layer on the side surface of an opening after the opening of a hard mask layer is formed, so that the first oxide layer of the hard mask layer can be completely surrounded by combining the side wall and a second nitride layer of the hard mask layer, wherein the side wall mainly covers the first oxide layer from the side surface; therefore, in the etching of the third oxide layer of the hard mask layer and the etching of the sacrificial oxide layer, the lateral side of the first oxide layer can not generate transverse etching any more due to the protection of the side wall, and thus after the groove is formed and the nitride layer is removed, the first oxide layer can well cover the surface outside the groove, so that in the process of filling the groove by epitaxy, an epitaxial layer only grows from the lateral side and the bottom surface of the groove, and the surface of the semiconductor substrate outside the groove cannot grow by epitaxy due to the fact that the surface is covered by the first oxide layer.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A-1G are schematic views of a device structure in steps of a conventional filling method for trench epitaxy;
Fig. 2 is a flow chart of a filling method of trench epitaxy according to an embodiment of the invention;
Fig. 3A to fig. 3H are schematic device structures in steps of a filling method for trench epitaxy according to an embodiment of the present invention.
Detailed Description
Fig. 2 is a flow chart of a filling method of trench epitaxy according to an embodiment of the present invention; as shown in fig. 3A to fig. 3H, the method for filling a trench epitaxy according to an embodiment of the present invention is a schematic device structure diagram in each step, and the method for filling a trench epitaxy according to an embodiment of the present invention includes the following steps:
step one, as shown in fig. 3A, a hard mask layer formed by overlapping a first oxide layer 3, a second nitride layer 4, and a third oxide layer 5 is formed on the surface of the semiconductor substrate 1.
In the embodiment of the present invention, a first epitaxial layer 2 is formed on the surface of the semiconductor substrate 1, and a subsequent trench 301 is formed in the first epitaxial layer 2. The trench 301 is a superjunction trench. The first epitaxial layer 2 has a first conductivity type and the subsequent trench epitaxial layer 6 has a second conductivity type.
Preferably, the semiconductor substrate 1 is a silicon substrate, the first epitaxial layer 2 and the subsequent trench epitaxial layer 6 are silicon epitaxial layers, the first oxide layer 3 and the third oxide layer 5 are silicon dioxide layers, and the second nitride layer 4 and the subsequent fourth nitride layer 4a are silicon nitride layers.
taking a specific parameter as an example: the thickness of the first oxide layer 3 isThe thickness of the second nitride layer 4 isThe thickness of the third oxide layer 5 is
Step two, as shown in fig. 3A, defining a formation region of the trench 301 by photolithography, and removing the third oxide layer 5, the second nitride layer 4, and the first oxide layer 3 in the formation region of the trench 301 in sequence by using an etching process to form a hard mask layer opening.
Step three, as shown in fig. 3A, a side wall 4a composed of a fourth nitride layer 4a is formed on the side surface of the hard mask layer opening.
Preferably, the third step includes the following sub-steps:
And 31, comprehensively depositing to form the fourth nitride layer 4 a. The thickness of the fourth nitride layer 4a is
And 32, performing overall etching on the nitride layer to form the side wall 4a in a self-alignment manner on the side face of the hard mask layer opening. Self-alignment here means that no photolithography process is required to form the side walls 4a between the sides of the hard mask layer openings.
Step four, as shown in fig. 3C, the semiconductor substrate 1 at the bottom of the opening of the hard mask layer is etched by using the hard mask layer as a mask to form the trench 301.
And the third oxide layer 5 is partially lost in the etching process of the fourth step. Taking a specific parameter as an example: after the fourth step, the residual thickness of the third oxide layer 5 is
And fifthly, as shown in fig. 3D, removing the third oxide layer 5, and using the side protection of the side wall 4a to prevent the first oxide layer 3 from being etched laterally in the process of removing the third oxide layer 5. The absence of lateral etching of the first oxide layer 3 at this step can be understood in conjunction with the corresponding steps of the prior art method shown in fig. 1C.
Sixthly, as shown in fig. 3E, forming a sacrificial oxide layer 302 on the side surface and the bottom surface of the trench 301; as shown in fig. 3F, the sacrificial oxide layer 302 is removed, and the first oxide layer 3 is not etched laterally during the process of removing the sacrificial oxide layer 302 by using the side protection of the sidewall 4 a. The absence of lateral etching of the first oxide layer 3 at this step can be understood in conjunction with the corresponding steps of the prior art method shown in fig. 1E.
And seventhly, as shown in fig. 3G, removing the second nitride layer 4 and the side wall 4a at the same time.
Step eight, as shown in fig. 3H, performing epitaxial growth to form a trench epitaxial layer 6 to fill the trench 301, and enabling the trench epitaxial layer 6 to grow only on the bottom surface and the side surface of the trench 301 in the epitaxial growth process by using the feature that the first oxide layer 3 is not etched laterally; that is, the surface outside the trench 301 is covered with the first oxide layer 3, so that an epitaxial layer cannot be formed on the surface outside the trench 301.
In this embodiment of the present invention, the trenches 301 include a plurality of second conductive type pillars formed by the trench epitaxial layers 6, first conductive type pillars formed by the first epitaxial layers 2 between the trenches 301, and a super junction structure formed by alternately arranging the first conductive type pillars and the second conductive type pillars.
in the embodiment of the invention, the first conductive type is an N type, and the second conductive type is a P type. In other embodiments can also be: the first conductivity type is P-type and the second conductivity type is N-type.
The technical scheme of the embodiment of the invention is specially designed according to the technical problems provided by the invention, and mainly comprises the steps of adding a step of forming a side wall 4a consisting of a fourth nitride layer 4a on the side surface of an opening after the opening of a hard mask layer is formed, so that the first oxide layer 3 of the hard mask layer can be completely surrounded by combining the side wall 4a and the second nitride layer 4 of the hard mask layer, wherein the side wall 4a mainly covers the first oxide layer 3 from the side surface; thus, in the etching of the third oxide layer 5 of the hard mask layer and the etching of the sacrificial oxide layer 302, the lateral surface of the first oxide layer 3 is protected by the sidewall 4a and thus no further lateral etching occurs, so that, after the formation of the trench 301, and after the removal of both the nitride layers 4 and 4a, the first oxide layer 3 can provide good coverage of the surface outside the trench 301, so that, in the process of epitaxially filling the trench 301, the epitaxial layer 6 grows only from the side and bottom surfaces of the trench 301, the surface of the semiconductor substrate 1 outside the trench 301 cannot be epitaxially grown because it is covered with the first oxide layer 3, embodiments of the present invention can prevent the epitaxial layer 6 in adjacent trenches 301 from extending outside the trenches 301 and forming merged structures, therefore, stress generated by merging of the groove epitaxial layer 6 can be eliminated, dislocation generated by the stress can be avoided, and the performance of the device can be improved.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (13)
1. A filling method for groove epitaxy is characterized by comprising the following steps:
step one, forming a hard mask layer formed by overlapping a first oxide layer, a second nitride layer and a third oxide layer on the surface of a semiconductor substrate;
Step two, defining a forming area of a groove by photoetching, and removing the third oxide layer, the second nitride layer and the first oxide layer in the forming area of the groove in sequence by adopting an etching process so as to form a hard mask layer opening;
Step three, forming a side wall consisting of a fourth nitride layer on the side face of the opening of the hard mask layer;
Etching the semiconductor substrate at the bottom of the opening of the hard mask layer by taking the hard mask layer as a mask to form the groove;
fifthly, removing the third oxide layer, and utilizing the side protection of the side wall to ensure that the first oxide layer is not etched transversely in the process of removing the third oxide layer;
forming sacrificial oxide layers on the side surfaces and the bottom surfaces of the grooves, removing the sacrificial oxide layers, and enabling the first oxide layers not to be etched transversely in the process of removing the sacrificial oxide layers by utilizing the side surface protection of the side walls;
Seventhly, removing the second nitride layer and the side wall at the same time;
And step eight, performing epitaxial growth to form a groove epitaxial layer to fill the groove, and enabling the groove epitaxial layer to grow only on the bottom surface and the side surface of the groove in the epitaxial growth process by utilizing the characteristic that the first oxide layer is not etched transversely.
2. a method of trench epitaxial filling according to claim 1 wherein: in the first step, a first epitaxial layer is formed on the surface of the semiconductor substrate, and the groove is formed in the first epitaxial layer.
3. a method of trench epitaxial filling according to claim 2 wherein: the trench is a super junction trench.
4. A method of trench epitaxial filling according to claim 3 wherein: the first epitaxial layer has a first conductivity type and the trench epitaxial layer has a second conductivity type.
5. A method of trench epitaxial filling according to claim 4 wherein: the grooves comprise a plurality of grooves, the groove epitaxial layers form second conductive type columns, the first epitaxial layers between the grooves form first conductive type columns, and the first conductive type columns and the second conductive type columns are alternately arranged to form a super junction structure.
6. A method of trench epitaxial filling according to claim 2 wherein: the semiconductor substrate is a silicon substrate, the first epitaxial layer and the groove epitaxial layer are silicon epitaxial layers, the first oxide layer and the third oxide layer are silicon dioxide layers, and the second nitride layer and the fourth nitride layer are silicon nitride layers.
7. A method of trench epitaxial filling according to claim 1 wherein: the third step comprises the following sub-steps:
step 31, forming the fourth nitride layer by overall deposition;
And 32, performing overall etching on the fourth nitride layer to form the side wall in a self-alignment manner on the side face of the hard mask layer opening.
8. A method of filling a trench epitaxy as claimed in claim 1 or 7, wherein: the thickness of the fourth nitride layer is
9. A method of filling a trench epitaxy as claimed in claim 1 or 2 or 6, wherein: the thickness of the first oxide layer isthe thickness of the second nitride layer isThe thickness of the third oxide layer is
10. A method of trench epitaxial filling according to claim 9 wherein: and the third oxide layer is partially lost in the etching process of the fourth step.
11. A method of filling a trench epitaxy as claimed in claim 10, wherein: after the fourth step, the residual thickness of the third oxide layer is
12. A method of filling a trench epitaxy as claimed in claim 4 or 5, wherein: the first conductivity type is N-type, and the second conductivity type is P-type.
13. A method of filling a trench epitaxy as claimed in claim 4 or 5, wherein: the first conductivity type is P-type and the second conductivity type is N-type.
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| CN109119459B (en) * | 2018-08-14 | 2022-03-08 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of groove type super junction |
| CN112736102B (en) * | 2020-12-23 | 2022-07-19 | 华虹半导体(无锡)有限公司 | Method for forming isolation region of CIS device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030059437A (en) * | 2001-12-29 | 2003-07-10 | 주식회사 하이닉스반도체 | Method of forming field oxide of semiconductor device |
| CN105957897A (en) * | 2016-06-28 | 2016-09-21 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for groove grid super junction MOSFET |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030059437A (en) * | 2001-12-29 | 2003-07-10 | 주식회사 하이닉스반도체 | Method of forming field oxide of semiconductor device |
| CN105957897A (en) * | 2016-06-28 | 2016-09-21 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for groove grid super junction MOSFET |
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