CN107731733A - The fill method of groove extension - Google Patents

The fill method of groove extension Download PDF

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Publication number
CN107731733A
CN107731733A CN201711075799.0A CN201711075799A CN107731733A CN 107731733 A CN107731733 A CN 107731733A CN 201711075799 A CN201711075799 A CN 201711075799A CN 107731733 A CN107731733 A CN 107731733A
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groove
oxide layer
layer
nitration case
fill method
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CN201711075799.0A
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CN107731733B (en
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孔蔚然
季伟
伍洲
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)

Abstract

The invention discloses a kind of fill method of groove extension, including step:Formed in semiconductor substrate surface and the hard mask layers formed are superimposed by the first oxide layer, the second nitration case and the 3rd oxide layer;Lithographic definition goes out the forming region of groove, performs etching to form hard mask layers opening;The side wall being made up of the 4th nitration case is formed in the side of hard mask layers opening;Semiconductor substrate is performed etching to form groove;Remove the 3rd oxide layer;Form sacrificial oxide layer and remove;Remove the second nitration case and side wall;Carry out being epitaxially-formed groove epitaxial layer filling groove, lower surface and lateral growth of groove epitaxial layer described in epitaxial process only in the groove are not made by the feature of lateral etching using first oxide layer.The present invention can prevent adjacent trenches epitaxial layers from extending to groove is outer and form combinatorial construction, caused stress and avoid resulting dislocation so as to eliminate merging due to groove epitaxial layer, improve the performance of device.

Description

The fill method of groove extension
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, more particularly to a kind of filling side of groove extension Method.
Background technology
As shown in Figure 1A to Fig. 1 G, be existing groove extension fill method each step in device architecture schematic diagram; Illustrated by taking the extension filling of the groove of super-junction structure as an example, the fill method of existing groove extension comprises the following steps:
As shown in Figure 1A, there is provided semi-conductive substrate such as silicon substrate 101, on the surface of silicon substrate 101 formed with N-type extension Layer 102, oxide layer 103, nitration case 104 and oxide layer 105 are sequentially formed on the surface of N-type epitaxy layer 102 and is superimposed to be formed firmly Matter mask layer;The forming region of groove is opened in photoetching, and the 3-tier architecture of the hard mask layers of groove forming region is carved successively Erosion forms the opening of hard mask layers.By taking the example of a design parameter as an example:The thickness of oxide layer 103 isNitration case 104 thickness isThe thickness of oxide layer 105 is
As shown in Figure 1B, the etching for N-type epitaxy layer 102 being carried out using hard mask layers as mask forms groove 201, superjunction Groove is due to the larger also commonly referred to as deep trench of depth.In the etching of groove 201, oxide layer 105 has certain loss, example Such as:Etching 105 remaining thickness of rear oxidation layer is
As shown in Figure 1 C, removing oxide layer 105 is removed.Because oxide layer 103 is identical with 105 material, therefore removing removing oxide layer During 105, the side of oxide layer 103 can also produce certain lateral etching, as shown in dotted line circle 202.Due to nitration case 104 material and oxide layer 105 is different, therefore nitration case 104 will not be etched.
As shown in figure iD, sacrificial oxide layer 203 is formed afterwards, such as:The thickness of sacrificial oxide layer 203 isSuch as figure Shown in 1E, the sacrificial oxide layer 203 is being removed afterwards.Because sacrificial oxide layer 203 is identical with the material of oxide layer 103, therefore During etching removes sacrificial oxide layer 203, oxide layer 103 also can be by lateral etching a certain amount.Oxide layer 103 is altogether By the region of lateral etching as shown in Fig. 1 F dotted line circle 204.Oxide layer 103 is altogether d1 by the distance of lateral etching, D1 is 0.6 micron in one example.
As shown in fig. 1F, after the removal of sacrificial oxide layer 203, nitration case 104 is removed.
As shown in Figure 1 G, the growth of p-type epitaxial layer 106 is carried out afterwards until groove 201 is filled up completely with.It is only aobvious in Fig. 1 G The structure in the growth course of p-type epitaxial layer 106 is shown.As can be seen that due to oxide layer 103 can by lateral etching it is certain away from From d1 so that the periphery width of groove 201 is protected for the not oxidized layer 103 of N-type epitaxy layer 102 in d1 region to be exposed Come.Because epitaxial growth technology is selected at the superficial growth of epitaxial layer, do not grown on the surface of oxide layer, such epitaxial growth During, the meeting of p-type epitaxial layer 106 while the not oxidized layer outside the side of groove 201 and lower surface and groove 201 The surface of N-type epitaxy layer 102 of 103 coverings grows simultaneously, the N-type epitaxy layer that the not oxidized layer 103 outside groove 201 covers The thickness for the p-type epitaxial layer 106 that 102 surfaces are formed can extend to the surface of oxide layer 103 simultaneously after being more than the thickness of oxide layer 103 Cross growth simultaneously, finally cause the easy oxide layer 103 between groove 201 of p-type epitaxial layer 106 in adjacent trenches 201 Extend mutually on surface and contact merging and connect into an overall structure, it is this to be formed in oxide layer 103 and laterally connect mutually Touch the p-type epitaxial layer 106 merged easily to produce stress and form dislocation (dislocation), can finally influence the performance of device.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of fill method of groove extension, can prevent in adjacent trenches Epitaxial layer extends to that groove is outer and form combinatorial construction, so as to eliminate merging due to groove epitaxial layer and caused stress with And resulting dislocation is avoided, improve the performance of device.
In order to solve the above technical problems, the fill method of groove extension provided by the invention comprises the following steps:
Shape is superimposed by the first oxide layer, the second nitration case and the 3rd oxide layer Step 1: being formed in semiconductor substrate surface Into hard mask layers.
Step 2: lithographic definition goes out the forming region of groove, the formation area of the groove is removed successively using etching technics The 3rd oxide layer, second nitration case and first oxide layer in domain are so as to forming hard mask layers opening.
Step 3: the side wall being made up of the 4th nitration case is formed in the side of the hard mask layers opening.
Step 4: using the Semiconductor substrate of the hard mask layers as mask to the hard mask layers open bottom Perform etching to form the groove.
Step 5: removing the 3rd oxide layer, make removing the 3rd oxidation using the lateral protection of the side wall First oxide layer is not by lateral etching during layer.
Step 6: forming sacrificial oxide layer in the side of the groove and lower surface, described sacrifice is removed afterwards and is aoxidized Layer, makes first oxide layer during sacrificial oxide layer is stated described in removal not horizontal using the lateral protection of the side wall To etching.
Step 7: second nitration case and the side wall are removed simultaneously.
Step 8: be epitaxially-formed groove epitaxial layer fills the groove, using first oxide layer not by The feature of lateral etching makes lower surface and lateral growth of groove epitaxial layer described in epitaxial process only in the groove.
Further improve is that semiconductor substrate surface described in step 1 is formed with the first epitaxial layer, the ditch flute profile In first epitaxial layer described in Cheng Yu.
Further improve is that the groove is superjunction groove.
Further improve is that first epitaxial layer has the first conduction type, and the groove epitaxial layer has second Conduction type.
Further improve be, the groove includes multiple, and the second conductivity type columns are formed by the groove epitaxial layer, by First epitaxial layer between the groove forms the first conductivity type columns, by first conductivity type columns and described second Conductivity type columns are alternately arranged composition super-junction structure.
Further improve is that the Semiconductor substrate is silicon substrate, first epitaxial layer and the groove epitaxial layer All it is silicon epitaxy layer, first oxide layer and the 3rd oxide layer are all silicon dioxide layer, second nitration case and institute It is all silicon nitride layer to state the 4th nitration case.
Further improve is that step 3 is included as follows step by step:
Step 31, deposit forms the 4th nitration case comprehensively.
Step 32, comprehensive etching of progress nitration case form the side in the side autoregistration of the hard mask layers opening Wall.
Further improve is that the thickness of the 4th nitration case is
Further improve is that the thickness of first oxide layer isThe thickness of second nitration case isThe thickness of 3rd oxide layer is
Further improve is that the 3rd oxide layer is by partition losses described in the etching process of step 4.
Further improve is that the residual thickness of the 3rd oxide layer is after the completion of step 4
Further improve is that the first conduction type is N-type, and the second conduction type is p-type.
Further improve is that the first conduction type is p-type, and the second conduction type is N-type.
Technical scheme has carried out special design according to technical problem proposed by the present invention, mainly in hard After the opening of mask layer is formed, a step of step forms the side wall being made up of the 4th nitration case in the side of opening is added, this Second nitration case of sample combination side wall and hard mask layers, the first oxide layer of hard mask layers can all be surrounded, wherein Side wall mainly covers from side to the first oxide layer;So, hard mask layers the 3rd oxide layer etching and In the etching of sacrificial oxide layer, the side of the first oxide layer is due to having the protection of side wall without producing lateral etching again, so, After the trenches are formed and after nitration case all removes, the first oxide layer can be covered well to the surface outside groove, be made During obtaining extension filling groove, epitaxial layer only grows from the side of groove and lower surface, the Semiconductor substrate outside groove Surface can not carry out epitaxial growth due to being covered by the first oxide layer, so the present invention can prevent adjacent trenches epitaxial layers from prolonging It is outer and form combinatorial construction to reach groove, so as to eliminate merging due to groove epitaxial layer and caused stress and avoid by This caused dislocation, improve the performance of device.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description:
Figure 1A-Fig. 1 G are the device architecture schematic diagrames in each step of the fill method of existing groove extension;
Fig. 2 is the flow chart of the fill method of groove extension of the embodiment of the present invention;
Fig. 3 A- Fig. 3 H are the device architecture schematic diagrames in each step of the fill method of groove extension of the embodiment of the present invention.
Embodiment
As shown in Fig. 2 it is the flow chart of the fill method of groove extension of the embodiment of the present invention;As shown in Fig. 3 A to Fig. 3 H, Be the fill method of groove extension of the embodiment of the present invention each step in device architecture schematic diagram, outside groove of the embodiment of the present invention The fill method prolonged comprises the following steps:
Step 1: as shown in Figure 3A, formed on the surface of Semiconductor substrate 1 by the first oxide layer 3, the second nitration case 4 and the The hard mask layers that the superposition of three oxide layers 5 is formed.
In the embodiment of the present invention, the surface of Semiconductor substrate 1 is formed formed with the first epitaxial layer 2, follow-up groove 301 In first epitaxial layer 2.The groove 301 is superjunction groove.First epitaxial layer 2 has the first conduction type, after Continuous groove epitaxial layer 6 has the second conduction type.
Preferably, the Semiconductor substrate 1 is silicon substrate, first epitaxial layer 2 and the follow-up groove epitaxial layer 6 All it is silicon epitaxy layer, first oxide layer 3 and the 3rd oxide layer 5 are all silicon dioxide layer, the He of the second nitration case 4 The 4th follow-up nitration case 4a is silicon nitride layer.
By taking a design parameter as an example:The thickness of first oxide layer 3 isThe thickness of second nitration case 4 ForThe thickness of 3rd oxide layer 5 is
Step 2: as shown in Figure 3A, lithographic definition goes out the forming region of groove 301, institute is removed successively using etching technics The 3rd oxide layer 5, second nitration case 4 and first oxide layer 3 in the forming region of groove 301 are stated so as to shape Into hard mask layers opening.
Step 3: as shown in Figure 3A, form what is be made up of the 4th nitration case 4a in the side of the hard mask layers opening Side wall 4a.
Preferably, step 3 is included as follows step by step:
Step 31, deposit forms the 4th nitration case 4a comprehensively.The thickness of the 4th nitration case 4a is
Step 32, comprehensive etching of progress nitration case form the side in the side autoregistration of the hard mask layers opening Wall 4a.Here self aligned mean need not use photoetching process with regard to side wall 4a is formed at into the hard mask layers between energy The side of opening.
It is mask to described in the hard mask layers open bottom using the hard mask layers Step 4: show such as Fig. 3 C Semiconductor substrate 1 performs etching to form the groove 301.
The 3rd oxide layer 5 is by partition losses described in the etching process of step 4.By taking a design parameter as an example:Step 4 After the completion of the residual thickness of the 3rd oxide layer 5 be
Step 5: such as Fig. 3 D show, the 3rd oxide layer 5 is removed, makes removing using the lateral protection of the side wall 4a First oxide layer 3 is not by lateral etching during 3rd oxide layer 5.First oxide layer 3 of the step is not It can be gone to understand with reference to step corresponding to the existing method shown in Fig. 1 C by lateral etching.
Step 6: such as Fig. 3 E show, sacrificial oxide layer 302 is formed in the side of the groove 301 and lower surface;Such as Fig. 3 F Show, remove the sacrificial oxide layer 302 afterwards, make stating sacrificial oxide layer described in removal using the lateral protection of the side wall 4a First oxide layer 3 is not by lateral etching during 302.First oxide layer 3 of the step can not by lateral etching Go to understand with step corresponding to the existing method with reference to shown in Fig. 1 E.
Step 7: such as Fig. 3 G show, while remove second nitration case 4 and the side wall 4a.
Step 8: show such as Fig. 3 H, carry out being epitaxially-formed groove epitaxial layer 6 and fill the groove 301, utilize described the One oxide layer 3 does not make bottom of groove epitaxial layer described in epitaxial process 6 only in the groove 301 by the feature of lateral etching Portion surface and lateral growth;Namely the surface outside the groove 301 is all covered by first oxide layer 3, so described Epitaxial layer can not be formed on surface outside groove 301.
In the embodiment of the present invention, the groove 301 include it is multiple, the second conduction type is formed by the groove epitaxial layer 6 Post, the first conductivity type columns are formed by first epitaxial layer 2 between the groove 301, by first conductivity type columns Composition super-junction structure is alternately arranged with second conductivity type columns.
In the embodiment of the present invention, the first conduction type is N-type, and the second conduction type is p-type.Also can in other embodiments For:First conduction type is p-type, and the second conduction type is N-type.
The technical scheme of the embodiment of the present invention has carried out special design according to technical problem proposed by the present invention, mainly After the opening of hard mask layers is formed, add a step and the side wall 4a being made up of the 4th nitration case 4a is formed in the side of opening The step of, side wall 4a and the second nitration case 4 of hard mask layers are so combined, can be by the first oxide layer 3 of hard mask layers All surround, wherein side wall 4a mainly covers from side to the first oxide layer 3;So, the 3rd of hard mask layers the In the etching of oxide layer 5 and the etching of sacrificial oxide layer 302, the side of the first oxide layer 3 due to there is side wall 4a protection and Lateral etching will not be produced again, so, after the formation of groove 301 and after nitration case 4 and 4a remove, the energy of the first oxide layer 3 It is enough that surface outside groove 301 is covered well so that during extension filling groove 301, epitaxial layer 6 is only from groove 301 side and lower surface grow, and the surface of Semiconductor substrate 1 outside groove 301 can not due to being covered by the first oxide layer 3 Epitaxial growth is carried out, so the embodiment of the present invention can prevent the epitaxial layers 6 of adjacent trenches 301 from extending to outside groove 301 and be formed Combinatorial construction, caused stress and resulting dislocation is avoided so as to eliminate merging due to groove epitaxial layer 6, carried The performance of high device.
The present invention is described in detail above by specific embodiment, but these not form the limit to the present invention System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should It is considered as protection scope of the present invention.

Claims (13)

1. a kind of fill method of groove extension, it is characterised in that comprise the following steps:
It is superimposed what is formed by the first oxide layer, the second nitration case and the 3rd oxide layer Step 1: being formed in semiconductor substrate surface Hard mask layers;
Step 2: lithographic definition goes out the forming region of groove, in the forming region for removing the groove successively using etching technics The 3rd oxide layer, second nitration case and first oxide layer so as to forming hard mask layers opening;
Step 3: the side wall being made up of the 4th nitration case is formed in the side of the hard mask layers opening;
Step 4: the Semiconductor substrate of the hard mask layers open bottom is carried out using the hard mask layers as mask Etching forms the groove;
Step 5: removing the 3rd oxide layer, make removing the 3rd oxide layer using the lateral protection of the side wall During first oxide layer not by lateral etching;
Step 6: forming sacrificial oxide layer in the side of the groove and lower surface, the sacrificial oxide layer is removed afterwards, profit First oxide layer during sacrificial oxide layer is stated described in removal is set not carved laterally with the lateral protection of the side wall Erosion;
Step 7: second nitration case and the side wall are removed simultaneously;
Step 8: carry out being epitaxially-formed the groove epitaxial layer filling groove, using first oxide layer not by transverse direction The feature of etching makes lower surface and lateral growth of groove epitaxial layer described in epitaxial process only in the groove.
2. the fill method of groove extension as claimed in claim 1, it is characterised in that:Semiconductor substrate table described in step 1 Formed with the first epitaxial layer, the groove is formed in first epitaxial layer in face.
3. the fill method of groove extension as claimed in claim 2, it is characterised in that:The groove is superjunction groove.
4. the fill method of groove extension as claimed in claim 3, it is characterised in that:First epitaxial layer has first to lead Electric type, the groove epitaxial layer have the second conduction type.
5. the fill method of groove extension as claimed in claim 4, it is characterised in that:The groove is including multiple, by described Groove epitaxial layer forms the second conductivity type columns, and the first conduction type is formed by first epitaxial layer between the groove Post, it is alternately arranged by first conductivity type columns and second conductivity type columns and is formed super-junction structure.
6. the fill method of groove extension as claimed in claim 2, it is characterised in that:The Semiconductor substrate is silicon substrate, First epitaxial layer and the groove epitaxial layer are all silicon epitaxy layer, and first oxide layer and the 3rd oxide layer are all Silicon dioxide layer, second nitration case and the 4th nitration case are all silicon nitride layer.
7. the fill method of groove extension as claimed in claim 1, it is characterised in that:Step 3 is included as follows step by step:
Step 31, deposit forms the 4th nitration case comprehensively;
Step 32, comprehensive etching of progress nitration case form the side wall in the side autoregistration of the hard mask layers opening.
8. the fill method of the groove extension as described in claim 1 or 7, it is characterised in that:The thickness of 4th nitration case For
9. the fill method of the groove extension as described in claim 1 or 2 or 6, it is characterised in that:The thickness of first oxide layer Spend and beThe thickness of second nitration case isThe thickness of 3rd oxide layer is
10. the fill method of groove extension as claimed in claim 9, it is characterised in that:Described in the etching process of step 4 3rd oxide layer is by partition losses.
11. the fill method of groove extension as claimed in claim 10, it is characterised in that:3rd oxygen after the completion of step 4 Change layer residual thickness be
12. the fill method of the groove extension as described in claim 4 or 5, it is characterised in that:First conduction type is N-type, the Two conduction types are p-type.
13. the fill method of the groove extension as described in claim 4 or 5, it is characterised in that:First conduction type is p-type, the Two conduction types are N-type.
CN201711075799.0A 2017-11-06 2017-11-06 Filling method for groove epitaxy Active CN107731733B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109119459A (en) * 2018-08-14 2019-01-01 上海华虹宏力半导体制造有限公司 The manufacturing method of groove-shaped super junction
CN112736102A (en) * 2020-12-23 2021-04-30 华虹半导体(无锡)有限公司 Method for forming isolation region of CIS device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030059437A (en) * 2001-12-29 2003-07-10 주식회사 하이닉스반도체 Method of forming field oxide of semiconductor device
US20160079352A1 (en) * 2013-02-05 2016-03-17 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
CN105957897A (en) * 2016-06-28 2016-09-21 上海华虹宏力半导体制造有限公司 Manufacturing method for groove grid super junction MOSFET

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030059437A (en) * 2001-12-29 2003-07-10 주식회사 하이닉스반도체 Method of forming field oxide of semiconductor device
US20160079352A1 (en) * 2013-02-05 2016-03-17 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
CN105957897A (en) * 2016-06-28 2016-09-21 上海华虹宏力半导体制造有限公司 Manufacturing method for groove grid super junction MOSFET

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109119459A (en) * 2018-08-14 2019-01-01 上海华虹宏力半导体制造有限公司 The manufacturing method of groove-shaped super junction
CN112736102A (en) * 2020-12-23 2021-04-30 华虹半导体(无锡)有限公司 Method for forming isolation region of CIS device
CN112736102B (en) * 2020-12-23 2022-07-19 华虹半导体(无锡)有限公司 Method for forming isolation region of CIS device

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