CN107066393B - Method for improving mapping information density in address mapping table - Google Patents
Method for improving mapping information density in address mapping table Download PDFInfo
- Publication number
- CN107066393B CN107066393B CN201710022698.0A CN201710022698A CN107066393B CN 107066393 B CN107066393 B CN 107066393B CN 201710022698 A CN201710022698 A CN 201710022698A CN 107066393 B CN107066393 B CN 107066393B
- Authority
- CN
- China
- Prior art keywords
- mapping
- cache
- mapping table
- address
- records
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention discloses a method for improving mapping information density in an address mapping table, which can improve the hit rate of a cache mapping table in a page mapping scheme based on cache part mapping information, improve the read-write performance of a flash memory conversion layer, merge continuous and adjacent mapping records on a logic address and a physical address to generate a mapping entry on the premise of not increasing the number of entries in the cache mapping table in a memory, so that one mapping entry can represent the mapping relation between a plurality of logic addresses and physical addresses, one mapping entry is inserted into the cache mapping table instead of one mapping record which can only represent the mapping relation between one logic address and one physical address, thereby increasing the number of the mapping records stored in the cache mapping table on the premise of not increasing the occupation of the cache mapping table on the memory, and obviously increasing the hit rate of the cache mapping table, the read-write efficiency of the Flash conversion layer is improved, and the method can be widely applied to management of NAND Flash memories of various systems.
Description
Technical Field
The invention relates to the technical field of data storage, in particular to a method for improving mapping information density in an address mapping table.
Background
The NAND Flash is a nonvolatile semiconductor memory, can not cause the data loss stored on it because of the power-off, because there is no mechanical part in the NAND Flash memory, therefore have low power consumption, it is little to generate heat, light in weight, small, shock-resistant advantage that traditional mechanical disk memory does not have, its random read-write performance is far higher than traditional mechanical disk memory. With the breakthrough of the bottleneck of Flash memory storage capacity, the optimization of performance and the reduction of cost, NAND Flash memory has become a very important digital storage medium.
NAND Flash is composed of many blocks (blocks), each of which is composed of several pages (pages), where a Page is the minimum unit of reading and writing data, and a Block is the minimum unit of erasing. When the NAND Flash is subjected to write operation, the block where the page is located needs to be erased firstly, otherwise, the page cannot be subjected to write operation. Flash memory therefore has three basic operations: read, write, erase.
The three operations of the NAND Flash have different performances, the read performance is the best, the write performance is the second best, and the erase performance is the worst. The speed of the read operation is fastest, reading a page takes about tens of microseconds, the speed of the write operation is slower than the read operation, writing a page takes about hundreds of microseconds, the erase operation is very time consuming, and erasing a block takes about several milliseconds.
The erase times of the blocks of NAND Flash are limited and once their maximum erase times are exceeded, the data stored thereon may become unreliable.
When data stored In a certain page of the NAND Flash is updated, an erase operation must be used to erase a block where the page is located, where the erase is a millisecond-level operation, and is a very time-consuming operation compared with a microsecond-level write operation, and therefore if a local Update (In-plane Update) mode is also used, the write speed of the Flash memory is severely reduced. Furthermore, if the data on a block is frequently updated locally, this may cause the block to quickly reach its use limit as it is continually erased. Therefore, in actual use, when the NAND Flash updates data, an Out-Place Update (Out-Place Update) method is adopted, and all the updated data is not written into the original page, but is rewritten into other erased pages (free pages). The storage resources of the NANDFlash are distributed and managed in a mode that page numbers are physical addresses, and with the change of storage positions of effective data on the NANDFlash, a logical-to-physical mapping relation cannot be obtained through calculation by establishing an expression, and data addressing of a file system needs to be provided through establishing a mapping table. Therefore, introducing a Flash Translation Layer (FTL) and implementing an address mapping mechanism through the FTL to record a mapping relationship between a logical address and a physical address where data is actually stored becomes a mainstream flash management scheme at present.
In order to realize quick addressing, a mapping table is generally partially or completely cached in a memory and is called as a cache mapping table, and how to reduce the occupation of the cache mapping table on the memory and enable a request to complete direct addressing through the cache mapping table is a problem to be solved by a flash translation layer.
According to the difference of the address mapping granularity, the method for establishing the cache mapping table can be divided into four methods: page Mapping (PageMapping), block Mapping (Blocking Mapping), Hybrid Mapping (Hybrid Mapping), and Cached Page Mapping based on cache section Mapping information.
The page mapping is to perform address mapping by taking a page as a unit, store a page-based mapping table in the memory, where each logical page has a physical page corresponding to the logical page, and needs to be maintained by a mapping record in the mapping table, and one mapping record occupies one mapping table entry in the mapping table.
The block mapping is performed by using a block as a unit, and the address offset in the logical block is consistent with the offset in the physical block. Compared with a page mapping table, the mapping table occupies a small memory, but has the disadvantage of poor performance in processing small data updates, and the update of a small block of data causes the copy of the whole block of content.
Combining the advantages and disadvantages of page mapping and block mapping results in a hybrid mapping mechanism that functionally divides blocks on NAND Flash into data blocks and log blocks, with fewer log blocks. When the data in a certain data block is to be updated, new data will be written into the log block, and when the number of all log blocks is lower than a certain value, the data in the log block and the data block needs to be merged, which may result in significant performance degradation.
The page mapping scheme based on caching partial mapping information in a memory is an improvement on page mapping, the mapping mode uses a plurality of pages on a NAND Flash to store a complete mapping table, the pages are called mapping table storage pages, mapping records which are frequently requested are cached in the memory, the cache size is fixed, namely the number of mapping table items in the cache mapping table is provided with an upper limit, the storable number of the mapping records is the same as the number of the mapping table items, and the memory occupation of the cache mapping table is ensured not to be overlarge. When a read-write request comes, if the corresponding mapping record is not in the cache, namely the cache mapping table is not hit, the mapping record is read from the NAND Flash, when the number of the mapping record in the cache mapping table reaches an upper limit, the mapping record which is not used for access for the longest time is exchanged from the cache, and if the removed mapping record is dirty, namely the mapping relation between the logic and the physical page stored by the mapping record is changed in the cache, the mapping record needs to be written back to the mapping table in the NAND Flash. Reading and swapping out of mapping records results in additional reading and writing to NAND Flash.
In summary, page mapping is flexible and performs best, while hybrid mapping is poor and block mapping performs worst. The page mapping scheme based on the mapping information of the cache part does not generate merging operation, so the performance of the page mapping scheme is higher than that of hybrid mapping and is similar to that of a page mapping mode. However, the cache mapping table can only store limited mapping records, so that part of requests cannot hit the cache mapping table to complete direct addressing, and the requests need to exchange the mapping records with the mapping table in the NAND Flash, thereby generating additional read operation for reading the mapping table on the NAND Flash and additional write operation for writing the mapping records into the NAND Flash due to non-requests, and generating additional garbage collection operation caused by insufficient free blocks when the mapping records are written into the NAND Flash. These additional wipes eventually result in lower performance than page mapping, the lower the hit rate, the worse the performance. Therefore, how to cache more mapping table entries in the cache mapping table on the premise of not increasing the memory occupation, that is, improving the storage density of the cache mapping table to improve the hit rate, is a difficult point that needs to be mainly solved in a page mapping scheme based on the mapping information of the cache part.
Disclosure of Invention
The invention aims to provide a method for improving the mapping information density in an address mapping table, which can improve the mapping record density in a cache mapping table and achieve the aim of improving the reading and writing performance of an FTL.
The purpose of the invention is realized by the following technical scheme:
a method for improving mapping information density in an address mapping table comprises the following steps:
when data is written, dividing the data by taking a page as a unit, sequentially writing the data into a block with a plurality of continuous free pages in a memory according to the sequence of logical addresses from low to high, wherein each stored page of data corresponds to one mapping record, and generating one to a plurality of mapping entries according to the mapping records;
when reading data, dividing the read request address by taking a page as a unit, searching cache mapping tables in the memory one by one, if the logical address of a certain page does not hit the cache mapping table in the memory, reading a mapping table storage page used for storing the mapping table in the memory, and obtaining a required target mapping record from the mapping table storage page; and meanwhile, the mapping records around the target mapping record are also searched in the mapping table memory page, and a mapping entry is generated by combining the surrounding mapping records meeting the conditions, wherein the searching process comprises the following steps: reading the content of a storage page of a mapping table, namely a mapping table segment, retrieving the mapping table segment from a target mapping record in a front direction and a rear direction, if the difference between the logical address value and the physical address value of the adjacent mapping record B and the target mapping record is found to be 1 in a certain direction, continuing to retrieve the mapping table from the adjacent mapping record B in the same direction until the two adjacent mapping records are not continuous or exist in a cache mapping table or a first mapping record or a last mapping record in the storage page of the mapping table is retrieved;
and when data is written and read, the generated mapping item is inserted into a cache mapping table in the memory.
When data is written, if the number of pages of the written data is N, the number of continuous free pages in a block with a plurality of continuous free pages in a memory is M, and N is greater than M, cross-block storage is needed, namely, the data is sequentially written into other blocks with a plurality of continuous free pages by the rest data pages according to the sequence of logical addresses from low to high until all the data pages are written into the memory;
if S times of block crossing storage is generated when the data pages are written, S mapping entries are generated, and the data of the mapping records contained in each mapping entry is the number of the data pages stored in the corresponding block.
The mapping entries store a plurality of continuous mapping records; if one mapping record MPRec1 with LBA as L and PBA as P is available for one logical address, if another mapping record MPRec2 with LBA as L +1 is available, the mapping records MPRec1 and MPRec2 are consecutive with a physical address PBA of P +1, if the other logical address LBA is L +2 mapping record MPRec3, the physical address PBA is P +2, the mapping records MPRec1, MPRec2 and MPRec3 are consecutive, and so on, there are N mapping records, the logical address LBA values of which successively increase from low to high in accordance with L, L +1, L +2, …, L + N-1, the logical address values recorded in adjacent mapping records differ by 1, the values of the physical addresses PBA are also increased from low to high according to P, P +1, P +2, … and P + N-1, the values of the physical addresses recorded in adjacent mapping records are different by 1, and such N mapping records are consecutive mapping records.
The mapping item is composed of the logical address and the physical address in the mapping record with the minimum logical address, a length value N and a dirty flag bit in the N continuous mapping records;
the logical address and the physical address of the mapping entry occupy the same number of bytes as the logical address and the physical address in the corresponding mapping record, and one byte is additionally used for storing a length value N and a dirty flag bit, wherein the dirty flag bit occupies the highest bit of the byte and is used for identifying whether the mapping entry is changed in the life cycle of the cache mapping table, if the mapping entry is changed, the mapping entry is assigned to be 1, otherwise, the mapping entry is assigned to be 0; the length value of the entry is stored in bits 0 to 7 of the byte.
Inserting a mapping entry into a cache mapping table in the memory comprises:
if the mapping entries and the existing entries in the cache mapping table generate conflicts caused by intersection on the logical addresses, the relevant mapping entries need to be decomposed and recombined;
if the mapping entries and the existing entries in the cache mapping table are consecutive, the associated mapping entries need to be merged again.
After the mapping entries are inserted into the cache mapping table in the memory, if the received read request hits the mapping entries, the corresponding physical addresses are directly calculated, and the method comprises the following steps:
searching a cache mapping table, and comparing the logical address LBA in the read request with the logical address range represented by each mapping item to judge whether the LBA falls in the logical address range represented by a certain mapping record;
for a mapping entry with a length of N, where the stored logical address is LBA1, and the physical address is PBA1, when LBA > is LBA1, and LBA < ═ LBA1+ N-1, it indicates that the logical address included in the request hits the mapping entry in the cache mapping table, and the method for calculating the physical address PBA corresponding to the logical address LBA in the read request is as follows: PBA1+ LBA-LBA1, and the addressing of the physical address can be completed through calculation.
According to the technical scheme provided by the invention, the corresponding mapping record is generated according to the read-write operation and is inserted into the cache mapping table, so that the density of the mapping record in the cache mapping table can be improved on the premise of not occupying more memory resources, thereby increasing the number of the mapping record in the cache mapping table and improving the hit rate of the cache mapping table.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a flowchart of a method for increasing mapping information density in an address mapping table according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a decomposition and a reassembly of a mapping entry when the generated mapping entry is inserted into a cache mapping table in a memory according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating merging of mapping entries when a generated mapping entry is inserted into a cache mapping table in a memory according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating merging of mapping entries when a generated mapping entry is inserted into a cache mapping table in a memory according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a method for increasing mapping information density in an address mapping table, as shown in fig. 1, the method mainly includes:
1. condition for determining whether mapping records adjacent to multiple logical addresses can be merged into a mapping entry
In the embodiment of the invention, when data is written in and read out, a plurality of mapping records meeting the conditions can be merged into the mapping entries, and a plurality of continuous mapping records are stored in the generated mapping entries; specifically, if one mapping record MPRec1 with a logical address LBA of L has a physical address PBA of P, if the other mapping record LBA is L +1 MPRec2 with a physical address PBA of P +1, the mapping records MPRec1 and MPRec2 are consecutive, if the other mapping record LBA is L +2 MPRec3 with a physical address PBA of P +2, the mapping records MPRec1, MPRec2 and MPRec3 are consecutive, and so on, there are N mapping records with logical address LBA whose value increases consecutively from low to high according to L, L +1, L +2, … and L + N-1, the logical address values recorded in adjacent mapping records differ by 1, and the physical address values recorded in adjacent mapping records also differ from low to high according to P, P +1, P +2, … and P + N-1, and the physical address values in adjacent mapping records differ by 1, such N mapping records are consecutive mapping records, and such N mapping records may be merged into one mapping entry.
For N consecutive mapping records, the mapping entries may be merged: each mapping item consists of three parts, namely a mapping record with the minimum logical address in the N continuous mapping records, a length value N, a dirty flag bit and the like; the length value N and the dirty flag bit are stored in the same byte, the dirty flag bit occupies the highest bit of the byte and is used for identifying whether the mapping entry is changed in the life cycle of the cache mapping table, if the mapping entry is changed, the mapping entry is assigned to be '1', otherwise, the value is '0', and the length value N of the entry is stored in bits 0 to 7 of the byte.
2. When data is written, the data is divided by taking a page as a unit, then the data is sequentially written into a block with a plurality of continuous free pages in a memory (NAND Flash) according to the sequence of logical addresses from low to high, each page of stored data corresponds to one mapping record, and one or more mapping entries can be generated by the continuous mapping records.
When data is written, if the number of pages of the written data is N, the number of continuous free pages in a block with a plurality of continuous free pages in the memory is M, and N > M, cross-block storage is needed, that is, the data is sequentially written into other blocks with a plurality of continuous free pages by the rest data pages according to the sequence of logical addresses from low to high until all the data pages are written into the memory.
As will be understood by those skilled in the art, when data is written, the data is also written into a block in units of pages, and the writing order of the pages in the block can only be written from a low-address page to a high-address page sequentially and cannot be written randomly, so that data with a low logical address is written into a page with a low physical address to generate a mapping record of the logical address to the physical address, and data with a low logical address is written into a page with a low physical address to generate a mapping record of the logical address to the physical address until all the data of the request is written; if all the free pages in the free block are fully written in the writing process and partial page data of the request is not written into the NAND Flash, the data needs to be written in a cross-block mode, namely a new free block is allocated to be used for writing the data in the writing request, similarly, the data writing sequence is still that the data of the low logical address is written into the page of the low physical address, a mapping record from the logical address to the physical address is generated, the data of the second low logical address is written into the page of the second low physical address, and a mapping record from the logical address to the physical address is generated. This is repeated until all the data in the write request is written to the NAND Flash.
The write request thus generates N mapping records that are contiguous if no cross-block writes are generated at the time of writing. Thus, the N mapping records can be merged into 1 mapping entry with a length of N.
If cross-block writing is generated during writing, the M mapping records corresponding to the data stored in the same block are continuous, so that the M mapping records can be combined into 1 mapping entry with the length of M. If S times of block crossing storage is generated when the data pages are written, S mapping entries are generated, and the data of the mapping records contained in each mapping entry is the number of the pages of the corresponding block, in which the data are written due to the request.
3. When reading data, the address range of the read request is divided by taking a page as a unit, cache mapping tables in the memory are searched one by one, if the logical address of a certain page does not hit the cache mapping table in the memory, the mapping table in the memory is read, and the flash memory page for storing the mapping table is called a mapping table storage page. Obtaining the mapping relation between the logical address and the physical address of the required data by reading the storage page of the mapping table, namely target mapping record; after the content of the mapping table storage page is read, the mapping records around the target mapping record are searched in the content, and the mapping records around the target mapping record are combined into the mapping entries, wherein the searching process comprises the following steps: firstly, reading the content of a storage page of a mapping table, namely a mapping table segment, then, searching the mapping table segment in the front and back directions by taking a target mapping record as a starting point, and if the difference between the logical address value and the physical address value of the adjacent mapping record B and the mapping record is found to be 1 in a certain direction, continuously searching the mapping table in the same direction by taking the adjacent mapping record B as the starting point. The conditions for suspending the search are: a) two adjacent mapping records are no longer contiguous (i.e., there is no longer a1 difference in both logical and physical address values); b) the first mapping record in the mapping table segment has been retrieved; c) the last mapping record in the mapping table segment has been retrieved; d) mapping records that, although contiguous, already exist in the cache mapping table are encountered.
4. And inserting mapping entries generated during data writing and data reading into a cache mapping table in the memory.
In the embodiment of the invention, the generated mapping entries are also inserted into the cache mapping table in the memory, so that the space locality and the time locality of the request are fully utilized, and the reading and writing efficiency of the FTL is improved. When the mapping item is inserted into the cache mapping table, the following two different processing modes are adopted according to specific situations:
if the mapping entries to be inserted and the existing one or more entries in the cache mapping table have intersections in the logical address space, the related mapping entries need to be decomposed and recombined, and the two logical address spaces have multiple superposition modes and need to be processed respectively according to different conditions. By way of example, FIG. 2 illustrates one method of disassembling and reassembling: when a mapping entry with a logical head address of 1136 is inserted into the cache mapping table, the entry and the mapping entry with a logical head address of 1135 in the cache mapping table have an intersection in a logical address space, and need to be recombined, and 3 new mapping entries are generated after combination, wherein the entry with the logical head address of 1135 is stored in the cache mapping table in situ, while the other two entries are in a free state at this time, and if there are more than two empty entries in the cache mapping table at this time, the two mapping entries in the free state can be directly inserted into the cache mapping table. If the number of empty entries in the cache mapping table is less than two, the mapping entries which are not accessed for the longest time need to be replaced first, and then the new entries in the free state are inserted into the cache mapping table.
If the mapping entries and the existing entries in the cache mapping table are consecutive, the associated mapping entries need to be merged again. For example, as shown in fig. 3, when a mapping entry with a logical head address of 1132 and a length of 3 is inserted into the cache, the mapping entry may be merged with an entry with a logical head address of 1135 in the cache to generate a new mapping entry, where the logical head address and the physical head address of the new mapping entry are 1132 and 517, respectively, and the length of the mapping entry becomes 7. As shown in fig. 4, when a mapping entry with a logical first address of 1139 and a length of 3 is inserted into the cache, the mapping entry is merged with a mapping entry with a first address of 1135 and a length of 4 in the cache, and the merged mapping entry is still stored in the cache in place.
The embodiment of the invention also provides a method for calculating the target mapping record through the mapping items, which comprises the following steps:
if the request hits a mapping entry of the cache mapping table, the corresponding physical address can be directly calculated, and the steps include: searching a cache mapping table, and comparing the logical address LBA in the read request with the logical address range represented by each mapping item to judge whether the LBA falls in the logical address range represented by a certain mapping record; for a mapping entry with a length of N, where the stored logical address is LBA1, and the physical address is PBA1, when LBA > is LBA1, and LBA < ═ LBA1+ N-1, it indicates that the logical address included in the request hits the mapping entry in the cache mapping table, and the method for calculating the physical address PBA corresponding to the logical address LBA in the read request is as follows: PBA1+ LBA-LBA1, and the addressing of the physical address can be completed through calculation.
The above-mentioned scheme of the embodiment of the invention can improve the hit rate of the cache mapping table and improve the read-write performance of the FTL, and under the premise of not increasing the number of entries in the cache mapping table in the memory, the invention combines the continuous mapping records to generate the mapping entries, so that each mapping entry can represent the mapping relation between a plurality of logical addresses and physical addresses, and each entry in the cache mapping table stores one mapping entry instead of one mapping record which can only represent the mapping relation between one logical address and the physical addresses, thereby increasing the number of the mapping records stored in the cache mapping table, and obviously increasing the hit rate of the cache mapping table, and simultaneously, because the mapping entries can express the continuous mapping records on a plurality of logical addresses, the spatial locality of the request can be effectively utilized, and the read-write efficiency of the FTL can be improved, the method can be widely applied to the management of the NAND Flash memories of various systems.
Through the above description of the embodiments, it is clear to those skilled in the art that the above embodiments can be implemented by software, and can also be implemented by software plus a necessary general hardware platform. With this understanding, the technical solutions of the embodiments can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a usb disk, a removable hard disk, etc.), and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods according to the embodiments of the present invention.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. A method for increasing mapping information density in an address mapping table, comprising:
when data is written, dividing the data by taking a page as a unit, sequentially writing the data into a block with a plurality of continuous free pages in a memory according to the sequence of logical addresses from low to high, wherein each stored page of data corresponds to one mapping record, and generating one to a plurality of mapping entries according to the mapping records; if cross-block writing is not generated during writing, the mapping records are continuous and can be combined into 1 mapping entry; if cross-block writing is generated during writing, mapping records corresponding to data stored in the same block are continuous, and all corresponding mapping records can be combined into 1 mapping entry; thus, if S times of cross-block storage is generated when writing data pages, S pieces of mapping entries are generated together;
when reading data, dividing the read request address by taking a page as a unit, searching cache mapping tables in the memory one by one, if the logical address of a certain page does not hit the cache mapping table in the memory, reading a mapping table storage page used for storing the mapping table in the memory, and obtaining a required target mapping record from the mapping table storage page; and meanwhile, the mapping records around the target mapping record are also searched in the mapping table memory page, and a mapping entry is generated by combining the surrounding mapping records meeting the conditions, wherein the searching process comprises the following steps: reading the content of a storage page of a mapping table, namely a mapping table segment, retrieving the mapping table segment from a target mapping record in a front direction and a rear direction, if the difference between the logical address value and the physical address value of the adjacent mapping record B and the target mapping record is found to be 1 in a certain direction, continuing to retrieve the mapping table from the adjacent mapping record B in the same direction until the two adjacent mapping records are not continuous or exist in a cache mapping table or a first mapping record or a last mapping record in the storage page of the mapping table is retrieved;
and when data is written and read, the generated mapping item is inserted into a cache mapping table in the memory.
2. The method of claim 1, wherein when writing data, if the number of pages of the written data is N, the number of consecutive free pages in a block with multiple consecutive free pages in the memory is M, and N > M, then cross-block storage is required, i.e. the remaining data pages are required to write data into other blocks with multiple consecutive free pages in order of logical addresses from low to high, until all data pages are written into the memory;
if cross-block storage occurs when a data page is written, the data of the mapping record contained in each mapping entry is the number of data pages stored in the corresponding block.
3. The method for increasing mapping information density in the address mapping table according to claim 1 or 2, wherein the mapping entries store a plurality of consecutive mapping records; if one mapping record MPRec1 with LBA as L and PBA as P is available for one logical address, if another mapping record MPRec2 with LBA as L +1 is available, the mapping records MPRec1 and MPRec2 are consecutive with a physical address PBA of P +1, if the other logical address LBA is L +2 mapping record MPRec3, the physical address PBA is P +2, the mapping records MPRec1, MPRec2 and MPRec3 are consecutive, and so on, there are N mapping records, the logical address LBA values of which successively increase from low to high in accordance with L, L +1, L +2, …, L + N-1, the logical address values recorded in adjacent mapping records differ by 1, the values of the physical addresses PBA are also increased from low to high according to P, P +1, P +2, … and P + N-1, the values of the physical addresses recorded in adjacent mapping records are different by 1, and such N mapping records are consecutive mapping records.
4. A method for increasing mapping information density in an address mapping table according to claim 3, wherein a mapping entry is composed of the logical address and the physical address in the mapping record with the smallest logical address, a length value N and a dirty flag bit in the N consecutive mapping records;
the logical address and the physical address of the mapping entry occupy the same number of bytes as the logical address and the physical address in the corresponding mapping record, and one byte is additionally used for storing a length value N and a dirty flag bit, wherein the dirty flag bit occupies the highest bit of the byte and is used for identifying whether the mapping entry is changed in the life cycle of the cache mapping table, if the mapping entry is changed, the mapping entry is assigned to be 1, otherwise, the mapping entry is assigned to be 0; the length value of the entry is stored in bits 0 to 7 of the byte.
5. The method as claimed in claim 1, wherein the step of inserting the mapping entry into the cache mapping table in the memory comprises:
if the mapping entries and the existing entries in the cache mapping table generate conflicts caused by intersection on the logical addresses, the relevant mapping entries need to be decomposed and recombined;
if the mapping entries and the existing entries in the cache mapping table are consecutive, the associated mapping entries need to be merged again.
6. The method as claimed in claim 1, wherein after the mapping entries are inserted into the cache mapping table in the memory, if the received read request hits the mapping entries, the corresponding physical addresses are directly calculated, and the step includes:
searching a cache mapping table, and comparing the logical address LBA in the read request with the logical address range represented by each mapping item to judge whether the LBA falls in the logical address range represented by a certain mapping record;
for a mapping entry with a length of N, where the stored logical address is LBA1, and the physical address is PBA1, when LBA > is LBA1, and LBA < ═ LBA1+ N-1, it indicates that the logical address included in the request hits the mapping entry in the cache mapping table, and the method for calculating the physical address PBA corresponding to the logical address LBA in the read request is as follows: PBA1+ LBA-LBA1, and the addressing of the physical address can be completed through calculation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710022698.0A CN107066393B (en) | 2017-01-12 | 2017-01-12 | Method for improving mapping information density in address mapping table |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710022698.0A CN107066393B (en) | 2017-01-12 | 2017-01-12 | Method for improving mapping information density in address mapping table |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107066393A CN107066393A (en) | 2017-08-18 |
| CN107066393B true CN107066393B (en) | 2020-06-09 |
Family
ID=59599191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710022698.0A Active CN107066393B (en) | 2017-01-12 | 2017-01-12 | Method for improving mapping information density in address mapping table |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107066393B (en) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109671458A (en) * | 2017-10-17 | 2019-04-23 | 联发科技股份有限公司 | The method of management flash memory module and relevant flash controller |
| KR20190044968A (en) * | 2017-10-23 | 2019-05-02 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
| CN108021511B (en) * | 2017-11-22 | 2021-04-06 | 深圳忆联信息系统有限公司 | SSD performance improving method and SSD |
| CN108037725B (en) * | 2017-12-08 | 2019-09-03 | 中冶南方工程技术有限公司 | A kind of method and apparatus for reading and writing plc data |
| CN108595349B (en) * | 2017-12-28 | 2020-01-31 | 贵阳忆芯科技有限公司 | Address translation method and device for mass storage device |
| CN109348456B (en) * | 2018-10-17 | 2021-07-27 | 安徽大学 | Relation mining method based on short-distance wireless communication data |
| CN111694770B (en) * | 2019-03-15 | 2022-12-02 | 杭州宏杉科技股份有限公司 | Method and device for processing IO (input/output) request |
| EP3963853B1 (en) * | 2019-04-29 | 2023-07-05 | Hitachi Vantara LLC | Optimizing storage and retrieval of compressed data |
| CN110688155A (en) * | 2019-09-11 | 2020-01-14 | 上海高性能集成电路设计中心 | Merging method for storage instruction accessing non-cacheable area |
| CN111026678B (en) * | 2019-12-23 | 2021-11-16 | 深圳忆联信息系统有限公司 | Cache design method and device based on solid state disk and computer equipment |
| CN111143313B (en) * | 2019-12-25 | 2023-07-25 | 成都三零嘉微电子有限公司 | Method for improving log block read-write performance of hybrid mapping algorithm |
| US11144471B1 (en) | 2020-05-07 | 2021-10-12 | Micron Technology, Inc. | Dual address encoding for logical-to-physical mapping |
| CN112486852B (en) * | 2020-12-01 | 2024-05-14 | 合肥大唐存储科技有限公司 | Solid state disk and address mapping method thereof |
| CN112631518B (en) * | 2020-12-25 | 2022-07-26 | 苏州浪潮智能科技有限公司 | Data storage method and equipment |
| WO2022140918A1 (en) * | 2020-12-28 | 2022-07-07 | Alibaba Group Holding Limited | Method and system for in-memory metadata reduction in cloud storage system |
| CN112860596B (en) * | 2021-02-07 | 2023-12-22 | 厦门壹普智慧科技有限公司 | Data stream cache device of neural network tensor processor |
| WO2022193143A1 (en) * | 2021-03-16 | 2022-09-22 | Micron Technology, Inc. | Validity mapping techniques |
| CN113419675B (en) * | 2021-06-11 | 2023-03-03 | 联芸科技(杭州)股份有限公司 | Write operation method and read operation method for memory |
| CN113590503B (en) * | 2021-07-23 | 2024-03-22 | 合肥康芯威存储技术有限公司 | Garbage recycling method and garbage recycling system for non-volatile memory |
| CN113590502B (en) * | 2021-07-23 | 2024-03-22 | 合肥康芯威存储技术有限公司 | Garbage recycling method and garbage recycling system for non-volatile memory storage equipment |
| CN114153384A (en) * | 2021-11-09 | 2022-03-08 | 尧云科技(西安)有限公司 | Storage method and device of hybrid cache |
| CN117370222A (en) * | 2023-12-08 | 2024-01-09 | 成都佰维存储科技有限公司 | Storage mapping method, storage mapping device, computer readable storage medium and electronic equipment |
| CN117806570B (en) * | 2024-02-29 | 2024-05-03 | 深存科技(无锡)有限公司 | Online memory expansion method, device, equipment and storage medium |
| CN117891415B (en) * | 2024-03-18 | 2024-05-24 | 深圳星火半导体科技有限公司 | P2L data management method and device of storage device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8291194B2 (en) * | 2009-11-16 | 2012-10-16 | Mediatek Inc. | Methods of utilizing address mapping table to manage data access of storage medium without physically accessing storage medium and related storage controllers thereof |
| CN105103137A (en) * | 2013-03-15 | 2015-11-25 | 西部数据技术公司 | Compression and formatting of data for data storage systems |
| CN105518631A (en) * | 2014-08-08 | 2016-04-20 | 华为技术有限公司 | Memory management method, device and system and network-on-chip |
| CN106021159A (en) * | 2016-05-12 | 2016-10-12 | 北京匡恩网络科技有限责任公司 | Logical block address-to-physical block address mapping method for high-capacity solid-state disk |
-
2017
- 2017-01-12 CN CN201710022698.0A patent/CN107066393B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8291194B2 (en) * | 2009-11-16 | 2012-10-16 | Mediatek Inc. | Methods of utilizing address mapping table to manage data access of storage medium without physically accessing storage medium and related storage controllers thereof |
| CN105103137A (en) * | 2013-03-15 | 2015-11-25 | 西部数据技术公司 | Compression and formatting of data for data storage systems |
| CN105518631A (en) * | 2014-08-08 | 2016-04-20 | 华为技术有限公司 | Memory management method, device and system and network-on-chip |
| CN106021159A (en) * | 2016-05-12 | 2016-10-12 | 北京匡恩网络科技有限责任公司 | Logical block address-to-physical block address mapping method for high-capacity solid-state disk |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107066393A (en) | 2017-08-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107066393B (en) | Method for improving mapping information density in address mapping table | |
| US20240126433A1 (en) | Method of controlling nonvolatile semiconductor memory | |
| US10303596B2 (en) | Read-write control method for memory, and corresponding memory and server | |
| US8516219B2 (en) | Index cache tree | |
| CN107102955B (en) | Association and atomic write-back cache system and method for storage subsystems | |
| US8688894B2 (en) | Page based management of flash storage | |
| US9471500B2 (en) | Bucketized multi-index low-memory data structures | |
| CN103425600B (en) | Address mapping method in a kind of solid-state disk flash translation layer (FTL) | |
| CN105930282B (en) | A kind of data cache method for NAND FLASH | |
| KR101297442B1 (en) | Nand flash memory including demand-based flash translation layer considering spatial locality | |
| CN103136121A (en) | Cache management method for solid-state disc | |
| CN109582593B (en) | FTL address mapping reading and writing method based on calculation | |
| KR20100021868A (en) | Buffer cache management method for flash memory device | |
| CN104503703B (en) | The treating method and apparatus of caching | |
| CN111580754B (en) | Write-friendly flash memory solid-state disk cache management method | |
| CN110968269A (en) | SCM and SSD-based key value storage system and read-write request processing method | |
| CN108664217B (en) | Caching method and system for reducing jitter of writing performance of solid-state disk storage system | |
| JP6595654B2 (en) | Information processing device | |
| KR101153688B1 (en) | Nand flash memory system and method for providing invalidation chance to data pages | |
| Liu et al. | Page replacement algorithm based on counting bloom filter for NAND flash memory | |
| CN110968520B (en) | Multi-stream storage device based on unified cache architecture | |
| KR101353967B1 (en) | Data process method for reading/writing data in non-volatile memory cache having ring structure | |
| KR101022001B1 (en) | Flash memory system and method for managing flash memory | |
| CN109960667B (en) | Address translation method and device for large-capacity solid-state storage device | |
| US20240070081A1 (en) | Method and system of using hmb as a cache of physical address mapping table |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |