CN106784010A - A kind of MOSFET with floating split layer grid - Google Patents
A kind of MOSFET with floating split layer grid Download PDFInfo
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- CN106784010A CN106784010A CN201710100069.5A CN201710100069A CN106784010A CN 106784010 A CN106784010 A CN 106784010A CN 201710100069 A CN201710100069 A CN 201710100069A CN 106784010 A CN106784010 A CN 106784010A
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- 238000007667 floating Methods 0.000 title claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 4
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 15
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of MOSFET with floating split layer grid, including：N+ substrate layers, N+ substrate layers are provided with N epitaxial layers, the centre and both sides of N epitaxial layers are respectively arranged with P body layers, P body layers of the left and right sides is respectively arranged with a Trench grooves and the 2nd Trench grooves, it is discontinuous P body layers between two Trench grooves, two Trench grooves are through P body layers to N epitaxial layers top；SiO is each filled with every Trench grooves2Layer, SiO2Two discontinuous Poly structures are provided with layer；Every Trench notches outside is with a circle N traps in P body layers；P body layers is provided with Metal layers；SiO in two Trench grooves2Overfill to Metal layers；In N epitaxial layers, the every Trench grooves lower section of correspondence is provided with p-type floating layer, and two p-type floatings layer is discontinuous.The present invention greatly optimizes the internal electric field of traditional split gate by the introducing of p-type floating layer：Optimize split gate in the case where outer mask is not needed, further reduce the Rsp of split gate, improve the breakdown voltage of split gate, obtain good electrostatic protection effect.
Description
Technical field
There is floating split layer gate MOSFET the present invention relates to semiconductor applications, more particularly to one kind.
Background technology
Traditional design, low pressure Splitting-gate Trench MOS structures in, it is pressure-resistant using thick oxide layer, can
To greatly improve electrical resistivity of epitaxy, so as to reduce Rsp.But the electric field born due to the bottom of its bottom splitting bar structure is more
It is high so as to puncture and occur in advance.
Traditional discrete device is single chip design and production, simply completed to the shut-off of circuit according to gate electrode signal and
Open, unitary function, lack and fed back with the signal of circuit system, it is difficult to accomplish Based Intelligent Control.
The content of the invention
The present invention is in order to reduce the spike electric field of trench bottoms so that epitaxial layer and trench bottoms electric field more
Plus it is flat, therefore under the premise of breakdown voltage identical is ensured, further can improve extension concentration further to reduce Rsp.
Meanwhile, realize the intelligent integrated class chip with power device job information sampling feedback so that device is in any working condition
Under can be with monitored management, so as to realize the adjustment of working condition.
Technical scheme is specific as follows：
A kind of MOSFET with floating split layer grid, including：N+ substrate layers, N+ substrate layers are provided with N- epitaxial layers, N-
The centre and both sides of epitaxial layer are respectively arranged with P-body layers, and P-body layers of the left and right sides is respectively arranged with a Trench grooves
It is discontinuous P-body layers between two Trench grooves with the 2nd Trench grooves, two Trench grooves are outside P-body layers to N-
Prolong a layer top；SiO is each filled with every Trench grooves2Layer, SiO2Two discontinuous Poly structures are provided with layer；Every Trench
Notch outside is with a circle N- traps in P-body layers；P-body layers is provided with Metal layers；SiO in two Trench grooves2Overfill
To Metal layers；
In N- epitaxial layers, the every Trench grooves lower section of correspondence is provided with p-type floating layer, and two p-type floatings layer is discontinuous.
It is preferred that p-type floating layer is not attached to corresponding Trench grooves.
It is preferred that p-type floating layer is connected with corresponding Trench grooves.
Using above-mentioned technical proposal, the present invention greatly optimizes traditional split-gate's by the introducing of p-type floating layer
Internal electric field：Optimize split-gate in the case where outer mask is not needed, further reduce the Rsp of split-gate, improve
The breakdown voltage of split-gate, obtains good electrostatic protection effect.
Brief description of the drawings
Fig. 1 is the structural representation in the vertical section of the embodiment of the present invention one；
Fig. 2 is the Electric Field Characteristics figure of the embodiment of the present invention one；
Fig. 3 is the structural representation in the vertical section of the embodiment of the present invention two；
Fig. 4 is the Electric Field Characteristics figure of the embodiment of the present invention two.
Specific embodiment
Below in conjunction with the drawings and specific embodiments, invention is described in detail.
With shown in Fig. 2, the present invention provides a kind of MOSFET with floating split layer grid to reference picture 1, including：N+ substrate layers
101, N+ substrate layers 101 are provided with N- epitaxial layers 102, and the centre and both sides of N- epitaxial layers 102 are respectively arranged with P-body layers
103, P-body layer 103 of the left and right sides is respectively arranged with a Trench grooves 104a and the 2nd Trench groove 104b, two
It is discontinuous P-body layers 103 between Trench grooves 104a/104b, two Trench grooves 104a/104b run through P-body layers 103
To the top of N- epitaxial layers 102；SiO is each filled with every Trench grooves 104a/104b2Layer 105, SiO2It is provided with layer 105 and is neither connected
Continuous Poly structures 106；104a/104b mouthfuls of outside of every Trench grooves is with a circle N- traps 107 in P-body layers；P-body
Layer 103 is provided with Metal layers 108；SiO in two Trench grooves 104a/104b2Layer 105 overfills to Metal layers 108；Outside N-
Prolong in layer 102, the every Trench grooves 104a/104b lower sections of correspondence are provided with p-type floating layer 109, and two p-type floatings layer 109 does not connect
It is continuous.
Fig. 1 show embodiments of the invention one, wherein, p-type floating layer 109 and corresponding Trench grooves 104a/104b
It is not attached to.This kind of structure of embodiment one, the Electric Field Characteristics figure of acquisition is shown in that Fig. 2, wherein curve L0 are to be not introduced into p-type floating layer
109 performance plot, L1 is the performance plot of the present embodiment one, and two p-types of floating are introduced in Trench groove 104a/104b bottoms
After layer, there is change in the electric field spike for originally occurring in Trench bottoms, and electric field becomes more flat, as above figure red curve, with
This considerably increases breakdown voltage.If ensureing that breakdown voltage is constant, Rsp can be greatly reduced with this.
Fig. 3 show embodiments of the invention two, wherein, p-type floating layer 109 and corresponding Trench grooves 104a/104b
It is connected.This kind of structure of embodiment two, the Electric Field Characteristics figure of acquisition is shown in that Fig. 4, wherein curve L0 are to be not introduced into p-type floating layer 109
Performance plot, curve L2 is the performance plot of the present embodiment two, and the p-type floating layer of Trench bottoms 109 can be with trench bottoms
Connection, the floating effect of P-type layer is reduced with this.More peak electric field electric fields will be moved into p type island region.Its same embodiment of effect
One structure is consistent, can improve breakdown voltage or reduce Rsp.When p-type is connected with floating layer with trench bottoms, trench sides
Face EPI regions pinch-off more earlier, the reduction of electric field that it bears, positive good utilisation this concentration in this region is improved into (this portion
Dividing concentration to improve can be realized by the not homepitaxy concentration of two-layer, it is also possible to high energy ion implantation realization is used before Body injections).Cause
This this region electric field will improve (as shown in Figure 4), and Rsp drops are greatly reduced.
The P-type layer of all of above structure is injected all after Trench etchings, and the just face passivation layer etched by trench-
Hard-mask stops to inject, without extra mask.
The above, the only present invention preferably specific embodiment, but protection scope of the present invention is not limited thereto,
Any one skilled in the art in the technical scope of present disclosure, technology according to the present invention scheme and its
Inventive concept is subject to equivalent or change, should all be included within the scope of the present invention.
Claims (3)
1. a kind of MOSFET with floating split layer grid, it is characterised in that including：N+ substrate layers, N+ substrate layers are provided with N-
Epitaxial layer, the centre and both sides of N- epitaxial layers are respectively arranged with P-body layers, and P-body layers of the left and right sides is respectively arranged with
One Trench grooves and the 2nd Trench grooves, are discontinuous P-body layers between two Trench grooves, and two Trench grooves run through P-
Body layers to N- epitaxial layers top；SiO is each filled with every Trench grooves2Layer, SiO2Two discontinuous Poly knots are provided with layer
Structure；Every Trench notches outside is with a circle N- traps in P-body layers；P-body layers is provided with Metal layers；Two Trench
SiO in groove2Overfill to Metal layers；
In N- epitaxial layers, the every Trench grooves lower section of correspondence is provided with p-type floating layer, and two p-type floatings layer is discontinuous.
2. the MOSFET with floating split layer grid according to claim 1, it is characterised in that p-type floating layer with it is corresponding
Trench grooves be not attached to.
3. the MOSFET with floating split layer grid according to claim 1, it is characterised in that p-type floating layer with it is corresponding
Trench grooves be connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710100069.5A CN106784010A (en) | 2017-02-23 | 2017-02-23 | A kind of MOSFET with floating split layer grid |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710100069.5A CN106784010A (en) | 2017-02-23 | 2017-02-23 | A kind of MOSFET with floating split layer grid |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106784010A true CN106784010A (en) | 2017-05-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710100069.5A Pending CN106784010A (en) | 2017-02-23 | 2017-02-23 | A kind of MOSFET with floating split layer grid |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109119489A (en) * | 2018-08-24 | 2019-01-01 | 电子科技大学 | A kind of metal-oxide-semiconductor diode of composite construction |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110254088A1 (en) * | 2010-04-20 | 2011-10-20 | Maxpower Semiconductor Inc. | Power MOSFET With Embedded Recessed Field Plate and Methods of Fabrication |
| CN103247681A (en) * | 2012-02-02 | 2013-08-14 | 万国半导体股份有限公司 | Nano MOSFET of trench bottom oxide shield and three-dimensional P-body contact region |
| CN103390545A (en) * | 2012-05-08 | 2013-11-13 | 上海华虹Nec电子有限公司 | Method for increasing drain-source breakdown voltage of trench NMOS and structure of trench NMOS |
| US8829607B1 (en) * | 2013-07-25 | 2014-09-09 | Fu-Yuan Hsieh | Fast switching super-junction trench MOSFETs |
| CN206471336U (en) * | 2017-02-23 | 2017-09-05 | 深圳市迪浦电子有限公司 | A kind of MOSFET with floating split layer grid |
-
2017
- 2017-02-23 CN CN201710100069.5A patent/CN106784010A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110254088A1 (en) * | 2010-04-20 | 2011-10-20 | Maxpower Semiconductor Inc. | Power MOSFET With Embedded Recessed Field Plate and Methods of Fabrication |
| CN103247681A (en) * | 2012-02-02 | 2013-08-14 | 万国半导体股份有限公司 | Nano MOSFET of trench bottom oxide shield and three-dimensional P-body contact region |
| CN103390545A (en) * | 2012-05-08 | 2013-11-13 | 上海华虹Nec电子有限公司 | Method for increasing drain-source breakdown voltage of trench NMOS and structure of trench NMOS |
| US8829607B1 (en) * | 2013-07-25 | 2014-09-09 | Fu-Yuan Hsieh | Fast switching super-junction trench MOSFETs |
| CN206471336U (en) * | 2017-02-23 | 2017-09-05 | 深圳市迪浦电子有限公司 | A kind of MOSFET with floating split layer grid |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109119489A (en) * | 2018-08-24 | 2019-01-01 | 电子科技大学 | A kind of metal-oxide-semiconductor diode of composite construction |
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Application publication date: 20170531 |