CN106298627A - The manufacture method of a kind of semiconductor device and electronic installation - Google Patents
The manufacture method of a kind of semiconductor device and electronic installation Download PDFInfo
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- CN106298627A CN106298627A CN201510259140.5A CN201510259140A CN106298627A CN 106298627 A CN106298627 A CN 106298627A CN 201510259140 A CN201510259140 A CN 201510259140A CN 106298627 A CN106298627 A CN 106298627A
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- 238000000034 method Methods 0.000 title claims abstract description 79
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000009434 installation Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 166
- 238000002955 isolation Methods 0.000 claims abstract description 49
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 40
- 239000010703 silicon Substances 0.000 claims abstract description 40
- 239000000463 material Substances 0.000 claims description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 230000009467 reduction Effects 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000000227 grinding Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 239000011469 building brick Substances 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- 238000012856 packing Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 3
- 238000010009 beating Methods 0.000 claims description 2
- 238000010276 construction Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 11
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 9
- 238000005530 etching Methods 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000004567 concrete Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000011513 prestressed concrete Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
The present invention provides manufacture method and the electronic installation of a kind of semiconductor device, relates to technical field of semiconductors.Including: the first substrate is provided, forms the deep trench isolation structure being positioned at the first substrate from the first surface of the first substrate；First substrate of first surface side is formed at least one front-end devices, forms the first dielectric cap cap layers covering first surface and the interconnection structure being positioned at the first dielectric cap cap layers；Carrying substrate is provided, the side being formed with the first dielectric cap cap layers of the first substrate is engaged with carrying substrate；From the second surface relative with first surface, the first substrate is carried out thinning, stop in deep trench isolation structure；The second surface of the first substrate is formed the second dielectric cap cap layers, forms at least one silicon through hole.The method of the present invention uses simpler and ripe processing technology to achieve the processing to body silicon substrate and obtain the device architecture essentially identical with using SOI substrate, can reduce cost.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to the system of a kind of semiconductor device
Make method and electronic installation.
Background technology
SOI (Silicon-On-Insulator, i.e. silicon-on-insulator) refers to the dielectric substrate at silicon
On form a thin layer monocrystal silicon again, or monocrystalline thin silicone layer is separated from silicon substrate by insulating barrier,
The material of this structure can make device and substrate completely isolated, and traditional employing body silicon conduct
All devices of substrate are shared a substrate and be there is not any physical dielectric separation.
Compared with conventional bulk silicon technology, SOI technology has the advantage that ghost effect is little, merit
Depletion is little, speed improves, integrated level is high, capability of resistance to radiation strengthens, eliminate latch up effect,
Leakage current is little, can provide good Fully dielectric isolation etc. for device and circuit, in view of above-mentioned advantage
Existence, SOI technology is at low pressure, low consumption circuit, high-frequency microwave circuit and high temperature resistant anti-
Raddiating circuit and three dimensional integrated circuits have a wide range of applications.
Although SOI technology has an advantage that many body silicon is incomparable, but the system of SOI substrate
Standby complicated so that SOI substrate is relatively costly, directly constrains its application in semiconductor industry.
Correspondingly, use the semiconductor device (such as radio frequency front-end devices) of silicon-on-insulator substrate,
Often cost is higher.
Deep trench isolation (DTI) technique has been widely studied and applied a very long time, with
This simultaneously, the melted bonding/stacking of Silicon Wafer and back process are in the back side work of thin film silicon device
Application in skill is the most ripe, and thinning back side to 2 μm also has total thickness variations (TTV)
Be 0.3 μm technological standards require applied a large amount of device products.
Therefore, it is necessary to propose the manufacture method of a kind of semiconductor device, not use insulation
On body in the case of silicon substrate, the maturation process such as existing deep trench isolation are used to complete quasiconductor
The manufacture of device, thus reduce the cost of semiconductor device.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will be concrete real
Execute in mode part and further describe.The Summary of the present invention is not meant to
Attempt to limit key feature and the essential features of technical scheme required for protection, less
Mean the protection domain attempting to determine technical scheme required for protection.
For the deficiencies in the prior art, the embodiment of the present invention one provides the system of a kind of semiconductor device
Making method, described method includes:
Step S201: provide the first substrate, forms position from the first surface of described first substrate
Deep trench isolation structure in described first substrate；
Step S202: form at least one on described first substrate of described first surface side
Individual front-end devices, is formed and covers the first dielectric cap cap layers of described first surface and be positioned at described
Interconnection structure in first dielectric cap cap layers；
Step S203: carrying substrate is provided, described first substrate is formed with described first
The side of dielectric cap cap layers engages with described carrying substrate；
Step S204: from the second surface relative with described first surface to described first substrate
Carry out reduction processing, stop in described deep trench isolation structure；
Step S205: form the second dielectric cap on the described second surface of described first substrate
Cap layers, is formed and runs through described second dielectric cap cap layers, described deep trench isolation structure and part institute
State the first dielectric cap cap layers and at least one the silicon through hole being connected with described interconnection structure.
In one example, the step forming described deep trench isolation structure includes:
Step S2011: form the mask layer of patterning on the first surface of described first substrate,
In described mask layer, the size of deep trench isolation structure has been stated in definition；
Step S2012: with the mask layer of described patterning as mask, etch described first substrate
Form deep trench；
Step S2013: fill deep trench isolation material in described deep trench.
Further, described step S2013 includes:
Full polysilicon layer is filled in described deep trench；
Polysilicon layer described in etch-back；
Described polysilicon layer is formed silicon oxide layer；
Described silicon oxide layer is carried out cmp, stops at the first of described first substrate
On surface.
Further, the method that described polysilicon layer is aoxidized is used to form described silicon oxide
Layer.
Further, between described step S2012 and described step S2013, it is additionally included in institute
State the step forming laying on the sidewall of deep trench.
Further, the packing material of described deep trench isolation structure includes that stacking is many from bottom to top
Crystal silicon layer and silicon oxide layer.
Further, the depth bounds of described deep trench isolation structure is 1～3 μm.
Further, in described step S204, described reduction processing includes:
Step S2041: described first substrate is carried out grinding back surface process；
Step S2042: described first substrate is carried out CMP and makes described CMP stop at institute
State the bottom of deep trench isolation structure.
Further, also include described between described step S2041 and described step S2042
First substrate carries out the step of wet etching.
Further, further comprising the steps of after described step S205:
The described second surface of described first substrate is formed the weldering being connected with described silicon through hole
Dish；
Form the described second surface of described first substrate of covering but expose beating of described pad
The passivation layer in line district.
Further, described front-end devices includes transistor.
Further, described transistor includes source electrode, drain and gate structure, wherein, described source
Pole and described drain electrode are positioned at the lower section of described first surface, and described grid structure is positioned at described first
The top on surface.
Further, described first substrate includes body silicon substrate.
The embodiment of the present invention two provides a kind of electronic installation, including electronic building brick and with this electronics
The semiconductor device that assembly is connected, the manufacture method of wherein said semiconductor device includes:
Step S201: provide the first substrate, forms position from the first surface of described first substrate
Deep trench isolation structure in described first substrate；
Step S202: form at least one on described first substrate of described first surface side
Individual front-end devices, is formed and covers the first dielectric cap cap layers of described first surface and be positioned at described
Interconnection structure in first dielectric cap cap layers；
Step S203: carrying substrate is provided, described first substrate is formed with described first
The side of dielectric cap cap layers engages with described carrying substrate；
Step S204: from the second surface relative with described first surface to described first substrate
Carry out thinning, stop in described deep trench isolation structure；
Step S205: form the second dielectric cap on the described second surface of described first substrate
Cap layers, is formed and runs through described second dielectric cap cap layers, described deep trench isolation structure and part institute
State the first dielectric cap cap layers and at least one the silicon through hole being connected with described interconnection structure.
The manufacture method of the semiconductor device of the embodiment of the present invention, by engaging on the first substrate
Carrying substrate also carries out reduction processing to the first substrate, can with common body silicon substrate rather than exhausted
On edge body, silicon substrate is as the first substrate, and the method for the present invention uses simpler and ripe system
Achieve the processing to body silicon substrate as technique and obtain with to use SOI substrate essentially identical
Device architecture, can reduce cost.The electronic installation of the present invention, including using the method manufacture
Semiconductor device, thus there is above-mentioned advantage equally.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Attached
Figure shows embodiments of the invention and description thereof, is used for explaining the principle of the present invention.
In accompanying drawing:
Figure 1A, Figure 1B, Fig. 1 C, Fig. 1 D and Fig. 1 E is one embodiment of the present of invention
The sectional view of the structure that the correlation step of the manufacture method of a kind of semiconductor device is formed；
Fig. 2 is showing of the manufacture method of a kind of semiconductor device of one embodiment of the present of invention
Meaning property flow chart.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention more
Understand thoroughly.It is, however, obvious to a person skilled in the art that the present invention
Can be carried out without these details one or more.In other example, in order to keep away
Exempt to obscure with the present invention, technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, it is open thoroughly with complete to provide these embodiments to make
Entirely, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
In order to clear, the size in Ceng He district and relative size may be exaggerated.The most identical attached
Figure labelling represents identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... adjacent ", " being connected to "
Or when " being coupled to " other element or layer, its can directly on other element or layer and
Adjacent, be connected or coupled to other element or layer, or element between two parties or layer can be there is.
On the contrary, when element be referred to as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other element or layer, the most there is not element between two parties or layer.Should
Understand, although can use term first, second, third, etc. describe various element, parts,
District, floor and/or part, these elements, parts, district, floor and/or part should be by these
Term limits.These terms be used merely to distinguish an element, parts, district, floor or part with
Another element, parts, district, floor or part.Therefore, under without departing from present invention teach that,
First element discussed below, parts, district, floor or part be represented by the second element, parts,
District, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ... it
Under ", " ... on ", " above " etc., here can describe for convenience and used from
And shown in figure a element or feature and other element or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term is intended to also include using and operating
In the different orientation of device.Such as, if the device upset in accompanying drawing, then, it is described as
" below other element " or " under it " or " under it " element or feature will orientations
For other element or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " upper and lower two orientations can be included.Device can additionally be orientated (90-degree rotation or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When using at this, " ", " " and " described/to be somebody's turn to do " of singulative
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " forms " and/or " including ", when using in this specification, determine described feature,
The existence of integer, step, operation, element and/or parts, but be not excluded for one or more its
The existence of its feature, integer, step, operation, element, parts and/or group or interpolation.
When using at this, term "and/or" includes any and all combination of relevant Listed Items.
Horizontal stroke herein with reference to the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Sectional view describes inventive embodiment.As a result, it is contemplated that due to such as manufacturing technology and/
Or the change from shown shape that tolerance causes.Therefore, embodiments of the invention should not limit to
In the given shape in district shown here, but include owing to such as manufacturing the shape caused inclined
Difference.Such as, be shown as the injection region of rectangle be generally of at its edge round or bending features and
/ or implantation concentration gradient rather than the binary from injection region to non-injection regions change.Equally,
The disposal area formed by injection may result in this disposal area and inject when carrying out the surface of process
Between district in some inject.Therefore, in figure, the district of display is substantially schematic, it
Shape be not intended the true form in district of display device and be not intended to limit the present invention
Scope.
In order to thoroughly understand the present invention, detailed step and in detail will be proposed in following description
Thin structure, in order to the technical scheme that the explaination present invention proposes.Presently preferred embodiments of the present invention is detailed
Carefully it is described as follows, but in addition to these describe in detail, the present invention can also have other and implement
Mode.
Embodiment one
Below, describe one embodiment of the present of invention with reference to Figure 1A to Fig. 1 E and Fig. 2 to carry
The manufacture method of a kind of semiconductor device gone out.Wherein, Figure 1A to Fig. 1 E is the present invention's
The structure that the correlation step of the manufacture method of a kind of semiconductor device of one embodiment is formed
Sectional view；Fig. 2 is the manufacture method of a kind of semiconductor device of one embodiment of the present of invention
Indicative flowchart.
Exemplarily, the manufacture method of the semiconductor device of one embodiment of the present of invention, including
Following steps:
First, as shown in Figure 1A, it is provided that the first substrate 100, from described first substrate 100
First surface 1001 formed and be positioned at the deep trench isolation structure of described first substrate 100
101。
First substrate 100 can be body silicon (bulk Si) substrate or other various suitable substrates.
Without as in the prior art, use silicon-on-insulator substrate (SOI) or High resistivity substrate
(high-resistance substrate)。
Wherein, relative with the first surface of the first substrate 100 (also referred to as upper surface) 1001
Surface is referred to as second surface (also referred to as lower surface) 1002, as shown in Figure 1A.
Exemplarily, the depth bounds of described deep trench isolation structure is 1～3 μm.
In one example, the step forming described deep trench isolation structure 101 is included below:
First, the first surface of described first substrate forms the mask layer of patterning, described
In mask layer, the size of deep trench isolation structure has been stated in definition；Mask layer generally can include number
Plant any one of mask material, include but not limited to: hard mask material and photoresist mask material
Material.It is preferred that mask layer includes photoresist mask material.
Then, with the mask layer of described patterning as mask, etch described first substrate and formed deeply
Groove.This etching is preferably deep dry etch process, such as reactive ion etching, ion beam etching,
The combination in any of plasma etching, laser ablation or these methods.Single quarter can be used
Etching method, or more than one lithographic method can also be used.Zanjon according to predetermined formation
The degree of depth of recess isolating structure sets the degree of depth of etching, and such as, forming depth bounds is 1～3 μ
The deep trench of m.
Then, in described deep trench, deep trench isolation material is filled.Alternatively, described zanjon
The packing material of recess isolating structure includes polysilicon layer and the silicon oxide layer of stacking from bottom to top.Show
Example ground, fills deep trench isolation material and comprises the following steps: fill full in described deep trench
Polysilicon layer, polysilicon layer described in etch-back, described polysilicon layer is formed silicon oxide layer,
The method that described polysilicon layer is aoxidized can be used to form described silicon oxide layer, it is also possible to adopt
Form described silicon oxide layer by methods such as chemical gaseous phase substrates, afterwards, described silicon oxide layer is entered
Row cmp, stops on the first surface of described first substrate, and this chemical machinery grinds
Mill step is by beyond deep trench top.Material layer (the bag more than first surface of the first substrate
Include unnecessary silicon oxide layer) grind and remove.
Before filling deep trench isolation material, it is additionally included on the sidewall of described deep trench formation
The step of laying (not shown).Laying can include any one of several gasket materials,
Include but not limited to: silicon oxide liner cushion material and silicon nitride liner material, in the present embodiment, lining
Bed course is preferably chosen as including silicon oxide liner cushion material.One also can be carried out after forming laying
Step annealing step, with the stress accumulated in release liner material.
Afterwards, as shown in Figure 1B, at described first lining of described first surface 1001 side
Form at least one front-end devices 102 at the end 100, formed and cover described first surface 1001
The first dielectric cap cap layers 103 and be positioned at the mutual link of described first dielectric cap cap layers 103
Structure 104.
Exemplarily, described front-end devices includes transistor 102.Form the step of front-end devices
Including FEOL and last part technology.Described transistor 102 includes source electrode 1022, drain electrode 1023
With grid structure 1021, wherein, described source electrode 1022 and described drain electrode 1023 are positioned at described
The lower section of first surface 1001, described grid structure 1021 is positioned at described first surface 1001
Top.Technique well known to those skilled in the art can be used to form described front-end devices.Grid
Structure 1021 includes gate dielectric from bottom to top and gate material layers.Form grid structure
The method of 1021 can be first grid technology or post tensioned unbonded prestressed concrete technique.
Wherein, formed while transistor, it is also possible to form other devices, such as diode,
Resistance, electric capacity etc., be not defined at this.
The method of the embodiment of the present invention, directly at body silicon substrate rather than on silicon-on-insulator substrate
Form the devices such as transistor.The technique forming the devices such as transistor is formed with on body silicon substrate
The technique of cmos device completes identical.
Form the first dielectric cap cap layers 103 covering described first surface 1001, this first Jie
Electricity cap covers and covers front-end devices 102 simultaneously, and the first dielectric cap cap layers 103 can include
Any one of several dielectric substances.Limiting examples includes oxide, nitride and nitrogen
Oxide, especially, the oxide of silicon, nitride and nitrogen oxides, but do not include other yuan
Oxide, nitride and the nitrogen oxides of element.First dielectric cap cap layers 103 can include crystal
Or noncrystal dielectric substance.Usual highly preferred crystal current dielectric material.Can be used several
Any one of method forms the first dielectric cap cap layers 103.Limiting examples includes chemistry
Vapour deposition method and physical vapor deposition methods.
It is positioned at the interconnection structure 104 of described first dielectric cap cap layers 103.Interconnection structure 104
For connecting at least one in source electrode 1022, drain electrode 1023 and grid structure 1021.Mutually
The material linking structure 104 can be conducting metal (such as copper) or other suitable materials.
Then, as shown in Figure 1 C, it is provided that carrying substrate 200, by described first substrate 100
The side being formed with described first dielectric cap cap layers 103 connect with described carrying substrate 200
Close.
In one example, the first substrate 100 is being formed with the first dielectric cap cap layers 103
Side and carrying before substrate 200 engages, be first formed with first at the first substrate 100
Distinguish on the surface of the side of dielectric cap cap layers 103 and on the carrying corresponding surface of substrate 200
Form bonding cap.Exemplarily, bonding cap 300 material can be silicon oxide or
Other suitable materials.
Exemplarily, by the method that the first substrate 100 engages with carrying substrate 200 can be
Melted bonding (fusion bonding) or other suitable methods.In the present embodiment, preferably
It is bonded for oxide fusion.
Wherein, carrying substrate 200 can be silicon substrate or other suitable substrates.Show at one
In example, carrying substrate 200 has the same shape and dimensions with the first substrate 100.
Wherein, carrying substrate 200 can carry out reduction processing follow-up to the first substrate 100
During to first substrate 100 provide support.
Then, as shown in figure ip, from the second surface relative with described first surface 1001
1002 pairs of described first substrates 100 carry out reduction processing, stop at described deep trench isolation knot
In structure 101.
Described reduction processing includes: described first substrate 100 is carried out grinding back surface (backside
Grinding) process, then the first substrate 100 is carried out wet etching.Wherein, used
Method for grinding rear surface can be CMP (cmp) or other suitable technique.
Described wet etching can use various feasible etching liquid, such as TMAH etc., at this also
It is not defined.
Continue from the second surface 1002 relative with first surface 1001, first substrate 100 to be entered
Row reduction processing, including: described first substrate 100 is carried out CMP and makes described CMP
Stop at the bottom of described deep trench isolation structure 101.Exemplarily, deep trench isolation structure
Interior packing material (such as polysilicon layer) is as the stop-layer of this CMP, through this step,
The structure formed is as shown in figure ip.Wherein, this CMP can use various feasible CMP
Technique.Reduction process can realize the thickness thinning close to 2 μm and total thickness variations the most easily
It is the technological standards of 0.3 μm, therefore can well ensure the quality of substrate.
The method of the embodiment of the present invention, owing to including engaging on the first substrate carrying substrate right
First substrate carries out the step of reduction processing, and therefore, the first substrate can use common body silicon
(bulk Si) substrate is as basic device layer substrate, without using silicon-on-insulator substrate
(SOI) or High resistivity substrate (high-resistance substrate), therefore the method for the present invention is adopted
Achieve the processing to body silicon substrate by simpler and ripe processing technology and obtain and use
The device architecture that SOI substrate is essentially identical, can reduce cost.
Further, the method for the present embodiment by use simultaneously deep trench isolation, grinding back surface,
The method such as CMP, wet etching (being matched by multiple stop-layers) carries out reduction processing, can
The first substrate is carried out accurate reduction processing to desired thickness, and homogeneous desired by ensureing
Property.
Additionally, due to the bonding technology between deep trench isolation technique, silicon substrate and thinning work
Skill is more ripe, and therefore the method for the present embodiment is while reducing cost, it is also possible to
Ensure the yield of the semiconductor device prepared.
Then, as referring to figure 1e, at the described second surface 1002 of described first substrate 100
Upper formation the second dielectric cap cap layers 105, is formed and runs through described second dielectric cap cap layers 105, institute
State deep trench isolation structure 101 and the described first dielectric cap cap layers 103 of part and with described interconnection
At least one silicon through hole 106 that structure 104 is connected.
Exemplarily, the method forming silicon through hole (TSV) 106 includes: etching formation runs through
Second dielectric cap cap layers 105, described deep trench isolation structure 101 and described first dielectric of part
The via of cap 103；
Conductive material is filled in this via；
The conductive material of excess is removed to form silicon through hole 106 by CMP.
Wherein, conductive material can be metal or other suitable materials, metal can be copper,
Aluminum, tungsten, stannum etc..
The most further comprising the steps of: at the described second surface 1002 of described first substrate 100
The pad 107 that upper formation is connected with described silicon through hole 106, is formed and covers described first substrate 100
Described second surface 1002 but expose the passivation layer in the routing district of described pad 107 (not
Illustrate).
The material of pad 107 can be metal or other suitable material, and metal is preferably aluminum
Metal.
So far, the committed step of the manufacture method of the semiconductor device of the embodiment of the present invention is completed
Introduction.It will be understood to those skilled in the art that in addition to above-mentioned step, and in phase
Between adjacent step, it is also possible to include other feasible steps, be not defined at this.
The manufacture method of the semiconductor device of the embodiment of the present invention, by engaging on the first substrate
Carrying substrate also carries out reduction processing to the first substrate, can with common body silicon substrate rather than exhausted
On edge body, silicon substrate is as the first substrate, and the method for the present invention uses simpler and ripe system
Achieve the processing to body silicon substrate as technique and obtain with to use SOI substrate essentially identical
Device architecture, can reduce cost.
Fig. 2 shows the manufacture method of a kind of semiconductor device that the embodiment of the present invention proposes
A kind of indicative flowchart, for schematically illustrating the typical process of said method.Specifically include:
In step s 201, it is provided that the first substrate, from the first surface shape of described first substrate
Become to be positioned at the deep trench isolation structure of described first substrate；
In step S202, described first substrate of described first surface side is formed to
A few front-end devices, is formed and covers the first dielectric cap cap layers of described first surface and be positioned at
Interconnection structure in described first dielectric cap cap layers；
In step S203, it is provided that carrying substrate, by described for being formed of described first substrate
The side of the first dielectric cap cap layers engages with described carrying substrate；
In step S204, from the second surface relative with described first surface to described first
Substrate carries out reduction processing, stops in described deep trench isolation structure；
In step S205, the described second surface of described first substrate forms second Jie
Electricity cap, is formed and runs through described second dielectric cap cap layers, described deep trench isolation structure and portion
Divide described first dielectric cap cap layers and at least one the silicon through hole being connected with described interconnection structure.
Embodiment two
An alternative embodiment of the invention provides a kind of electronic installation, it include electronic building brick and
The semiconductor device being connected with this electronic building brick.Wherein, as above institute according to this semiconductor device
Semiconductor device obtained by the manufacture method of the semiconductor device stated.This electronic building brick can be
Any suitable assembly.
Exemplarily, the manufacture method of this semiconductor device includes:
Step S201: provide the first substrate, forms position from the first surface of described first substrate
Deep trench isolation structure in described first substrate；
Step S202: form at least one on described first substrate of described first surface side
Individual front-end devices, is formed and covers the first dielectric cap cap layers of described first surface and be positioned at described
Interconnection structure in first dielectric cap cap layers；
Step S203: carrying substrate is provided, described first substrate is formed with described first
The side of dielectric cap cap layers engages with described carrying substrate；
Step S204: from the second surface relative with described first surface to described first substrate
Carry out thinning, stop in described deep trench isolation structure；
Step S205: form the second dielectric cap on the described second surface of described first substrate
Cap layers, is formed and runs through described second dielectric cap cap layers, described deep trench isolation structure and part institute
State the first dielectric cap cap layers and at least one the silicon through hole being connected with described interconnection structure.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, on
Net basis, game machine, television set, VCD, DVD, navigator, photographing unit, video camera,
Any electronic product such as recording pen, MP3, MP4, PSP or equipment, it is possible to include for any
The intermediate products of this semiconductor device.
The electronic installation of the embodiment of the present invention, partly leads according to what said method prepared owing to employing
Body device, thus there is above-mentioned advantage equally.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repair
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and equivalent scope thereof.
Claims (14)
1. the manufacture method of a semiconductor device, it is characterised in that described method includes:
Step S201: provide the first substrate (100), from the of described first substrate (100)
One surface (1001) forms the deep trench isolation structure being positioned at described first substrate (100)
(101)；
Step S202: described first substrate (100) of described first surface (1001) side
At least one front-end devices of upper formation (102), is formed and covers described first surface (1001)
First dielectric cap cap layers (103) and be positioned at the mutual of described first dielectric cap cap layers (103)
Link structure (104)；
Step S203: provide carrying substrate (200), by the shape of described first substrate (100)
Become to have the side of described first dielectric cap cap layers (103) to connect with described carrying substrate (200)
Close；
Step S204: from the second surface (1002) relative with described first surface (1001)
Described first substrate (100) is carried out reduction processing, stops at described deep trench isolation structure
(101) in；
Step S205: on the described second surface (1002) of described first substrate (100)
Form the second dielectric cap cap layers (105), formed run through described second dielectric cap cap layers (105),
Described deep trench isolation structure (101) and the described first dielectric cap cap layers (103) of part and with
At least one silicon through hole (106) that described interconnection structure (104) is connected.
Manufacture method the most according to claim 1, it is characterised in that formed described deeply
The step of groove isolation construction includes:
Step S2011: form the mask layer of patterning on the first surface of described first substrate,
In described mask layer, the size of deep trench isolation structure has been stated in definition；
Step S2012: with the mask layer of described patterning as mask, etch described first substrate
Form deep trench；
Step S2013: fill deep trench isolation material in described deep trench.
Manufacture method the most according to claim 2, it is characterised in that described step S2013
Including:
Full polysilicon layer is filled in described deep trench；
Polysilicon layer described in etch-back；
Described polysilicon layer is formed silicon oxide layer；
Described silicon oxide layer is carried out cmp, stops at the first of described first substrate
On surface.
Manufacture method the most according to claim 3, it is characterised in that use described
The method that polysilicon layer carries out aoxidizing forms described silicon oxide layer.
Manufacture method the most according to claim 2, it is characterised in that in described step
Between S2012 and described step S2013, it is additionally included on the sidewall of described deep trench formation lining
The step of bed course.
Manufacture method the most according to claim 1, it is characterised in that described deep trench
The packing material of isolation structure includes polysilicon layer and the silicon oxide layer of stacking from bottom to top.
Manufacture method the most according to claim 1, it is characterised in that described deep trench
The depth bounds of isolation structure is 1～3 μm.
Manufacture method the most according to claim 1, it is characterised in that in described step
In S204, described reduction processing includes:
Step S2041: described first substrate is carried out grinding back surface process；
Step S2042: described first substrate is carried out CMP and makes described CMP stop at institute
State the bottom of deep trench isolation structure.
Manufacture method the most according to claim 8, it is characterised in that in described step
Also include between S2041 and described step S2042 described first substrate is carried out wet etching
Step.
Manufacture method the most according to claim 1, it is characterised in that in described step
After S205 further comprising the steps of:
The described second surface of described first substrate is formed the weldering being connected with described silicon through hole
Dish；
Form the described second surface of described first substrate of covering but expose beating of described pad
The passivation layer in line district.
11. manufacture methods according to claim 1, it is characterised in that described front end-apparatus
Part includes transistor.
12. manufacture methods according to claim 11, it is characterised in that described crystal
Pipe includes source electrode, drain and gate structure, and wherein, described source electrode and described drain electrode are positioned at described
The lower section of first surface, described grid structure is positioned at the top of described first surface.
13. manufacture methods according to claim 1, it is characterised in that described first lining
The end, includes body silicon substrate.
14. 1 kinds of electronic installations, it is characterised in that include electronic building brick and with this electronics group
The semiconductor device that part is connected, the manufacture method of wherein said semiconductor device includes:
Step S201: provide the first substrate, forms position from the first surface of described first substrate
Deep trench isolation structure in described first substrate；
Step S202: form at least one on described first substrate of described first surface side
Individual front-end devices, is formed and covers the first dielectric cap cap layers of described first surface and be positioned at described
Interconnection structure in first dielectric cap cap layers；
Step S203: carrying substrate is provided, described first substrate is formed with described first
The side of dielectric cap cap layers engages with described carrying substrate；
Step S204: from the second surface relative with described first surface to described first substrate
Carry out thinning, stop in described deep trench isolation structure；
Step S205: form the second dielectric cap on the described second surface of described first substrate
Cap layers, is formed and runs through described second dielectric cap cap layers, described deep trench isolation structure and part institute
State the first dielectric cap cap layers and at least one the silicon through hole being connected with described interconnection structure.
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| CN113608197A (en) * | 2021-07-30 | 2021-11-05 | 联合微电子中心有限责任公司 | Optical antenna, method of manufacturing the same, and optical phased array chip |
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