CN106067817A - 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate gradual approaching A/D converter - Google Patents
1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate gradual approaching A/D converter Download PDFInfo
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- CN106067817A CN106067817A CN201610411806.9A CN201610411806A CN106067817A CN 106067817 A CN106067817 A CN 106067817A CN 201610411806 A CN201610411806 A CN 201610411806A CN 106067817 A CN106067817 A CN 106067817A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
- H03M1/0695—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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Abstract
The invention belongs to technical field of integrated circuits, be specially the gradual approaching A/D converter that 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate.The analog-digital converter structure that the present invention provides includes two identical boot-strapped switch, one group of symmetrical N position binary capacitor array, two controlled asymmetric dynamic comparators, a common dynamic comparer and the Digital Logical Circuits module of SAR ADC.Present invention introduces 1.5 redundancy bits speed technologies, shorten former of wait and set up the time completely, accelerate the switching rate of analog-digital converter, add redundancy, reduce error code, lose code, improve precision.Compared to conventional art, can significantly simplify circuit scale, particularly omit generating circuit from reference voltage, then power consumption and the area of analog-digital converter are reduced, equivalence reference voltage level is set up in change rapidly, accelerate the conversion speed of analog-digital converter, and there is universality, can apply to the application scenarios of other 0.5 bits.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of based on controlled asymmetric dynamic comparator 1.5
Redundancy bits accelerates successive approximation digital to analog converter.
Background technology
The technology of 1.5 bits is widely used in flow-line modulus converter, with cross increase redundancy eliminate by
The precision of A/D converter that static offset error causes by a small margin declines.And 1.5 apply at Approach by inchmeal for the first time than trick
In pattern number converter, or Chun-Cheng Liu and Soon-Jyh Chang in 2010 at super large-scale integration
Issue first in meeting (Symposium on VLSI circuits), although the most do not propose the concept of 1.5 bits, but
The redundancy approach wherein implemented is strictly the way of 1.5 bits.It is that Chun-Cheng Liu delivers in this meeting shown in Fig. 1
The structure of the gradual approaching A/D converter of front four 10MS/s, 10bit top plate samplings using 1.5 bits to compare foundation
Schematic diagram.Fig. 1 mainly includes two boot-strapped switch 101, with input signal and the climax of 10 binary capacitor array 102
Plate and node 103,104 connect；10 binary capacitor array 102, the top plate of capacitor array link together with dynamically than
Relatively device 105,106,107 is connected to node 103,104, and the structure of traditional top plate sampling gradual approaching A/D converter
Comparing, front four two parts being split into equivalent of the capacitor array 102 of Fig. 1, turning to of sole plate level is individually controlled；
Dynamic comparer 105,106,107, the dynamic comparer quantity of figure one is no longer one in traditional structure, and is extended to three
Individual, wherein 106,107 compare foundation for 1.5 bits；One six seat digital to analog converter 108, is overturn by electric capacity sole plate
Producing every grade of 1.5 bits and compare the reference voltage of foundation, the Approach by inchmeal analog-digital converter that this partial circuit is traditional does not has
's；SAR ADC application of logic circuit module 109, clock producing method, control level conversion direction and output code combination logic and tradition
Gradual approaching A/D converter also has difference.
Front four 1.5 bits of structure shown in Fig. 1 are to be turned by 106,107 and six seat digital-to-analogue of two dynamic comparers
Parallel operation realizes.Two dynamic comparers 106,107 connect top plate and the six seat digital-to-analogues of 10 symmetrical capacitor arrays respectively
Transducer 108, the input of i.e. two dynamic comparers 106,107 connects node 103,110 and node 104,110 respectively.Six
Position sub-adc converter 108 produce reference voltage range be common-mode voltage 1/2nd to common-mode voltage 16/
15, when two capacitor array top crown voltages are all higher than reference voltage, this low pole plate of capacitance group does not overturns；When two
Capacitor array top crown voltage one be less than reference voltage, one higher than reference voltage time, the capacitance group sole plate earthing of high side,
The capacitance group sole plate of downside connects reference voltage.
The working method of foregoing circuit is as follows.When CK is high level, and boot-strapped switch 101 is opened, and input signal is adopted
Sample on the top plate of the binary capacitor array 102 of analog-digital converter, now capacitance group C1a~C4aSole plate earthing, remaining
Capacitance group (C1b~C4bAnd C5~C9) connecing reference voltage, dynamic comparer 105,106,107 is turned off, and analog-digital converter is in be adopted
The sample stage.When CK is low level, and boot-strapped switch 101 turns off, and capacitor array 102 is unsettled, and the quantity of electric charge is constant, the trailing edge moment
Input signal be just held on capacitor array 102, analog-digital converter is in quantization stage.The input signal difference that will keep
Being compared with reference voltage by two dynamic comparers 106,107, the data of comparator are transferred to the application of logic circuit module of SAR ADC
In 109, combined logic produces logic control signal, controls first capacitance group C1aAnd C1bThe reverses direction of sole plate, through one
After the foundation of section time completely, start the comparison of next 1.5 bits, until the 4th.After 4th bit comparison terminates, dynamically than
Relatively device 106,107 will be off until the next quantization cycle, and the 4th foundation terminates, and dynamic comparer 105 is opened, and completes it
The comparison of latter six, until the tenth.Dynamic comparer 105,106,107 quantifies the data that the logic circuit at SAR ADC
Module 109 produces through digital logical operation the binary code of ten, is stored in depositor, when next external sampling
The rising edge output of clock.
From foregoing teachings, front four 1.5 bits that Chun-Cheng Liu builds compare the 10MS/s of foundation,
The gradual approaching A/D converter main purpose of 10bit top plate sampling is to reduce upset probability, since reduce power consumption, and fast
Not raising speed on degree, the redundancy that can increase is the most extremely limited.And this technique being designed with is 0.18um CMOS work
Skill, unit capacitance values is 5fF.And along with technological development, the linearity of metal wire is more preferable, build under 65nm C MOS technique
Unit capacitance values is essentially 1fF, and this just illustrates that the total capacitance value of capacitor array of identical figure place is reduced to 1/5th, and level is built
Being greatly shortened between immediately, so using ten successive approximation comparators of four 1.5 bits, the consumption of hardware and delay are more
Greatly.This is designed with six seat digital to analog converters 108 and generates reference voltage, not only consumes certain area and power consumption, and
Easily the level on the capacitor array 102 of interference successive approximation comparator is set up, it is possible to introduce imbalance, at high frequencies
Affect bigger.This also limits the speed of the successive approximation comparator under this structure.
Summary of the invention
It is an object of the invention to propose a kind of novel 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate
The structure of gradual approaching A/D converter.Its feature is after first to introduce the technology that 1.5 redundancy bits accelerate,
MSB electric capacity sole plate level overturn after, capacitor array top plate level not yet completely set up when by top plate level
Intersect and input two controlled asymmetric dynamic comparators, compare, select the sole plate of this group electric capacity is connect ginseng according to result
Examine voltage high level, reference voltage low level or maintain common mode electrical level.1.5 redundancy bits that present invention introduces accelerate skill
Art, not only shortens former of wait and sets up the time completely, accelerate the switching rate of analog-digital converter, but also add
Redundancy, reduces error code, loses code, improve precision.
1.5 redundancy bits based on controlled asymmetric dynamic comparator that the present invention provides accelerate successive approximation modulus and turn
Parallel operation, its structure is as shown in Figure 2.Its circuit comprises: two identical boot-strapped switch 201, one group of symmetrical N position binary system
Capacitor array 202, two controlled asymmetric dynamic comparators 205,206, a common dynamic comparer 207 and SAR ADC's
Digital Logical Circuits module 208；Wherein:
Boot-strapped switch 201 is containing a signal input part, an input end of clock, an outfan；
The group electric capacity Han N in N position binary capacitor array 202, wherein N group capacitance and N-1 group capacitance are equal, are list
Position electric capacity, from N-1 group to first group, two times of geometric ratios of capacitance are incremented by；The top plate of each group of electric capacity be mutually coupled with node 203,
204, the sole plate of each group of electric capacity connects three groups of transmission gate switches 210,211；
Each transmission gate 210,211 comprises a n type field effect transistor and a p type field effect transistor, both raceway groove parallel
Cloth, both drain electrode ends are interconnected to constitute the drain electrode end of transmission gate circuit, and source terminal is interconnected to constitute transmission gate circuit
Source terminal, the gate terminal of n type field effect transistor constitutes the N gate terminal of transmission gate circuit, the gate terminal of p type field effect transistor
The P-gate constituting transmission gate circuit is extreme；
Each controlled asymmetric dynamic comparator 205,206 has a positive input terminal, a negative input end, a clock input
End, a positive output end and a negative output terminal；
Each common dynamic comparer 207 has the input of two not polarities, a clock control end, have two corresponding
Outfan；
The Digital Logical Circuits module 208 of SAR ADC comprises:
Clock generation module, according to the data miscarriage generating clock signal 222,223 of three comparators；
Digital Logic processing module, for producing the logic control signal of N position binary capacitor array 202 sole plate level upset
220,221 and register module storage output numeric data code；
In the present invention, the input of two boot-strapped switch signals connects differential signal input respectively, input end of clock all connect whole by
The external control clock of secondary approach type comparator, and sampling holding clock, the N position binary capacitor array that output termination is symmetrical
The top plate of 202 and node 203,204, sample phase by input signal collection on capacitor array top plate after switch off,
Magnitude of voltage is saved on the top plate of capacitor array；
In the present invention, in N position binary capacitor array 202, the top plate of each group of electric capacity is mutually coupled with boot-strapped switch 201, two
The input 207 of 205,206, common dynamic comparer of input of individual controlled asymmetric dynamic comparator and node 203,
204；The sole plate of each group of electric capacity connects three groups of transmission gate switches 210,211, the application of logic circuit module 208 of SAR ADC produce
Logic control connect reference voltage high level, reference voltage low level or common mode electrical level；So, each capacitor array top plate
The comparative result of level processes via the application of logic circuit module 208 of SAR ADC and produces electric capacity sole plate level upset control signal
220,221, control when the sole plate of the capacitance group of position connects reference voltage high level, reference voltage low level or common mode electrical level, with
Capacitor array top plate produces the comparative level of next bit；
In the present invention, the positive-negative input end intersection input N position binary system electricity of two controlled asymmetry dynamic comparers 205,206
Hold two top plate voltages of array 202, and intersection access node 203,204；Clock input connects the logic circuit mould of SAR ADC
The control signal 220,221 that block 208 produces, controls cut-offfing of controlled asymmetry dynamic comparer 205,206；Controlled asymmetric
Property comparator 205,206 utilize the load of latch in comparator asymmetric or non-right to pipe threshold of the input of comparator
Claiming, one adjustable reference voltage of superposition in the side input signal of comparator, such connection is equivalent to N position binary system electricity
Hold the differential voltage of 202 two top plate of array with adjustable reference voltage ratio relatively, produce the output code of 1.5 bits, it is achieved 1.5 ratios
Special redundancy is accelerated；The code of output is transferred to the application of logic circuit module 208 of SAR ADC, produce comparator control clock 222,
223, and electric capacity sole plate level upset control signal 220,221；
In the present invention, two top plate electricity of a common dynamic comparer 207 input termination N position binary capacitor array 202
Pressure, and access node 203,204；Clock input connects the control signal 220,221 that the application of logic circuit module 208 of SAR ADC produces,
Control cut-offfing of common dynamic comparer 207；Two top plate voltages of N position binary capacitor array 202 are compared in control,
Produce the output code of 1 bit；The code of output is transferred to the application of logic circuit module 208 of SAR ADC, produces the control clock of comparator
222,223, and electric capacity sole plate level upset control signal 220,221；
In the present invention, first is compared triggering next bit with the comparison of M to N position by common dynamic comparer 207 and sets up, and
Comparison at second to M position is compared triggering next bit by two controlled asymmetric dynamic comparators 205,206 and is set up；
In the present invention, the Digital Logical Circuits module 208 of SAR ADC is according to the data miscarriage generating clock signal of three comparators
The logic control signal 220,221 of 222,223, N position binary capacitor array 202 sole plate level upset and storage output number
According to code；
The present invention further provides 1.5 redundancy bits acceleration successive approximation moduluses based on controlled asymmetric dynamic comparator to turn
The workflow of parallel operation, specific as follows:
When CK is high level, and boot-strapped switch 201 is opened, input signal is sampled the binary capacitor battle array of analog-digital converter
On the top plate of row 202, now the sole plate often organizing capacitance group of capacitor array meets common mode electrical level Vcm, common dynamic comparer
207 and controlled asymmetric comparator 205,206 be turned off, analog-digital converter is in sample phase；
When CK is low level, and boot-strapped switch 201 turns off, and capacitor array 202 is unsettled, and the quantity of electric charge is constant, the trailing edge moment
Input signal is just held on capacitor array 202, and analog-digital converter is in quantization stage；
Common dynamic comparer 207 is under the control of the clock signal 222,223 of application of logic circuit module 208 generation of SAR ADC
Comparing the input signal kept, the data of dynamic comparer 207 are transferred in the application of logic circuit module 208 of SAR ADC,
Combined logic produces logic control signal 220,221, controls first capacitance group sole plate by three groups of transmission gate switches 210
Symmetrical reverses direction, reference voltage high level or reference voltage low level；Through the delay of one period of short time, the most primary
Level is set up and is not yet completed, and two controlled asymmetric dynamic comparators start the comparison of 1.5 bits, and symmetrical top plate level is handed over
Fork two controlled asymmetric dynamic comparators 205,206 of input, will node 203,204 intersect access two controlled asymmetric dynamic
The positive input terminal of state comparator 205,206 and negative input end, the clock signal that the application of logic circuit module 208 at SAR ADC produces
222, comparing setting up signal under the control of 223, two controlled asymmetric dynamic comparator 205,206 data are transferred to
In the application of logic circuit module 208 of SAR ADC, combined logic produces logic control signal 220,221, is opened by three groups of transmission gates
Close 210 controls the sole plate of second group of electric capacity connects reference voltage high level, reference voltage low level or maintains common mode electricity
Flat, repeat this step, until last position 1.5 bit-level；
After last position 1.5 bit-level compares end, controlled asymmetric dynamic comparator 205,206 will be off until next
In the quantization cycle, after this bit level is set up completely, common dynamic comparer 207 is opened, the comparison of figure place after completing, until N position；
Dynamic comparer 205,206,207 quantifies the data that in the application of logic circuit module 208 of SAR ADC through Digital Logic
Computing produces the binary code of N position, is stored in depositor, in the rising edge output of next external sampling clock.
Being used in the present invention realizes the controlled asymmetric dynamic comparator of 1.5 bits as shown in Figure 3.Controlled asymmetric dynamic
The method that state comparator realizes has two kinds, the slightly different configuration of the controlled asymmetric dynamic comparator of different implementation methods.
The first is that dynamic comparer latch load is controlled asymmetric, comprises and inputs pipe 301,302, is N-type transistor in figure 3
M1、M2；Tail current source capsule 303, is N-type transistor M3 in figure 3；Latch 304, two end to end phase inverters are constituted,
It is made up of P-type transistor M6, M7 and N-type transistor M4, M5 in figure 3；Reset transistor 305,306,307,308, in figure 3
It is P-type transistor M9, M10, M11, M12；Output buffer 309A, 309B, be by P-type transistor M14, M15 and N in figure 3
Transistor npn npn M12, M13 are constituted；The latch output node 310,311 of controlled asymmetric dynamic comparator；312A, 312B are
The latch output controlled capacitance array of controlled asymmetric dynamic comparator.Implementation is as follows: the latch of dynamic comparer
304 are connected to node 310,311 with capacitive load array 312A, 312B of belt switch, by controlling the logical of switch 331,332
Disconnected, structure gathers the load difference at latch 304 two ends, is produced the upset threshold of latch by the tripe systems of load
The difference of threshold voltage, equivalence to input, artificially produces not mating of input threshold value, produces at one end superposition in input signal
The effect of one reference voltage.And by the difference of regulation comparator latch 304 two ends load, can adjust and vary in size
Reference voltage effect.It is controlled asymmetric to pipe threshold voltage that the second implementation method is exactly dynamic comparer input, comprises defeated
Enter pipe 301,302, be N-type transistor M1, M2 in figure 3；Tail current source capsule 303, is N-type transistor M3 in figure 3；Latch
Device 304, two end to end phase inverters are constituted, and are made up of P-type transistor M6, M7 and N-type transistor M4, M5 in figure 3；Multiple
Bit transistor 305,306,307,308, is P-type transistor M9, M10, M11, M12 in figure 3；Output buffer 309A, 309B,
It is made up of P-type transistor M14, M15 and N-type transistor M12, M13 in figure 3；The lock of controlled asymmetric dynamic comparator
Storage output node 310,311；The input of controlled asymmetric dynamic comparator is external to the body terminal voltage 320,321 of pipe.Realize
Mode is as follows: input drawn the body end of pipe 301,302, external voltage, by changing metal-oxide-semiconductor source and the voltage difference of body end
The regulation input threshold voltage to pipe 301,302, produces the effect of one reference voltage of superposition at one end input signal.And
By regulation input to body terminal voltage difference, the effect of the reference voltage that varies in size can be adjusted.But there is any to need note
Meaning, utilizes second method to need input to be P-type transistor or deep trap N-type transistor to pipe.The method that the present invention provides
Though accurate reference voltage level can not be constructed, but can explain in detail afterwards, in 1.5 redundancy bits accelerating circuits, reference voltage
Value need not accurate especially, only need to meet in certain limit.This 1.5 ratios based on controlled asymmetric dynamic comparator
Special implementation method adds corresponding reference voltage or two two compared to two four input comparators needed for 1.5 traditional bits realizations
Input comparator adds redundant reference voltage generation circuit, it is possible to significantly simplifies circuit scale, particularly eliminates reference voltage
Produce circuit, then reduce power consumption and the area of analog-digital converter, it is possible to change sets up equivalence reference voltage level (if needed rapidly
Want), accelerate the conversion speed of analog-digital converter, and there is universality, can apply to the application scenarios of other 0.5 bits.
Foregoing teachings substantially describes inventive feature and technological merit, cited below particularly go out embodiment, in order to brighter
The thought of the present invention is described clearly.Any those of ordinary skill in the art are it will be understood that can be according to disclosed
Idea and specific embodiment are revised or design the framework realizing the identical purpose of the present invention, and this type of equal framework is without departing from this
Spirit and scope defined in bright appended claims.
Accompanying drawing explanation
Fig. 1 is the gradual approaching A/D converter of front four 1.5 bits that Chun-Cheng Liu delivered in 2010
Structural representation.
Fig. 2 provides 1.5 redundancy bits based on controlled asymmetric dynamic comparator to accelerate gradual approaching for the present invention
The structural representation of number converter.
The circuit diagram of the controlled asymmetric dynamic comparator that Fig. 3 provides for the present invention.
The example that Fig. 4 provides for the present invention, second is the gradual approaching A/D converter amount that 1.5 redundancy bits accelerate
Top plate Voltage Establishment schematic diagram during change.
The example that Fig. 5 provides for the present invention, second is the gradual approaching A/D converter that 1.5 redundancy bits accelerate
Digital calibration logic.
Label in figure:
101 is the two of the gradual approaching A/D converter of front four 1.5 bits that Chun-Cheng Liu delivered in 2010
Individual boot-strapped switch 101；102 is 10 binary capacitor array of this SAR ADC, the top plate of 103,104 capacitor arrays
Link together the node being connected with dynamic comparer；105,106,107 is three dynamic comparers of this SAR ADC, wherein
106,107 compare foundation for 1.5 bits；108 is the six seat digital to analog converters of this SAR ADC, is turned over by electric capacity sole plate
Raw every grade of 1.5 bits of changing the line of production compare the reference voltage of foundation；108 is the application of logic circuit module of this SAR ADC.
201 is that 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate gradual approaching A/D converter
Two identical boot-strapped switch；202 is the N position binary capacitor array of this invention；203, the top plate of 204 capacitor arrays
Link together the node being connected with dynamic comparer；205,206 is two controlled asymmetric dynamic comparators of this invention；
207 is a common dynamic comparer of this invention；208 is the Digital Logical Circuits module of the SAR ADC of this invention；210、
211 is the sole plate transmission gate switch of the N position binary capacitor of this invention；220,221 is that the numeral of SAR ADC of this invention is patrolled
Collect the logic control signal that circuit module produces；What 222, the Digital Logical Circuits module of the SAR ADC of 223 these inventions produced is dynamic
State comparator clock signal.
301,302 be the input of the controlled asymmetric dynamic comparator that the present invention provides to pipe, be body terminal voltage in figure 3
Derivative deep trap N-type transistor M1, M2；303 is the tail current source capsule of controlled asymmetric dynamic comparator, N-type transistor M3；
304 is the latch of controlled asymmetric dynamic comparator；305,306,307,308 is the reset of controlled asymmetric dynamic comparator
Transistor, P-type transistor M9, M10, M11, M12；309A, 309B are the output buffers of controlled asymmetric dynamic comparator；
310,311 is the latch output node of controlled asymmetric dynamic comparator；312A, 312B are controlled asymmetric dynamic comparators
Latch output controlled capacitance array；320,321 is the input of the controlled asymmetric dynamic comparator body terminal voltage to pipe.
401 is the top plate Voltage Establishment schematic diagram of the gradual approaching A/D converter of tradition top plate sampling, wherein
410 is the redundancy of first foundation of the gradual approaching A/D converter of tradition top plate sampling；402 is that the present invention provides
Example, second be 1.5 redundancy bits accelerate gradual approaching A/D converter quantizing process in top plate Voltage Establishment
Schematic diagram, wherein 411 be second be the superfluous of first of gradual approaching A/D converter foundation accelerating of 1.5 redundancy bits
Remaining, 412 be second be 1.5 redundancy bits accelerate gradual approaching A/D converter second set up redundancy；
403 is the example that the present invention provides, and second is the Dynamic comparison of the gradual approaching A/D converter that 1.5 redundancy bits accelerate
Device group, 413 is controlled asymmetric dynamic comparator, and 414 is common dynamic comparer；404 is the example that the present invention provides, second
Position is the control clock of the dynamic comparer group of the gradual approaching A/D converter that 1.5 redundancy bits accelerate, and wherein 415 is control
Making the clock of two controlled asymmetric dynamic comparators, 416 is the clock controlling dynamic comparer.
501 is the example that the present invention provides, and second is in the gradual approaching A/D converter that 1.5 redundancy bits accelerate
The data of single-stage one bit；502 be second be 1.5 redundancy bits accelerate gradual approaching A/D converter in 1.5 bits
The data of every grade；503 be second be the output data of gradual approaching A/D converter that 1.5 redundancy bits accelerate.
Detailed description of the invention
The bearing calibration provided the present invention below in conjunction with the accompanying drawings is described in detail.It should be noted that the present invention carries
The gradual approaching A/D converter that 1.5 redundancy bits of confession accelerate has different indexs and performance implementation method, in the present invention
1.5 bits based on controlled asymmetric dynamic comparator realize there is plurality of application scenes.Examples below is the present invention
There is provided a typical case to realize circuit, only in order to formation and the use of the present invention to be described, be not limited to the present invention.
1.5 redundancy bits based on controlled asymmetric dynamic comparator that the present invention provides accelerate primary and secondary approach type modulus and turn
Parallel operation example, implementation goal is the 150MS/s sample rate realizing the acceleration top plate sampling of a second 1.5 redundancy bits, 10
The gradual approaching A/D converter of position precision, concrete structure figure is as shown in Figure 2.Described structure includes comprising two identical grid
Pressure bootstrapped switch 201, one group of 10 symmetrical binary capacitor array 202, two controlled asymmetric dynamic comparators 205,
206, the Digital Logical Circuits module 208 of a common dynamic comparer 207 and SAR ADC；Wherein:
Two boot-strapped switch signal inputs connect differential signal input respectively, and input end of clock all connects whole successive approximation ratio
The external control clock of relatively device, and sampling holding clock, the climax of 10 binary capacitor array 202 that output termination is symmetrical
Plate, the input of two controlled asymmetric dynamic comparators 205,206, the input of a common dynamic comparer 207 and joint
Point 203,204, sample phase by input signal collection on capacitor array top plate after switch off, magnitude of voltage is saved in electric capacity
On the top plate of array；The sole plate of each group of electric capacity of 10 binary capacitor array 202 connect three groups of transmission gate switches 210,
211, the application of logic circuit module 208 of SAR ADC the logic control 220,221 produced connects reference voltage high level, reference voltage
Low level or common mode electrical level；The positive-negative input end intersection input N position two of two controlled asymmetry dynamic comparers 205,206 is entered
Two top plate voltages of capacitor array 202 processed, and intersection access node 203,204；Clock input connects the logic electricity of SAR ADC
The control signal 222,223 that road module 208 produces, controls cut-offfing of controlled asymmetry dynamic comparer 205,206；Controlled non-
Symmetry comparator 205,206 utilizes the load of latch in comparator asymmetric or the input of comparator is to pipe threshold
Asymmetric, one adjustable reference voltage of superposition in the side input signal of comparator, such connection is equivalent to 10 two
The differential voltage of 202 two top plate of system capacitor array with adjustable reference voltage ratio relatively, produces the output code of 1.5 bits, real
Existing 1.5 redundancy bits accelerate；The code of output is transferred to the application of logic circuit module 208 of SAR ADC, produces the control clock of comparator
222,223, and electric capacity sole plate level upset control signal 220,221.First comparison with the three to ten in this example
Compared triggering next bit by common dynamic comparer 207 to set up, and compare by two controlled asymmetric dynamic deputy
Comparator 205,206 compares triggering next bit and sets up；
The work schedule of the dynamic comparer of this example as shown in Fig. 4 415,416, in conjunction with sequential chart its work process done as
Lower explanation:
(1) above-mentioned second 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerates successive approximation analog digital conversion
Device is when CK is high, and CK is high level, and boot-strapped switch 201 is opened, and input signal samples the two of analog-digital converter and enters
On the top plate of capacitor array 202 processed, now the sole plate often organizing capacitance group of capacitor array meets common mode electrical level Vcm, the most dynamically
Comparator 207 and controlled asymmetric comparator 205,206 are turned off, and analog-digital converter is in sample phase；
(2) being low level as CK, boot-strapped switch 201 turns off, and capacitor array 202 is unsettled, and the quantity of electric charge is constant, the trailing edge moment
Input signal be just held on capacitor array 202, analog-digital converter is in quantization stage.Common dynamic comparer 207 exists
Under the clock signal 222,223 that the application of logic circuit module 208 of SAR ADC produces controls, and during signal 416 high level, to holding
Input signal compare, the data of dynamic comparer 207 are transferred in the application of logic circuit module 208 of SAR ADC, combined
Logic produces logic control signal 220,221, is controlled the symmetry of first capacitance group sole plate by three groups of transmission gate switches 210
Reverses direction, reference voltage high level or reference voltage low level；
(3) through the delay of one period of short time, the most primary level is set up and is not yet completed, and two controlled asymmetric dynamic compare
Device starts the comparison of deputy 1.5 bits, symmetrical top plate level cross two controlled asymmetric dynamic comparators of input
205,206, node 203,204 intersection will access the positive input terminal of two controlled asymmetric dynamic comparators 205,206 and bear
Input, under the control of the clock signal 222,223 of application of logic circuit module 208 generation of SAR ADC, and the high electricity of signal 415
At ordinary times, comparing setting up signal, two controlled asymmetric dynamic comparator 205,206 data are transferred to patrolling of SAR ADC
Collecting in circuit module 208, combined logic produces logic control signal 220,221, and being controlled by three groups of transmission gate switches 210 will
The sole plate of second group of electric capacity connects reference voltage high level, reference voltage low level or maintains common mode electrical level, controlled non-right
Dynamic comparer 205,206 is claimed to will be off until the next quantization cycle；
(4) through time delay after a while, after second level is set up completely, during signal 416 high level, common dynamic comparer
207 open, and compare setting up signal, and the data of dynamic comparer 207 are transferred to the application of logic circuit module 208 of SAR ADC
In, combined logic produces logic control signal 220,221, is controlled at the bottom of first capacitance group by three groups of transmission gate switches 210
The symmetrical reverses direction of pole plate, reference voltage high level or reference voltage low level；
(5) dynamic comparer 205,206 quantify data B2H and B2L, 207 quantify data B1, and B3 ~ B10 is at SAR ADC
Application of logic circuit module 208 according to the logical calculation method computing in Fig. 5, produce the binary code of 10, be stored in and deposit
In device, in the rising edge output of next external sampling clock.
Although present disclosure and advantage disclose as above in detail, but should be noted that, the scope of the present invention is also
It is not only restricted to the specific embodiments such as method described in this description and step, without departing from the spirit and scope of the present invention,
Any those of ordinary skill in the art all can make many deformation and amendment according to disclosed content, and these also should regard
For protection scope of the present invention.
Claims (7)
1. 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate a gradual approaching A/D converter, and it is special
Levying and be, its circuit comprises: two identical boot-strapped switch (201), one group of symmetrical N position binary capacitor array
(202), two controlled asymmetric dynamic comparators (205,206), a common dynamic comparer (207) and the number of SAR ADC
Word application of logic circuit module (208)；Wherein:
Boot-strapped switch (201) contains a signal input part, an input end of clock, an outfan；
The group electric capacity Han N in N position binary capacitor array (202), wherein, N group capacitance and N-1 group capacitance are equal, all
For unit electric capacity, from N-1 group to first group, two times of geometric ratios of capacitance are incremented by；The top plate of each group of electric capacity is mutually coupled with two
Node (203,204), the sole plate of each group of electric capacity connects three groups of transmission gate switches (210,211)；
Each transmission gate switch (210,211) comprises a n type field effect transistor and a p type field effect transistor, both raceway grooves
Parallel arrangement, both drain electrode ends are interconnected to constitute the drain electrode end of transmission gate circuit, and source terminal is interconnected to constitute transmission gate
The source terminal of circuit, the gate terminal of n type field effect transistor constitutes the N gate terminal of transmission gate circuit, p type field effect transistor
The P-gate that gate terminal constitutes transmission gate circuit is extreme；
Each controlled asymmetric dynamic comparator (205,206) has a positive input terminal, a negative input end, a clock input
End, a positive output end and a negative output terminal；
Each common dynamic comparer (207) has the input of two not polarities, a clock control end, have two corresponding
Outfan；
The Digital Logical Circuits module (208) of SAR ADC comprises:
Clock generation module, according to data miscarriage generating clock signal (222,223) of three comparators；
Digital Logic processing module, is used for producing the logic control letter of N position binary capacitor array (202) sole plate level upset
Number (220,221) and register module storage output numeric data code.
2. 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate successive approximation ratio
Relatively device, it is characterised in that two boot-strapped switch signal inputs connect differential signal input respectively, and input end of clock all connects whole
The external control clock of successive approximation comparator, and sampling holding clock, the N position binary capacitor array that output termination is symmetrical
(202) top plate and two nodes (203,204), sample phase by input signal collection on capacitor array top plate after open
Closing and disconnect, magnitude of voltage is saved on the top plate of capacitor array.
3. 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate successive approximation ratio
Relatively device, it is characterised in that in N position binary capacitor array (202), the top plate of each group of electric capacity is mutually coupled with boot-strapped switch
(201), the input (205,206) of two controlled asymmetric dynamic comparators, the input of a common dynamic comparer
And node (203,204) (207)；The sole plate of each group of electric capacity connects three groups of transmission gate switches (210,211), by SAR ADC's
The logic control that application of logic circuit module (208) produces connects reference voltage high level, reference voltage low level or common mode electrical level；This
Sample, the comparative result of each capacitor array top plate level processes via the application of logic circuit module (208) of SAR ADC and produces electricity
Hold sole plate level upset control signal (220,221), control when the sole plate of the capacitance group of position connects reference voltage high level, ginseng
Examine voltage low level or common mode electrical level, to produce the comparative level of next bit on capacitor array top plate.
4. 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate successive approximation ratio
Relatively device, it is characterised in that the positive-negative input end intersection input N position two of two controlled asymmetry dynamic comparers (205,206)
Two top plate voltages of system capacitor array (202), and intersection two nodes (203,204) of access；Clock input meets SAR
The control signal (220,221) that the application of logic circuit module (208) of ADC produces, control controlled asymmetry dynamic comparer (205,
206) cut-off；Controlled asymmetry comparator (205,206) utilizes the load of latch in comparator asymmetric or ratio
Compared with asymmetric to pipe threshold of input of device, one adjustable reference voltage of superposition in the side input signal of comparator, so
Connection be equivalent to by the differential voltage of (202) two top plate of N position binary capacitor array and adjustable reference voltage ratio relatively, produce
The output code of raw 1.5 bits, it is achieved 1.5 redundancy bits accelerate；The code of output is transferred to the application of logic circuit module of SAR ADC
(208), the control clock (222,223) of comparator, and electric capacity sole plate level upset control signal (220,221) are produced.
5. 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate successive approximation ratio
Relatively device, it is characterised in that two tops of a common dynamic comparer (207) input termination N position binary capacitor array (202)
Polar plate voltage, and access two nodes (203,204)；Clock input connects the control that the application of logic circuit module (208) of SAR ADC produces
Signal processed (220,221), controls cut-offfing of common dynamic comparer (207)；To N position binary capacitor array (202) two
Top plate voltage compares in control, produces the output code of 1 bit；The code of output is transferred to the application of logic circuit module of SAR ADC
(208), the control clock (222,223) of comparator, and electric capacity sole plate level upset control signal (220,221) are produced.
6. 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate successive approximation ratio
Relatively device, it is characterised in that first is compared triggering next bit with the comparison of M to N position by common dynamic comparer (207) and build
Vertical, and compared by two controlled asymmetric dynamic comparators (205,206) in the comparison of second to M position and trigger next bit and build
Vertical.
7. 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate successive approximation ratio
Relatively device, it is characterised in that its workflow is as follows:
When CK is high level, boot-strapped switch (201) is opened, and input signal samples the binary capacitor of analog-digital converter
On the top plate of array (202), now the sole plate often organizing capacitance group of capacitor array meets common mode electrical level Vcm, common Dynamic comparison
Device (207) and two controlled asymmetric comparators (205,206) are turned off, and analog-digital converter is in sample phase；
When CK is low level, boot-strapped switch (201) turns off, and binary capacitor array (202) is unsettled, and the quantity of electric charge is constant, under
Dropping the input signal along the moment to be just held on capacitor array (202), analog-digital converter is in quantization stage；
Two clock signals that common dynamic comparer (207) produces in the application of logic circuit module (208) of SAR ADC (222,
223) comparing, under control, the input signal kept, the data of common dynamic comparer (207) are transferred to SAR ADC's
In application of logic circuit module (208), combined logic produces two logic control signals (220,221), is opened by three groups of transmission gates
Close (210) and control the symmetrical reverses direction of first capacitance group sole plate, reference voltage high level or reference voltage low level；Warp
The delay of one period of short time, the most primary level sets up and not yet completes, two controlled asymmetric dynamic comparators (205,
206) start the comparison of 1.5 bits, symmetrical top plate level cross input two controlled asymmetric dynamic comparators (205,
206), two nodes (203,204) will intersect and access the positive input terminal of two controlled asymmetric dynamic comparators (205,206)
And negative input end, right under the control of two clock signals (222,223) produced in the application of logic circuit module (208) of SAR ADC
Setting up signal to compare, two controlled asymmetric dynamic comparator (205,206) data are transferred to the logic circuit of SAR ADC
In module (208), combined logic produces two logic control signals (220,221), is controlled by three groups of transmission gate switches (210)
The sole plate of second group of electric capacity is connect reference voltage high level, reference voltage low level or maintains common mode electrical level by system, repeats
This step, until last position 1.5 bit-level；
After last position 1.5 bit-level compares end, two controlled asymmetric dynamic comparators (205,206) will be off, directly
To the next quantization cycle；After this bit level is set up completely, common dynamic comparer (207) is opened, the ratio of figure place after completing
Relatively, until N position；
The data that two controlled asymmetric dynamic comparators (205,206), common dynamic comparers (207) quantify are at SAR
In the application of logic circuit module (208) of ADC through digital logical operation produce N position binary code, be stored in depositor, under
The rising edge output of one external sampling clock.
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| CN111865319A (en) * | 2020-07-28 | 2020-10-30 | 西安电子科技大学 | Ultra-low power consumption successive approximation type analog-to-digital converter based on four-input comparator |
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