CN105957897A - Manufacturing method for groove grid super junction MOSFET - Google Patents
Manufacturing method for groove grid super junction MOSFET Download PDFInfo
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- CN105957897A CN105957897A CN201610484791.9A CN201610484791A CN105957897A CN 105957897 A CN105957897 A CN 105957897A CN 201610484791 A CN201610484791 A CN 201610484791A CN 105957897 A CN105957897 A CN 105957897A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 12
- 238000001259 photo etching Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 108
- 238000000034 method Methods 0.000 claims description 33
- 238000000407 epitaxy Methods 0.000 claims description 30
- 239000011241 protective layer Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 230000001939 inductive effect Effects 0.000 abstract description 3
- 238000009825 accumulation Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000002146 bilateral effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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Abstract
The invention discloses a manufacturing method for a groove grid super junction MOSFET. The manufacturing method comprises the steps of forming a hard mask layer; photoetching the hard mask layer to open a groove forming area; etching for the first time to form a top groove; removing a protection layer at the bottom of the top groove, and reserving the protection layer on the side surface of the top groove; etching for the second time to form a bottom groove; filling the bottom groove with a P-type epitaxial layer to form a bottom epitaxial filled layer; filling the top of the bottom epitaxial filled layer with a P-type epitaxial layer to form a top epitaxial filled layer; removing the hard mask layer and the protection layer and thus forming a grid groove at the periphery of the top of a P-shaped column; and forming a grid dielectric layer in the grid groove and filling a grid conductive material in the grid groove. According to the manufacturing method, the registration deviation between the groove grid and the P-type column can be avoided, the technological stability can be improved and thereby the threshold voltage and breakover voltage drop of the device are more uniform, the size of the super junction unit can be smaller, and the capability of resisting unclamped inductive switching impact can be greatly enhanced.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, particularly relate to a kind of groove grid super node (super
Junction) manufacture method of power device.
Background technology
Super-junction structure is exactly alternately arranged N-type post and p-type post composition structure.If replaced vertically with super-junction structure
Bilateral diffusion MOS transistor (Vertical Double-diffused Metal-Oxide-Semiconductor, VDMOS)
N-type drift region in device, provides conduction path by N-type post in the on-state, and during conducting, p-type post does not provides
Conduction path；Jointly born reversed bias voltage by PN column in the off state, be the formation of superjunction metal-oxide half
Conductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor,
MOSFET).Super node MOSFET can be in the case of breakdown reverse voltage be consistent with traditional VDMOS device, by making
With the epitaxial layer of low-resistivity, and the conducting resistance of device is made to be greatly reduced.
As it is shown in figure 1, the structural representation of existing planar gate super junction power device；Here with N-type groove grid super node
Being introduced as a example by MOSFET, as shown in Figure 1, N-type groove grid super node MOSFET includes:
Semiconductor substrate such as silicon substrate 1, is formed with N-type epitaxy layer such as N-type silicon epitaxy on the surface of Semiconductor substrate 1
Layer 2, p-type post 3 that super-junction structure is formed from N-type epitaxy layer 2 and by the N-type extension between each p-type post 3
The alternately arranged formation of N-type post 4 of layer 2 composition.
PXing Ti district 5a is formed at the top of each p-type post 3.
Polysilicon gate 6a is formed at the top of the selection area of PXing Ti district 5a and is separated with gate dielectric layer mutually such as
Gate oxide, the surface of the PXing Ti district 5a covered by polysilicon gate 6a is for forming raceway groove, so PXing Ti district 5a
As channel region.The grid structure being made up of polysilicon gate 6a and gate dielectric layer also extends into the N outside PXing Ti district 5a
Type post surface.
The source region 7 being made up of N+ district is formed at the surface of PXing Ti district 5a, the side of source region 7 and polysilicon gate 5a
Autoregistration.
Interlayer film 8 is formed at the front of Semiconductor substrate 1 and by the polysilicon gate 6a of device, source region 7 and PXing Ti district
5a etc. cover.Contact hole 9 contacts through interlayer film 8 with corresponding source region 7 or the polysilicon gate 6a of bottom.In source
The bottom of the contact hole 9 of district 7 correspondence be formed P+ doping contact implanted layer 10, contact implanted layer 10 bottom and
PXing Ti district 5a contacts.Source region 7 and PXing Ti district 5a is connected to by front metal layer 11 by the contact hole 9 at top
The source electrode of composition；Polysilicon gate 6a is connected to the grid being made up of front metal layer 11 by the contact hole 9 at top.
When groove grid super node MOSFET is MOSFET element, the Semiconductor substrate 1 highly doped by N-type forms drain region,
And the drain electrode being made up of metal layer on back is formed at the back side of Semiconductor substrate 1.
Understanding as shown in Figure 1, a p-type post 3 and adjacent p-type post 4 form a superjunction unit, a superjunction
Forming an i.e. primitive unit cell of super junction power device unit in unit, polysilicon gate 6a is formed at the top of N-type post 4 and is
Two adjacent superjunction units shareds；Owing to polysilicon gate 6a is planar structure, can take bigger area, this is also
The size that can make superjunction unit can be bigger.
It is known that use trench gate to replace planar gate in super junction power device, can effectively reduce P/N column dimension i.e.
The size of superjunction unit, this size refers to transverse width, and the reduction of P/N column dimension means can be with richer epitaxial layer
Realize charge balance, therefore conduction voltage drop can be reduced.As in figure 2 it is shown, be existing groove grid super node MOSFET
Structural representation；In place of the difference of structure shown in Fig. 2 and Fig. 1 it is:
PXing Ti district 5 can cover the surface of whole super-junction structure in the horizontal, and polysilicon gate 6 is formed in groove, many
Crystal silicon grid 6 can be through PXing Ti district 5 and from covering PXing Ti district 5, side, the p-type covered by polysilicon gate 6 side
The surface in body district 5 is used for forming raceway groove.The groove of polysilicon gate 6 requires to be positioned at the top of N-type post 4.
Although the trench gate structure shown in Fig. 2 can reduce the size of device, but no matter uses multilamellar in actual process
The mode that extension or extension are filled forms p-type post 3, because p-type post 3 and trench gate i.e. polysilicon gate 6 is twice light
Carving and formed, the register partial difference in technique can cause the situation of the accumulation area occurring that p-type post 3 affects trench gate；Trench gate
Accumulation area be i.e. positioned at PXing Ti district 5 bottom and by polysilicon gate 6 side cover N-type epitaxy layer 2, p-type post 3
And when there is register partial difference between trench gate, the lateral dimension of accumulation area can be affected, thus the unlatching of device can be made
Voltage and conduction voltage drop are deteriorated.
Summary of the invention
The technical problem to be solved is to provide the manufacture method of a kind of groove grid super node MOSFET, can prevent
Between trench gate and p-type post, register partial difference occurs, technology stability can be improved and make cut-in voltage and the conducting of device
Pressure drop evenly, can produce the groove grid super node MOSFET of less primitive unit cell size.
For solving above-mentioned technical problem, the manufacture method of the groove grid super node MOSFET that the present invention provides includes walking as follows
Rapid:
Step one, offer semi-conductive substrate, be formed with N-type epitaxy layer at described semiconductor substrate surface；Described
N-type epitaxy layer surface forms hard mask layers.
Step 2, employing photoetching process define groove and form region；Described hard mask layers is performed etching groove
Formation region is opened.
Step 3, carrying out described N-type epitaxy layer etching for the first time, described first time etches with described hard mask layers
For mask, the degree of depth of etching of described first time reaches the degree of depth required by trench gate and forms top channel.
Lower surface and the side of described top channel are covered by step 4, formation protective layer.
Step 5, employing dry etching remove the described protective layer bottom described top channel, described top channel side
Described protective layer retain.
Step 6, described N-type epitaxy layer is carried out second time etch, described second time etch with described hard mask layers
Be mask with described protective layer, described second time etching after degree of depth super-junction structure to be reached p-type post required by deep
Spending and formed undercut, the width of described undercut is less than the width of described top channel.
Step 7, to carry out selective epitaxial for the first time under conditions of retaining described hard mask layers and described protective layer raw
Long technique is filled p-type epitaxial layer in described undercut and forms bottom extension packed layer.
Step 8, to carry out second time selective epitaxial under conditions of retaining described hard mask layers and described protective layer raw
Long technique is filled p-type epitaxial layer in the groove at the top of described bottom extension packed layer and forms top extension filling
Layer.
By being filled in described bottom extension packed layer and the extension packed layer superposition of described top forms p-type post, by each described
The N-type post of the described N-type epitaxy layer composition between p-type post, by described p-type post and alternately arranged group of described N-type post
Become super-junction structure.
Step 9, remove described hard mask layers and described protective layer, described protective layer at described p-type post after removing
Top all sides formed groove as gate trench.
Step 10, lower surface in described gate trench and side form gate dielectric layer；Afterwards, described
Gate trench is filled grid conducting material, this grid conducting material forms trench gate.
Further improving is that described Semiconductor substrate is silicon substrate, and described N-type epitaxy layer is N-type silicon epitaxy layer,
Described p-type epitaxial layer is p-type epitaxial layer.
Further improving is that described hard mask layers is made up of silicon nitride or is made up of silicon oxide superposition silicon nitride.
Further improving is that the material of described protective layer is silicon oxide.
Further improving is that grid conducting material described in step 10 is polysilicon.
Further improving is that the described gate dielectric layer in step 10 is gate oxide.
Further improving is to further comprise the steps of: after step 10
Step 11, form PXing Ti district at the top of described super-junction structure, through described p-type bottom described trench gate
Body district, the described p-type body surface covered by the described trench gate side being positioned at described N-type column top is for forming ditch
Road.
Step 12, described PXing Ti district surface formed source region.
Step 13, formation interlayer film, contact hole and front metal layer.
Described front metal layer is patterned formation source electrode and grid, described source region and described PXing Ti district by right
The contact hole answered is connected to described source electrode, and described trench gate is connected to grid by corresponding contact hole.
Further improving is, in step 13, to be all formed at the top of each described N-type post and each described p-type post
One contact hole being connected to source electrode.
The inventive method uses groove and the gate trench simultaneously defining super-junction structure with photoetching process, wherein,
The groove of super-junction structure is used for filling formation p-type post, and gate trench is used for forming trench gate；During etching groove
Etch at twice, etch into the degree of depth of gate trench for the first time, the groove side surface after etching for the first time is formed protect afterwards
Sheath, proceeds second time afterwards and etches；After being formed due to protective layer, the mask window of second time etching can diminish,
Therefore the width of the undercut formed is less than the width of top channel；And to whole groove under conditions of reservation protection layer
Carry out extension to fill and formed after p-type post, autoregistration can form grid at the top of p-type post by removing protective layer
Groove.It follows that the groove of the super-junction structure of the present invention and gate trench can use and once be lithographically formed, p-type
Post and gate trench autoregistration, so register partial difference problem when this invention removes the definition of Twi-lithography technique, namely
The present invention can prevent register partial difference occur between trench gate and p-type post, it is thus possible to improve technology stability and make device
Cut-in voltage and conduction voltage drop evenly, owing to there is no register partial difference so that it is less that superjunction unit can make,
The groove grid super node MOSFET making making little primitive unit cell size is possibly realized.
It addition, the top autoregistration of gate trench of the present invention and p-type post, gate trench is filled grid conducting material
After forming trench gate, the p-type body surface only covered by the trench gate side being positioned at N-type column top can form ditch
Road, same N-type column top has two separate trench gate sides that can be used in forming raceway groove, this split
Structure makes the top of N-type post and p-type post can form extraction source region and the contact hole in PXing Ti district, this contact hole
Structure can increase substantially device anti-undamped inductive switching (Unclamped Inductive Switching,
UIS) impact capacity, anti-UIS impact capacity is device ability of load energy under avalanche breakdown；Reason is: nothing
Generation when puncturing of opinion device, between the PN junction that p-type post and N-type epitaxy layer are formed, is also to occur at PXing Ti district
And between the PN junction of N-type epitaxy layer formation, the electric current puncturing formation can flow away from contact hole uniformly, thus greatly
Amplitude improves the anti-UIS impact capacity of device.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is the structural representation of existing planar gate super junction power device；
Fig. 2 is the structural representation of existing groove grid super node MOSFET；
Fig. 3 is the flow chart of the manufacture method of embodiment of the present invention groove grid super node MOSFET；
Fig. 4 A-Fig. 4 M is the device architecture in each step of manufacture method of embodiment of the present invention groove grid super node MOSFET
Schematic diagram.
Detailed description of the invention
As it is shown on figure 3, be the flow chart of the manufacture method of embodiment of the present invention groove grid super node MOSFET；Such as Fig. 4 A
To shown in Fig. 4 M, it is that the device architecture in each step of manufacture method of embodiment of the present invention groove grid super node MOSFET shows
Being intended to, the manufacture method of embodiment of the present invention groove grid super node MOSFET comprises the steps:
Step one, as shown in Figure 4 A, it is provided that semi-conductive substrate 101, is formed on described Semiconductor substrate 101 surface
There is N-type epitaxy layer 102.
As shown in Figure 4 B, hard mask layers 201 is formed on described N-type epitaxy layer 102 surface.
Preferably, described Semiconductor substrate 101 is silicon substrate, and described N-type epitaxy layer 102 is N-type silicon epitaxy layer,
The p-type epitaxial layer of follow-up filling groove is p-type epitaxial layer.
Described hard mask layers 201 is made up of silicon nitride or is made up of silicon oxide superposition silicon nitride.
Step 2, as shown in Figure 4 B, uses photoetching process to form photoetching offset plate figure 202 and defines groove and form region；
Described hard mask layers 201 is performed etching and groove is formed region opens.
Step 3, as shown in Figure 4 C, carries out described N-type epitaxy layer 102 etching for the first time, and described first time carves
Losing with described hard mask layers 201 as mask, it is deep that the degree of depth of etching of described first time reaches required by trench gate 105
Spend and form top channel 203a.
Step 4, as shown in Figure 4 D, forms protective layer 204 by the lower surface of described top channel 203a and side
Cover.Preferably, the material of described protective layer 204 is silicon oxide.
Step 5, as shown in Figure 4 E, uses dry etching to remove the described protective layer bottom described top channel 203a
204, the described protective layer 204 of described top channel 203a side retains.
Step 6, as illustrated in figure 4f, carries out second time and etches described N-type epitaxy layer 102, and described second time is carved
Losing with described hard mask layers 201 and described protective layer 204 as mask, the degree of depth after described second time etching to reach
The degree of depth required by p-type post 103 of super-junction structure also forms undercut 203b, the width of described undercut 203b
Degree is less than the width of described top channel 203a.
Step 7, as shown in Figure 4 G, under conditions of retaining described hard mask layers 201 and described protective layer 204
Carry out selective epitaxial growth process for the first time in described undercut 203b, fill p-type epitaxial layer and form bottom
Extension packed layer 103a.
Step 8, as shown at figure 4h, under conditions of retaining described hard mask layers 201 and described protective layer 204
Carry out second time selective epitaxial growth process in the groove at the top of described bottom extension packed layer 103a, fill P
Type epitaxial layer also forms top extension packed layer 103b.
By being filled in described bottom extension packed layer 103a and the extension packed layer 103b superposition of described top forms p-type post
103, the N-type post being made up of the described N-type epitaxy layer 102 between each described p-type post 103, by described p-type post
103 and described N-type post alternately arranged composition super-junction structure.
As shown in fig. 41, carry out extension planarization and return quarter, described p-type post 103 after planarizing and return carving technology
Top surface equal with the top surface of described N-type epitaxy layer 102.
Step 9, as shown in fig. 4j, removes described hard mask layers 201 and described protective layer 204, by described protection
The groove that layer 204 is formed in all sides at the top of described p-type post 103 after removing is as gate trench 205.
Step 10, as shown in Figure 4 K, lower surface and side in described gate trench 205 form gate dielectric layer
104；Afterwards, described gate trench 205 is filled grid conducting material, is made up of this grid conducting material
Trench gate 105.
Preferably, described grid conducting material is polysilicon.Described gate dielectric layer 104 is gate oxide.
Further comprise the steps of:
Step 11, as illustrated in fig. 4l, forms PXing Ti district 106, described trench gate at the top of described super-junction structure
Through described PXing Ti district 106 bottom 105, covered by described trench gate 105 side being positioned at described N-type column top
Surface, described PXing Ti district 106 be used for forming raceway groove.Shown in Fig. 4 L, the top of each N-type post will
Have the side of two described trench gate 105 for forming raceway groove.
Step 12, as illustrated in fig. 4l, forms source region 107 on the surface in described PXing Ti district 106.
Step 13, as shown in fig. 4m, forms interlayer film 108, contact hole 109 and front metal layer 111.
Described front metal layer 111 is patterned formation source electrode and grid, described source region 107 and described p-type body
District 106 is connected to described source electrode by corresponding contact hole 109, and described trench gate 105 is by corresponding contact hole 109
It is connected to grid.
The contact injection region 110 of P+ doping it is also formed with in the bottom of the contact hole 109 corresponding to described source region 107.
Shown in Fig. 4 M, all it is formed with a company at the top of each described N-type post and each described p-type post 103
Receive the contact hole 109 of source electrode.The structure of this contact hole can increase substantially the anti-UIS impact capacity of device,
Reason is: no matter device occur when puncturing between the PN junction that p-type post 103 and N-type epitaxy layer 102 are formed,
Also being to occur between the PN junction of PXing Ti district 106 and N-type epitaxy layer 102 formation, the electric current puncturing formation can
Flow away from contact hole uniformly, thus increase substantially the UIS ability of device.
Afterwards, following back process step is also included:
Described Semiconductor substrate 1 is carried out thinning back side.
Carry out the first conduction type heavy doping ion at the described Semiconductor substrate back side and inject formation drain region, described drain region.
Form metal layer on back, this metal layer on back draw drain electrode.
Above by specific embodiment, the present invention is described in detail, but these have not constituted the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improves, this
Also should be regarded as protection scope of the present invention a bit.
Claims (8)
1. the manufacture method of a groove grid super node MOSFET, it is characterised in that comprise the steps:
Step one, offer semi-conductive substrate, be formed with N-type epitaxy layer at described semiconductor substrate surface；Described
N-type epitaxy layer surface forms hard mask layers；
Step 2, employing photoetching process define groove and form region；Described hard mask layers is performed etching groove
Formation region is opened；
Step 3, carrying out described N-type epitaxy layer etching for the first time, described first time etches with described hard mask layers
For mask, the degree of depth of etching of described first time reaches the degree of depth required by trench gate and forms top channel；
Lower surface and the side of described top channel are covered by step 4, formation protective layer；
Step 5, employing dry etching remove the described protective layer bottom described top channel, described top channel side
Described protective layer retain；
Step 6, described N-type epitaxy layer is carried out second time etch, described second time etch with described hard mask layers
Be mask with described protective layer, described second time etching after degree of depth super-junction structure to be reached p-type post required by deep
Spending and formed undercut, the width of described undercut is less than the width of described top channel；
Step 7, to carry out selective epitaxial for the first time under conditions of retaining described hard mask layers and described protective layer raw
Long technique is filled p-type epitaxial layer in described undercut and forms bottom extension packed layer；
Step 8, to carry out second time selective epitaxial under conditions of retaining described hard mask layers and described protective layer raw
Long technique is filled p-type epitaxial layer in the groove at the top of described bottom extension packed layer and forms top extension filling
Layer；
By being filled in described bottom extension packed layer and the extension packed layer superposition of described top forms p-type post, by each described
The N-type post of the described N-type epitaxy layer composition between p-type post, by described p-type post and alternately arranged group of described N-type post
Become super-junction structure；
Step 9, remove described hard mask layers and described protective layer, described protective layer at described p-type post after removing
Top all sides formed groove as gate trench；
Step 10, lower surface in described gate trench and side form gate dielectric layer；Afterwards, described
Gate trench is filled grid conducting material, this grid conducting material forms trench gate.
2. the manufacture method of groove grid super node MOSFET as claimed in claim 1, it is characterised in that: described partly lead
Body substrate is silicon substrate, and described N-type epitaxy layer is N-type silicon epitaxy layer, and described p-type epitaxial layer is p-type epitaxial layer.
3. the manufacture method of groove grid super node MOSFET as claimed in claim 2, it is characterised in that: described firmly
Matter mask layer is made up of silicon nitride or is made up of silicon oxide superposition silicon nitride.
4. the manufacture method of groove grid super node MOSFET as claimed in claim 2, it is characterised in that: described protection
The material of layer is silicon oxide.
5. the manufacture method of groove grid super node MOSFET as claimed in claim 1 or 2, it is characterised in that: step
Grid conducting material described in ten is polysilicon.
6. the manufacture method of groove grid super node MOSFET as claimed in claim 1 or 2, it is characterised in that: step
Described gate dielectric layer in ten is gate oxide.
7. the manufacture method of groove grid super node MOSFET as claimed in claim 1, it is characterised in that step 10 it
After further comprise the steps of:
Step 11, form PXing Ti district at the top of described super-junction structure, through described p-type bottom described trench gate
Body district, the described p-type body surface covered by the described trench gate side being positioned at described N-type column top is for forming ditch
Road；
Step 12, described PXing Ti district surface formed source region；
Step 13, formation interlayer film, contact hole and front metal layer；
Described front metal layer is patterned formation source electrode and grid, described source region and described PXing Ti district by right
The contact hole answered is connected to described source electrode, and described trench gate is connected to grid by corresponding contact hole.
8. the manufacture method of groove grid super node MOSFET as claimed in claim 7, it is characterised in that: step 13
In, all it is formed with a contact hole being connected to source electrode at the top of each described N-type post and each described p-type post.
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| CN107731733A (en) * | 2017-11-06 | 2018-02-23 | 上海华虹宏力半导体制造有限公司 | The fill method of groove extension |
| CN117174757A (en) * | 2023-11-02 | 2023-12-05 | 深圳芯能半导体技术有限公司 | Super-junction trench gate silicon carbide MOSFET and preparation method thereof |
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| KR20050089188A (en) * | 2004-03-04 | 2005-09-08 | 김선호 | Method of forming a isolation layer in a semiconductor device |
| CN101996868A (en) * | 2009-08-27 | 2011-03-30 | 上海华虹Nec电子有限公司 | Forming method of P-type and N-type semiconductor thin layers arranged in alternant mode |
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| US20050023634A1 (en) * | 2003-07-29 | 2005-02-03 | Yoon Byoung-Moon | Method of fabricating shallow trench isolation structure and microelectronic device having the structure |
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| CN117174757B (en) * | 2023-11-02 | 2024-03-26 | 深圳芯能半导体技术有限公司 | Super-junction trench gate silicon carbide MOSFET and preparation method thereof |
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