CN105895677B - A kind of backside structure of semiconductor devices - Google Patents
A kind of backside structure of semiconductor devices Download PDFInfo
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Abstract
The invention discloses a kind of backside structures of semiconductor devices, the back side of device includes following characteristics: at least there are three types of the regions of different levels of doping to be in contact with back metal for semiconductor back surface, the region of these three different levels of doping is: low doping concentration area, the area P+ and the area N+.Wherein the doping concentration range in low doping concentration area is 5 × 1014/cm3To 1 × 1018/cm3, the concentration range in the area P+ is 5 × 1018/cm3To 1 × 1020/cm3, the doping concentration range in the area N+ is 5 × 1018/cm3To 1 × 1020/cm3, contacted with semiconductor back surface as metal electrode.
Description
Technical field:
The present invention is to be related to a kind of structure of semiconductor devices, more particularly to a kind of semiconductor power device
The back side doped structure of silicon wafer.
Background technique:
1980, RCA Corp., the U.S. applied for first IGBT patent, and Toshiba Corp is made that first within 1985
Industrial IGBT.From device physically for, it is non-transparent collector punch IGBT, referred to as punch IGBT
(Punchthrough IGBT- is abbreviated as PT-IGBT).PT-IGBT is manufacture on epitaxial silicon chip, usually in P+On substrate
One layer of N-type buffer area is grown, then grows a N again-Area will manufacture the resistance to voltage device of 1200V, just need to grow a N-type buffer area, mix
Miscellaneous concentration is about 1 × 1017/cm3, thickness is about 10um, and then one epitaxy layer thickness of regrowth is about 110um, and doping concentration is about
It is 5 × 1013/cm3To 1 × 1014/cm3N-Area, this is relatively thicker epitaxial layer.To manufacture the higher PT-IGBT of pressure resistance,
If pressure resistance is 2500V or 3300V, then N-Area needs thicker and higher resistivity.The extension for growing such specification, technically has
Difficulty, and cost can sharply increase, so, it is within the scope of 400V to 1200V that PT-IGBT, which is generally only applicable to pressure resistance,.
As previously mentioned, it is to be to manufacture pressure resistance within the scope of 400V to 1200V that PT-IGBT, which is generally only applicable to pressure resistance,
1700V or 2500V or 3300V or more, early stage, all with non-punch through IGBT, (Non-punchthrough IGBT, was abbreviated as
NPT-IGBT), device is fabricated directly in thickness and has in several hundred microns of FZ N-type silicon chip, the p type island region of device collector junction or p-type/N
Type area is formed by ion implanting.The voltage drop of this non-punch through IGBT is positive temperature coefficient.The structure of this collector junction
Also it is used for device such as MCT or GTO etc..Since the doping of collector junction is formed by ion implanting, the dosage of injection can be controlled arbitrarily,
If the P-type dopant amount of injection is high, general high hole injection efficiency collector junction (i.e. strong collector) will form;If injection
P-type dopant amount is small, then hole injection efficiency is low, and electronics can effectively flow through p type island region to metal via diffusion and contact
Place, this kind of collector junction are referred to as weak collector junction or transparent collector junction (or being transparent collector).During 94 and 95 years, weak collection
Electricity knot is once used for NPT-IGBT and GTO, if weak collector junction method is used to manufacture 600V or 1200V IGBT, the collection of IGBT
Electricity knot needs to make on the only FZ N-type silicon chip back side of about 60um or about 120um thickness, and during 94 and 95 years, industry is also not
There is this ultra thin silicon wafers technological ability.
In 1996, motorola inc delivered a research of the article description in relation to manufacturing non-break-through IGBT, stressed
The technique that collector how is manufactured in thin silicon wafer, there are about 170um thickness for FZ N-type silicon chip used most thin.Next year,
Infineon company has also delivered the NPT-IGBT that 600V is made with the FZ N-type silicon chip of 100um thickness.It is 99 years or so, industrial new
The IGBT of a generation starts to go into operation, and the IGBT of this new generation is a kind of high-speed switching devices, its voltage drop is positive temperature coefficient,
It does not need to shorten minority carrier life time in device with heavy metal or irradiation, and technology mainly is ultra thin silicon wafers technique plus weak collection
Electricity knot (or being transparent collector junction).Infineon company is referred to as field cut-off IGBT, the following years, each main production IGBT
Company all release one after another similar product.From that time, IGBT has obtained qualitative leap on electric property, quickly grows simultaneously
The market of medium power range is dominated.
The backside structure of such so-called field cut-off IGBT device mainly has a N-type buffer layer 10 and a collector junction P-type layer 11
As shown in Figure 1, the thickness of P-type layer is generally no greater than 1 micron, doping concentration range about 1 × 1017/cm3To 5 × 1018/cm3Range
Between, this P-type layer and back metal form weak collector, and when device is turned off from opening state, N-type carrier (i.e. electronics) can
It is collected with easily passing through P-type layer directly Bei Bei Mian collector, these N-type carriers remain in N-type base area and N-type buffer area
Time is very short, so not as, PT type IGBT leaves a long Current Tail when shutdown.
With the development of power device IGBT technology, the switching speed of IGBT is getting faster, and in application system, is had fast
The IGBT needs of speed switch are asked using fast recovery diode (FRD) as freewheeling diode.Switching device IGBT each time from
It opens into turn off process, freewheeling diode can become off state from state.And this is crossed range request diode and has
Fast and soft recovery characteristics.In application process, it is desirable to which the small power consumption of system, high reliablity and lesser electromagnetic noise, this is right
IGBT and FRD have high requirements, however, industry ignores the exploitation of fast diode in a very long time, because
The performance of FRD is not caught up with, and the efficiency for becoming limitation whole system can not also be brought into play, quickly although the performance of IGBT is fine
The effect of diode receives the attention of height.
Since two thousand, the technological development that IGBT is made of thin silicon blade technolgy is rapid, as thin silicon wafer IGBT makes
Maturation, naturally corresponding technology is also used to production FRD. and manufactures the technique of 400V to 1200V FRD with FZ n-type silicon chip,
It is broadly divided into two large divisions, i.e. preceding working procedure and later process.Preceding working procedure is mainly made the front structure of device in FZ n
On the surface of type silicon wafer.Just FZ silicon wafer wear down to required thickness after the completion of preceding working procedure, such as pressure resistance is 1200V, then required thick
Degree is about 120um or so.Subsequently into later process, needs overleaf to inject high concentration n-type dopant in later process and carry out shape
At N+ type area 13, this N+ type area and back metal composition electron emitter as shown in Fig. 2, general injection phosphorus or arsenic, if fruit is only infused
Enter primary, silicon chip back side will form a height and tie, this can make the soft factor be hardened, when shutdown can generate biggish electromagnetic noise or
Oscillation, this be it is unacceptable, general solution is overleaf to inject p-type impurity twice.
Early stage thin silicon blade technolgy mainly put forth effort on how wear down silicon wafer, how to handle grinding after back Mian, how to wear down
Technologic problem is done ion implanting and how to anneal etc. at the back side of silicon wafer afterwards, and the backside structure ratio of IGBT is ended in early stage field
It is relatively simple as shown in Figure 1.The FRD made of thin slice technique is then as shown in Fig. 2, these backside structures are all only a kind of doped regions
Such as 11 or 14 and back metal contacts.
In 2010 or so, attention started to turn to backside structure, the 5th generation IGBT and IR company, the U.S. such as Ying Feilun
Eighth generation IGBT, the FRD of the RC-IGBT and Fig. 4 of these new backside structures such as Fig. 3.
Such as the RC-IGBT in Fig. 3, in order to reduce conducting voltage, to reduce conducting power consumption, wherein the back side has suitable one
Part region is that continuously there was only P+ doping 12, is adulterated without N+, and the width in this region can be greater than 200um, can make RC- in this way
For turn-on characteristics when the conducting of IGBT is penetrated close to general IGBT, but when off, the electronics on this partial area cannot
By highly doped P+, it can only detour and flow to back metal through the area N+, this can make turn-off speed slack-off
The backside structure of FRD in Fig. 4 can be reduced reverse recovery charge, but will increase conduction voltage drop, with backside structure come
Limitation injection charge is not good method, furthermore, the turn-off characteristic of this structure can be very hard, can cause to vibrate, or even be made into FRD device
Part is impaired, this is upper unacceptable in application.
Silicon wafer after wear down do mask plate be aligned in technique and upper production on be all extremely difficult, so described before
More complicated backside structure is only directly contacted with back metal electrode there are two types of doped region, such as the RC-IGBT in Fig. 3,
There are P+ that doping concentration is high and high the two regions N+ and back metal contacts, the FRD of Fig. 4 of doping concentration there was only highly doped N+
Area and the low-doped area N and back metal contacts.The technique that region and metal contact there are two types of this is simpler, is readily produced,
Disadvantage is the failure to the electric property of optimised devices
Summary of the invention:
Field cut-off IGBT, RC-IGBT or the FRD that the above is said, the structure of back side part is very to the performance of device
Crucial, it is an object of the invention to propose a kind of to be avoided that a kind of above-mentioned insufficient and semiconductor power device silicon of practical
The backside structure of piece, the present invention are that at least there are three types of different doping are dense by the present invention from the most significantly different place of back structures before
The region of degree is in contact with back metal, and the region of these three different levels of doping is: (1) a low doping concentration area, (2) area P+
(3) area N+.The width in the area P+ and the area N+ is greater than 20um, and the width in the area wherein at least one P+ is greater than 200um.These areas
Relative position and concentration be can be through FZ silicon wafer doping concentration itself, mask plate structure, the dosage of ion implanting, energy,
Type and injection angles and annealing conditions etc. determine, repeat and can simply implement, and are suitable for production, this structure is available
End IGBT, RC-IGBT and FRD in field.
Implementing the present invention has following several different schemes for RC-IGBT:
Scheme (1): the present invention is for improveing RC-IGBT Bei Mian structure, Bei Mian structure and general anode in short circuit
IGBT is similar, is a difference in that at least there are three the regions of different levels of doping to be in contact with back metal as schemed in device back Mian
5 and Fig. 6, when closed, the P+ far from N+14 can be initially injected hole, and hole is also successively injected in other areas P+ successively later,
Conduction voltage drop is set to be in low value, when shutdown, electronics can pass through the area N+ and flow to rear electrode, can also be efficiently directly through metal
It with FZ silicon wafer area contact position, is collected by rear electrode, keeps the turn-off speed of device faster than the structure of Fig. 3 before.
Scheme (2): the structure of Fig. 5 and Fig. 6 might have punch through on cutoff device on the scene, this can pass through mask plate
Higher energy injection N-type impurity such as hydrogen atom is also used while injecting P+ and N+, so that there is the sufficiently high N-type region handle of a concentration
The area P+, which fences up, prevents punch-through the generation in reverse bias.Fig. 8 is exactly the schematic diagram of this structure.Fig. 9 is another way, is not needed
Mask plate injects N-type impurity such as hydrogen atom to silicon chip back side higher-energy blanket type.
Scheme (3): Figure 10 is similar with scheme (2), only adds in scheme (2) miscellaneous with a blanket type low energy injecting p-type
Matter such as boron atom, crossing structure can make lower before conduction voltage drop ratio, and when shutdown, electronics can pass through the area N+ or post low-doped thin
P type island region is collected with the weak collector that metal forms by back metal, and turn-off speed is unaffected.
Implementing the present invention has following several different schemes for FRD:
It is similar with scheme before, it is the region N+ and the region P+ to be mutually adjusted in place of main difference, is set from being newly afraid of
Such as Figure 11, so that more applicable FRD.For FRD, behind structure can most influence injected electrons number when conducting, electronics energy when shutdown
It is how fast taken away by rear electrode, the more then conduction voltage drop is lower for injection electronics when conducting, and when shutdown, electronics is pumped then fastlyer
The soft factor is smaller, i.e. shutdown can become very hard, will lead to circuit oscillation, or even is made into that FRD is impaired, in order to when increasing shutdown
The soft factor can overleaf place some P+ type areas with metal contact position, when off, can make one when electronic current flowing
Flowing of these areas P+ of part injection hole to make electronics flow to back metal slows down, and makes the soft factor of circuit when off
Increase.
Because of this scheme area Zhong You P+ and back metal contacts, the higher N of doping concentration is needed in cutoff device on the scene
Type area such as N-type buffer area come surround the area P+ 13 such as Figure 12 and Figure 13, make there is no break-through to happen in reverse bias.
In order to increase soft factor when shutdown, it is as shown in figure 14 can overleaf to inject one layer of thin P-type layer.Through tune
The doping concentration for rising thin P-type layer is not easy electronics across in this case, electronics can only flow to collector, electronics through the area N+
It is more slowly taken away by rear electrode, shutdown can become softer, and it is as shown in figure 15 further to reduce the area N+, to reduce electricity
The channel that subflow is walked then increases electronics and leaves time in semiconductor back, then shutdown can become softer.Further, also
It can make some p type island regions 16 only partially area Gai get N+ such as Figure 16,17 Hes through the incidence angle and energy of adjustment injection ion
Shown in 18, so that electronics can only penetrate injection by Ba from the side, when shutdown, is so easy to flow away through the area N+ not as good as before, thus shutdown because
Son is softer.
Some schemes described above are more suitable for IGBT, some are more suitable for FRD, the side of generally each backside structure
Case is used equally for semiconductor power device such as IGBT or RC-IGBT or FRD or MCT or GTO;Or power MOS pipe.
Detailed description of the invention
Attached drawing is used to provide further understanding of the present invention, and is used to explain the present invention together with embodiments of the present invention,
It is not construed as limiting the invention, in the accompanying drawings:
Fig. 1 is the cross-sectional structure schematic diagram of general field cut-off IGBT device;
Fig. 2 is the cross-sectional structure schematic diagram of the FRD generally manufactured with thin silicon blade technolgy;
Fig. 3 is the cross-sectional structure schematic diagram of the RC-IGBT there are two types of doped region and back metal contacts;
Fig. 4 is the cross-sectional structure schematic diagram of the FRD there are two types of doped region and back metal contacts;
Fig. 5 is the cross-sectional structure schematic diagram that the present invention passes through AA ' in Fig. 7;
Fig. 6 is the cross-sectional structure schematic diagram that the present invention passes through BB ' in Fig. 7;
Fig. 7 is the top view of sub-fraction in mask plate used in the present invention;
Fig. 8 is the cross-sectional structure schematic diagram for having the device more than two kinds of doped regions and back metal contacts;
Fig. 9 is the cross-sectional structure schematic diagram for having the device more than two kinds of doped regions and back metal contacts;
Figure 10 is the cross-sectional structure schematic diagram of the device there are three types of doped region and back metal contacts;
Figure 11 is the cross-sectional structure schematic diagram of the device there are three types of doped region and back metal contacts;
Figure 12 is the cross-sectional structure schematic diagram of the device there are three types of doped region and back metal contacts;
Figure 13 is the cross-sectional structure schematic diagram of the device there are three types of doped region and back metal contacts;
Figure 14 is the cross-sectional structure schematic diagram of the device there are three types of doped region and back metal contacts;
Figure 15 is the cross-sectional structure schematic diagram of the device for three kinds of doped regions that there is the less area N+ at the back side;
Figure 16 present invention has the cross-sectional structure schematic diagram for paying the device for adding p type island region 16 to be;
Figure 17 present invention has the cross-sectional structure schematic diagram for paying the device for adding p type island region 16 to be;
Figure 18 present invention has the cross-sectional structure schematic diagram for paying the device for adding p type island region 16 to be;
Figure 19 is the surface texture schematic diagram of the formation power device of the embodiment of the present invention 1;
Figure 20 be the embodiment of the present invention 1 completion grinding process after schematic diagram;
Figure 21, which is the back surface to silicon wafer 200 of the embodiment of the present invention 1, is greater than 7 degree of injection P31 dopings with implant angle
Ion schematic diagram;
Figure 22 is the back surface injecting p-type boron doping matter ion schematic diagram to silicon wafer of embodiment 1;
Figure 23 is the cross-sectional structure schematic diagram that the embodiment of the present invention 1 completes device after rear electrode 15;
Figure 24 is that the back surface to silicon wafer of embodiment 2 injects hydrogen doping agent schematic diagram;
Figure 25 is the cross-sectional structure schematic diagram that the embodiment of the present invention 2 completes device after rear electrode 15;
Figure 26 is the back surface to silicon wafer of embodiment 3 through the same mask plate injection hydrogen doping agent schematic diagram of back;
Figure 27 is the cross-sectional structure schematic diagram that the embodiment of the present invention 3 completes device after rear electrode 15;
Figure 28 is the back surface injecting p-type boron doping matter ion schematic diagram to silicon wafer of embodiment 4;
Figure 29 is the cross-sectional structure schematic diagram that the embodiment of the present invention 4 completes device after rear electrode 15;
Figure 30 is the surface texture schematic diagram of the formation power device of the embodiment of the present invention 5;
Figure 31 be the embodiment of the present invention 5 completion grinding process after schematic diagram;
Figure 32, which is the back surface to silicon wafer 200 of the embodiment of the present invention 5, is greater than 7 degree of injecting p-type boron dopings with implant angle
Matter ion schematic diagram;
Figure 33 is the back surface injection P31 doping ion schematic diagram to silicon wafer for implementing 51;
Figure 34 is the cross-sectional structure schematic diagram that the embodiment of the present invention 5 completes device after rear electrode 15;
Figure 35 is the cross-sectional structure schematic diagram that the embodiment of the present invention 6 completes device after rear electrode 15;
Figure 36, which is the back surface to silicon wafer 200 of the embodiment of the present invention 7, is greater than 10 degree of injecting p-type boron dopings with implant angle
Matter ion schematic diagram;
Figure 37 is the cross-sectional structure schematic diagram that the embodiment of the present invention 7 completes device after rear electrode 15;
Figure 38 is the cross-sectional structure schematic diagram that the embodiment of the present invention 8 completes device after rear electrode 15;
Reference symbol table:
1 passivation layer
2 aluminium alloy layers
3 inter-level dielectrics
4 highly doped polysilicons
5 N-type source regions
The p-type high-doped zone of 6 contact hole channel bottoms
7 p-type base areas
The N-type region of 8 trench bottoms
9 N-type base areas
10 N-type buffer layers
11 close to the p type island region of back metal
12 are greater than the P+ type area of 200um close to the width of back metal
13 close to the P+ type area of back metal
14 close to the N+ type area of back metal
15 rear electrodes
16 on N+ type area (farther from the back side) p type island region
17 surround the N-type buffer area in the back side area P+
100 it is original be not thinned before substrate
200 complete the substrate after wear down process
Specific embodiment
Embodiment 1:
As shown in figure 19, the manufacturing process of the chip of entire power device can be divided into preceding working procedure and later process, preceding road
Process the surface cell of device, as IGBT device surface UMOS unit making silicon wafer 100 front surface, before silicon wafer
It is the inter-level dielectric 3 of UMOS unit, metal layer 2 (titanium/titanium nitride layer, tungsten and aluminium alloy) and passivation layer 1 on surface.Manufacture exists
Device on 100 surface of silicon wafer is also possible to MCT or GTO, and silicon wafer described here is FZ N-type silicon chip or CZ N-type silicon
Piece, resistance value is depending on the pressure resistance of manufactured device, and if pressure resistance is 1200V, resistance value range is about 50 Ω .cm to 120 Ω
.cm, with a thickness of thickness used in routine before not being thinned generally, about 400um to 720um is thick.
As shown in figure 20,100 wear down of silicon wafer that preceding road technique is completed to such as be manufactured 1200V pressure resistance to required thickness
Device, then after the completion of wear down process, thickness is about 110um, and silicon wafer 100 becomes silicon wafer 200.
As shown in figure 21, N type dopant such as P31 is injected through mask plate to the back surface of silicon wafer 200, implant angle is greater than
7 degree, dosage range is 1 × 1012/cm2To 5 × 1015/cm2, Implantation Energy range is 100KeV to 2MeV, this step is used to shape
At the N+ type area 14 of Figure 23 backside structure.
As shown in figure 22, after previous step completes ion implanting, the relative position before mask plate and silicon wafer is kept, so
Boron dope agent is injected through the mask plate of previous step to the back surface of silicon wafer 200 afterwards, implant angle is spent between range for 0 to 7,
Dosage range is 1 × 1015/cm2To 1 × 1016/cm2, Implantation Energy range is 20KeV to 200KeV, this step is used to form figure
The P+ type area 13 of 23 backside structures.
As shown in figure 23, silicon wafer 200 is placed in temperature range is 300 DEG C to 450 DEG C, and anneal 30mins to 100mins, is moved back
Fiery step activates the boron and P31 dopant of injection, forms P+ type area 13 and N+ type area 14, later with sputtering or deposition method handle
The metallization of 200 back surface of silicon wafer, as the rear electrode 15 of device, metal layer material can be Al/Ti/Ni/Ag or Ti/Ni/Ag
Or Al/Ti/Ni/Au etc..
In embodiment 1, annealing can also be after completing rear electrode metallization or overleaf electrode metallization step is worked as
Middle progress.
Embodiment 2:
The technical solution of the present embodiment is roughly the same with embodiment 1, and difference is only that:
In above-described embodiment 1, after 100 wear down to required thickness of silicon wafer;Make in the back surface to silicon wafer 200 any
Before injection, or behind the area injection P+ and the area N+ described in completion, pays and adds following injection step:
As shown in figure 24, hydrogen doping agent is injected to the back surface of silicon wafer 200, implant angle is 0 degree, dosage range for 1 ×
1012/cm2To 5 × 1015/cm2, Implantation Energy range is 100KeV to 2MeV, and the N-type that this step is used to be formed backside structure is slow
Rush layer 10.
Later step such as embodiment one after implantation is completed the step of, the Structure of cross section of device is as shown in figure 25.
Embodiment 3:
The technical solution of the present embodiment is roughly the same with embodiment 1, and difference is only that:
In above-described embodiment 1, after completing the area injection P+ and the area N+, pays and adds following injection step:
As shown in figure 26, after previous step completes ion implanting, the relative position before mask plate and silicon wafer is kept, so
Hydrogen doping agent is injected through the mask plate of previous step to the back surface of silicon wafer 200 afterwards, implant angle is 0 degree, dosage range 1
×1012/cm2To 5 × 1015/cm2, Implantation Energy range is 100KeV to 2MeV, this step is used to be formed the N-type of backside structure
Layer 16.
Later step such as scheme one after implantation is completed the step of, the Structure of cross section of device is as shown in figure 27.
Embodiment 4:
The technical solution of the present embodiment is roughly the same with embodiment 2, and difference is only that:
It is paid in above-described embodiment 2 and adds following injection step:
As shown in figure 28, boron dope agent is injected to the back surface of silicon wafer 200, does not need mask plate, implant angle be 0 degree extremely
Between 7 degree of ranges, dosage range is 1 × 1013/cm2To 1 × 1015/cm2, Implantation Energy range is 20KeV to 200KeV, this step
The rapid P-type layer 11 for being used to be formed backside structure.
Later step such as scheme one after implantation is completed the step of, the Structure of cross section of device is as shown in figure 29.
Embodiment 5:
As shown in figure 30, the manufacturing process of the chip of entire power device can be divided into preceding working procedure and later process, preceding road
Process the surface cell of device, as FRD device surface unit making silicon wafer 100 front surface, in the front surface of silicon wafer
On be UMOS unit inter-level dielectric 3, metal layer 2 (titanium/titanium nitride layer, tungsten and aluminium alloy) and passivation layer 1.Manufacture is in silicon wafer
Device on 100 surfaces is also possible to MCT or GTO, and silicon wafer described here is FZ N-type silicon chip or CZ N-type silicon chip, electricity
Resistance value is depending on the pressure resistance of manufactured device, and if pressure resistance is 1200V, resistance value range is about 50 Ω .cm to 120 Ω .cm, thickness
For thickness used in routine before not being thinned generally, about 400um to 720um is thick.
As shown in figure 31,100 wear down of silicon wafer that preceding road technique is completed to such as be manufactured 1200V pressure resistance to required thickness
Device, then after the completion of wear down process, thickness is about 110um, and silicon wafer 100 becomes silicon wafer 200.
As shown in figure 32, mask plate injecting p-type dopant such as boron is penetrated to the back surface of silicon wafer 200, implant angle is greater than 7
Degree, dosage range are 1 × 1015/cm2To 1 × 1016/cm2, Implantation Energy range is 100KeV to 2MeV, this step is used to be formed
The P+ type area 13 of Figure 34 backside structure.
As shown in figure 33, after previous step completes ion implanting, the relative position before mask plate and silicon wafer is kept, so
N type dopant such as P31 is injected through the mask plate of previous step to the back surface of silicon wafer 200 afterwards, implant angle is 0 to 7 degree model
Between enclosing, dosage range is 1 × 1014/cm2To 6 × 1015/cm2, Implantation Energy range is 20KeV to 200KeV, this step is used
To form the N+ type area 14 of Figure 34 backside structure.
As shown in figure 34, silicon wafer 200 is placed in temperature range is 300 DEG C to 450 DEG C, and anneal 30mins to 100mins, is moved back
Fiery step activates the boron and P31 of injection and hydrogen doping agent, forms P+ type area 13 and N+ type area 14, later with sputtering or deposition side
Method metallizes 200 back surface of silicon wafer, and as the rear electrode 15 of device, metal layer material can be Al/Ti/Ni/Ag or Ti/
Ni/Ag or Al/Ti/Ni/Au etc..
In embodiment 5, annealing can also be after completing rear electrode metallization or overleaf electrode metallization step is worked as
Middle progress.
Embodiment 6:
The technical solution of the present embodiment is roughly the same with embodiment 5, and difference is only that:
In above-described embodiment 5, after 100 wear down to required thickness of silicon wafer;Make in the back surface to silicon wafer 200 any
Before injection, or behind the area injection P+ and the area N+ described in completion, pays and adds following injection step:
Mask plate is not needed later, hydrogen doping agent is injected to the back surface of silicon wafer 200, implant angle is 0 degree, dosage range
It is 1 × 1014/cm2To 1 × 1015/cm2, Implantation Energy range is 100KeV to 2MeV, this step is used to be formed the N of backside structure
Type buffer layer 10.
Later step such as scheme one after implantation is completed the step of, the Structure of cross section of device is as shown in figure 35.
Embodiment 7:
The technical solution of the present embodiment is roughly the same with embodiment 6, and difference is only that:
It pays in the above-described embodiments and adds following injection step:
As shown in figure 36, after completing the area injection P+ and the area N+ or before, before keeping mask plate and silicon wafer
Then relative position penetrates the mask plate injecting p-type dopant such as boron of previous step, implant angle to the back surface of silicon wafer 200
Greater than 10 degree, dosage range is 1 × 1014/cm2To 1 × 1015/cm2, Implantation Energy range is 20KeV to 2.0MeV, this step
For forming the p type island region 18 of Figure 37 backside structure.
Boron dope agent is injected to the back surface of silicon wafer 200 later, does not need mask plate, implant angle is 0 degree to 7 degree range
Between, dosage range is 1 × 1013/cm2To 1 × 1016/cm2, Implantation Energy range is 20KeV to 200KeV, this step is used to
Form the P-type layer 11 of backside structure.
Later step such as scheme one after implantation is completed the step of, the Structure of cross section of device is as shown in figure 37.
Embodiment 8:
The technical solution of the present embodiment is roughly the same with embodiment 6, and difference is only that:
It pays in the above-described embodiments and adds following injection step:
Boron dope agent is injected to the back surface of silicon wafer 200, does not need mask plate, implant angle be 0 degree to 7 degree range it
Between, dosage range is 1 × 1014/cm2To 5 × 1015/cm2, Implantation Energy range is 20KeV to 200KeV, this step is used to shape
At the P-type layer 11 of backside structure.
Later step such as scheme one after implantation is completed the step of, the Structure of cross section of device is as shown in figure 38.
Embodiment 9:
The technical solution of the present embodiment is roughly the same with embodiment before, and difference is only that:
In the above-described embodiments, after 100 wear down to required thickness of silicon wafer;Make in the back surface to silicon wafer 200 any
Before injection, minimum one layer of metal layer first is formed in 200 back surface of silicon wafer with sputtering or deposition method, metal layer can be aluminium,
Or aluminium alloy, or silver, or gold or titanium or titanium nitride or tungsten, thickness are about 0.05um to 1.0um, are injected later, annealing with
Surface metalation and etc. the step as described in above-described embodiment it is identical.
Finally, it should be noted that these are only the preferred embodiment of the present invention, it is not intended to restrict the invention, this hair
It is bright can be used for being related to manufacture semiconductor power device (for example, trench insulated gate bipolar transistor Trench IGBT or MCT or
GTO), the summary of the invention with embodiment of this document are made an explanation with N-type passage device, and the present invention also can be used for p-type channel device
Part for those skilled in the art, still can be with although invention is explained in detail referring to embodiment
It modifies the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features, but
It is that all within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should be included in the present invention
Protection scope within.
Claims (12)
1. a kind of backside structure of semiconductor devices includes at least following part:
(1) close to the independent area P+ (13) of semiconductor back surface at least one, width is greater than 20um, the one side in this area P+ (13) with
Back metal is connected to form Ohmic contact, and another side is surrounded by N-type buffer layer (10), the doping concentration range in this area P+ (13)
It is 5 × 1018/cm3To 1 × 1020/cm3;
(2) close to the independent area N+ (14) of semiconductor back surface at least one, width is greater than 20um, the one side in this area N+ (14) with
Back metal is connected to form Ohmic contact, and another side has part to be surrounded compared with low-doped n type buffer layer (10), this area N+ (14)
Doping concentration range be 5 × 1018/cm3To 1 × 1020/cm3;
(3) there are three types of different doped regions and back metal contacts for semiconductor back surface, these three different doped regions are the areas P+
(13), the area N+ (14) and N-type base area (9);
(4) back metal is connected to form rear electrode with semiconductor back surface, and wherein back metal and the area P+ (13) form ohm
Contact, wherein back metal and the area N+ (14) form Ohmic contact, form non-ohmic contact with N-type base area (9).
2. backside structure according to claim 1, in the area P+ (13) of part (1), it is characterised in that there is more than one P+
The width in area (13), the area wherein at least one P+ (13) is greater than 200um.
3. backside structure according to claim 1, in the area P+ (13) of part (1), it is characterised in that in addition to N-type base area
(9) except, an additional N-type buffer layer (10) surrounds the area P+ (13), this additional N-type buffer layer (10) is in the area P+
(13) thickness outside is greater than 0.5um, and the doping concentration range of this additional N-type buffer layer (10) is 5 × 1014/cm3To 5 ×
1017/cm3。
4. a kind of backside structure of semiconductor devices includes at least following part:
(1) semiconductor back surface has a N-type buffer layer (10), this N-type buffer layer (10) N-type base area (9) one side from semiconductor
The depth at the back side is greater than 1um, and doping concentration range is 5 × 1014/cm3To 5 × 1017/cm3;
(2) there are a P-type layer (11) close to semiconductor back surface, one side and the back metal of this P-type layer (11) form non-ohm and connect
Touching, another side are connected with N-type buffer layer (10), this P-type layer (11) is small far from the depth at the back side on one side of N-type buffer layer (10)
In 1um, doping concentration range is 1 × 1015/cm3To 1 × 1018/cm3;
(3) close to the independent area P+ (13) of semiconductor back surface at least one, width range is greater than 20um, and the one of this area P+ (13)
Side and back metal form Ohmic contact, have part Chong Die with P-type layer (11) in the area P+ (13) close to the back side, are overlapped with outside
Part is surrounded by N-type buffer area (10), and the knot that this area P+ (13) and N-type buffer layer (10) are formed is buffered than P-type layer (11) and N-type
The knot that layer (10) is formed is more deep, i.e., further from back surface, the doping concentration range in this area P+ (13) is 5 × 1018/cm3To 1
×1020/cm3;
(4) close to the independent area N+ (14) of semiconductor back surface at least one, width is greater than 20um, the one side in this area N+ (14) with
Back metal is connected to form Ohmic contact, and another side has part to be surrounded compared with low-doped n type buffer layer (10), this area N+ (14)
Doping concentration range be 5 × 1018/cm3To 1 × 1020/cm3;
(5) there are three types of different doped regions and back metal contacts for semiconductor back surface, these three different doped regions are the areas P+
(13), the area N+ (14) and P-type layer (11);
(6) back metal is connected to form rear electrode with semiconductor back surface, and wherein back metal and the area P+ (13) form ohm
Contact, wherein back metal and the area N+ (14) form Ohmic contact, form non-ohmic contact with P-type layer (11).
5. backside structure according to claim 4, in the area P+ (13) of part (3), it is characterised in that there is more than one P+
The width in area (13), the area wherein at least one P+ (13) is greater than 200um.
6. backside structure according to claim 4, in the area P+ (13) of part (3), it is characterised in that the area P+ (13) and back
The area total contact area ratio N+ (14) of face metal and the total contact area of back metal are more.
7. backside structure according to claim 4, in the area P+ (13) of part (3), it is characterised in that the area P+ (13) and back
The area total contact area ratio N+ (14) of face metal and the total contact area of back metal are small.
8. backside structure according to claim 4, in the area P+ (13) of part (3), it is characterised in that the area P+ (13) and back
Total contact area of face metal contact area more total than P-type layer (11) and back metal is more.
9. a kind of backside structure of semiconductor devices includes at least following part:
(1) semiconductor back surface has a N-type buffer layer (10), this N-type buffer layer (10) N-type base area (9) one side from semiconductor
The depth at the back side is greater than 1um, and doping concentration range is 5 × 1014/cm3To 5 × 1017/cm3;
(2) close to the independent area P+ (13) of semiconductor back surface at least one, width range is greater than 20um, and the one of this area P+ (13)
Side and back metal form Ohmic contact, and another side is surrounded by N-type buffer layer (10), and the doping concentration range in this area P+ (13) is
5×1018/cm3To 1 × 1020/cm3;
(3) close to the independent area N+ (14) of semiconductor back surface at least one, width is greater than 20um, the one side in this area N+ (14) with
Back metal is connected to form Ohmic contact, and another side has to be surrounded compared with low-doped n type buffer layer (10) partially or in whole, this N+
The doping concentration range in area (14) is 5 × 1018/cm3To 1 × 1020/cm3;
(4) there are three types of different doped regions and back metal contacts for semiconductor back surface, these three different doped regions are the areas P+
(13), the area N+ (14) and N-type buffer layer (10);
(5) back metal is connected to form rear electrode with semiconductor back surface, and wherein back metal and the area P+ (13) form ohm
Contact, wherein back metal and the area N+ (14) form Ohmic contact, form non-ohmic contact with N-type buffer layer (10).
10. backside structure according to claim 9, in the area N+ (14) of part (3), it is characterised in that the area N+ (14) and back
The area total contact area ratio P+ (13) of face metal and the total contact area of back metal are more.
11. backside structure according to claim 9, in the area N+ (14) of part (3), it is characterised in that the area N+ (14) and back
Total contact area of face metal contact area more total than N-type buffer layer (10) and back metal is small.
12. backside structure according to claim 9, in the area N+ (14) of part (3), it is characterized in that on the top of the area N+ (14)
Portion is attached with a p type island region (16), this additional p type island region (16) is greater than 0.5um, this additional p-type in the thickness of the area N+ (14) outside
The doping concentration range in area (16) is 5 × 1014/cm3To 5 × 1017/cm3。
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US4914043A (en) * | 1986-09-26 | 1990-04-03 | Zaidan Hojin Handotai Kenkyu Shinkokai | Method of making an integrated light-triggered and light-quenched static induction thyristor |
US5668385A (en) * | 1993-04-22 | 1997-09-16 | Asea Brown Boveri Ag | Power semiconductor component with transparent emitter and stop layer |
CN101419970A (en) * | 2007-10-24 | 2009-04-29 | 富士电机电子技术株式会社 | Semiconductor device with control circuit |
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US4914043A (en) * | 1986-09-26 | 1990-04-03 | Zaidan Hojin Handotai Kenkyu Shinkokai | Method of making an integrated light-triggered and light-quenched static induction thyristor |
US5668385A (en) * | 1993-04-22 | 1997-09-16 | Asea Brown Boveri Ag | Power semiconductor component with transparent emitter and stop layer |
CN101419970A (en) * | 2007-10-24 | 2009-04-29 | 富士电机电子技术株式会社 | Semiconductor device with control circuit |
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