CN105070681A - GaAs substrate mHEMT active region electrical isolating method - Google Patents
GaAs substrate mHEMT active region electrical isolating method Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 title claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 49
- 238000005468 ion implantation Methods 0.000 claims abstract description 23
- 230000000694 effects Effects 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 238000001039 wet etching Methods 0.000 claims abstract description 7
- 239000000523 sample Substances 0.000 claims description 77
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 20
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 20
- 238000001259 photo etching Methods 0.000 claims description 15
- 239000008367 deionised water Substances 0.000 claims description 13
- 229910021641 deionized water Inorganic materials 0.000 claims description 13
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 13
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 10
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000005566 electron beam evaporation Methods 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 239000011259 mixed solution Substances 0.000 claims description 5
- 238000010276 construction Methods 0.000 claims description 4
- 238000000276 deep-ultraviolet lithography Methods 0.000 claims description 4
- 238000005406 washing Methods 0.000 claims description 4
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- -1 boron ion Chemical class 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 3
- 239000000243 solution Substances 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 238000007781 pre-processing Methods 0.000 claims description 2
- 238000004064 recycling Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- UQEAIHBTYFGYIE-UHFFFAOYSA-N hexamethyldisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)C UQEAIHBTYFGYIE-UHFFFAOYSA-N 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 241000216843 Ursus arctos horribilis Species 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/7605—Making of isolation regions between components between components manufactured in an active substrate comprising AIII BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30612—Etching of AIIIBV compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The invention discloses a GaAs substrate mHEMT active region electrical isolating method, which is a method combining wet etching and ion implantation for active region electrical isolation of a various-component high-electron-mobility transistor. The GaAs substrate mHEMT active region electrical isolating method comprises the steps of removing a surface highly-doped layer and then carrying out ion implantation isolation, thereby effectively improving the ion implantation effect, and further improving the isolation effect between active regions. Under the same condition, the isolating method combining ion implantation and mesa etching has the advantages of good electrical isolation effect, high process compatibility, small impact on subsequent process, good reproducibility, easy implementation and the like, effectively avoids the defects caused by adopting mesa etching and ion implantation separately, and has good use value for the semiconductor manufacturing process.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, be specifically related to a kind of gallium arsenide substrate mHEMT (becoming component High Electron Mobility Transistor) active area electric isolation method.
Background technology
In semiconductor fabrication process process, the Major Technology of compound semiconductor device active area electric isolation comprises: mesa etch isolation and injection isolation.
Mesa etch method realizes electric isolation to be had many not beneficial, and such as deep-submicron grizzly bar easily occurs disconnected bar when crossing over the corrosion step of hundreds of nanometer and affects rate of finished products; Secondly, the active region mesa eroded away easily causes and contacts with conducting channel by during mesa side walls at grizzly bar, causes the increase of grid leakage current, the decline of grid puncture voltage; 3rd, the exposed heterojunction section at mesa side walls is easily corroded in technique preparation process, stain, also have when passivating film covers that a certain amount of to exhaust this be also usually produced problem in semiconductor preparing process process.
Relative to mesa etch, ion implantation is good selection, because it maintains the planar structure of device. this is conducive to device manufacture and chip technology processing.And ion implantation avoids the leakage of mesa sides grid, because this eliminating grid leakage problem.And a large amount of theory analysises and experimental result all show, the ideal isolation only adopting ion injection method to realize the InGaAs/InAlAsmHEMT of gallium arsenide substrate is inconvenient, this is because the InGaAs band gap of Lattice Matching is only 0.74eV, its intrinsic resistivity is very little, and along with the raising of In component, InGaAs raceway groove will narrow further, and intrinsic resistance is less; On the other hand, the ion of activation forms shallow donor's energy level in the material isolation performance also can be caused to be deteriorated; 3rd, inject Main ion profiles and substantially follow Gaussian Profile rule, the peak value of its concentration, or not surface, will inevitably affect the note people insulation resistance of very thin highly doped InGaAs cap layers.
Summary of the invention
The present invention is directed to and adopt separately mesa etch isolation and inject the drawback that isolation method carries out existing for the electric isolation of active area of semiconductor device, a kind of gallium arsenide substrate mHEMT active area electric isolation method is provided, it adopts wet etching to combine with ion implantation, realizes good active area isolation effect.
For solving the problem, the present invention is achieved by the following technical solutions:
A kind of gallium arsenide substrate mHEMT active area electric isolation method, comprises the steps:
Step 1, carries out organic washing and inorganic cleaning to sample, to guarantee that sample clean is clean; Sample is the epitaxial material system of the change component sandwich construction that gallium arsenide substrate grows, and the superiors of this epitaxial material system are cap layers;
Step 2, the active area of even glue photoetching protection sample, and firmly treatment is carried out so that isolation technology below to the sample after photoetching;
Step 3, carries out wet etching to sample, the cap layers of removing sample, and is formed with the groove being beneficial to ion implantation;
Step 4, being injected in sample by ion by removing cap layers region, being formed with the electric isolation in source region;
Step 5, carries out the photoetching of ohmic metal growth to sample, and utilizes electron beam evaporation platform evaporated devices ohmic metal on sample.
In above-mentioned steps 1, described cap layers comprises In
0.53ga
0.47as cap layers and In
0.65ga
0.35as cap layers, wherein In
0.53ga
0.47as cap layers and n
0.65ga
0.35as cap layers institute doping is Si.
In above-mentioned steps 1, the process of sample being carried out to organic washing is specially: be first statically placed in acetone soln by sample and soak, to remove the organic pollution of sample surfaces; Again sample is statically placed in aqueous isopropanol, removes the acetone on sample surfaces; After use deionized water rinsing, and nitrogen dries up; The process of sample being carried out to inorganic cleaning is specially: first soak sample with the mixed solution of ammoniacal liquor and deionized water, then use deionized water rinsing, and nitrogen dries up.
In above-mentioned steps 3, utilize the cap layers of citric acid and hydrogen peroxide mixed solution erosion removal sample surfaces.
In above-mentioned steps 4, the injection of boron ion need to utilize ion implantation simulation software calculate actual ions inject needed for energy, and be used for instructing energy and the dosage of actual ion implantation, to reduce the process costs of device.
In above-mentioned steps 5, electron beam evaporation platform is adopted to evaporate Ni, AuGe, Ni and Au successively from bottom to top, to form source and drain metal ohmic contact electrode.
In above-mentioned steps 2 and 5, the process of photoetching is specially: the surface first photoresist being coated to equably sample, and recycling deep-UV lithography machine exposes sample, and the rear developer solution that utilizes develops to the sample after exposure, use deionized water fixing again, and nitrogen dry up.
In above-mentioned steps 2 and step 5, all needed to carry out to sample the preprocessing process that sample surfaces is coated with adhesive before each photoetching, to strengthen the adhesiveness of photoresist and sample surfaces, thus the success rate of raising sample photoetching.
After above-mentioned steps 5, also comprise further, step 6, utilize probe station and test with the electric isolation effect of semiconductor test analyzer to the adjacent devices on sample, and verifying the process of this active area isolation effect.
Compared with prior art, the present invention has following features:
1, for the active area electric isolation becoming component High Electron Mobility Transistor, propose the partition method that wet etching and ion implantation combine, namely first utilize wet etching to remove sample surfaces heavily doped layer, then form the method for isolation by ion implantation.First remove surperficial heavily doped layer, then carry out ion implantation isolation, effectively improve the injection effect of ion implantation, and then improve the isolation effect between active area;
2, under equal conditions, the partition method that ion implantation and mesa etch combine, have that electric isolation is effective, processing compatibility be strong, less on subsequent technique impact, there is good repeatability and be convenient to the features such as realization, and efficiently avoid the drawback adopting separately mesa etch and ion implantation, there is good use value to semiconductor fabrication process.
Accompanying drawing explanation
Fig. 1-Fig. 5 is the preparation flow schematic diagram of a kind of gallium arsenide substrate mHEMT active area electric isolation method.
Fig. 6 is the I-V curve chart of the sample adjacent devices active area electric isolation adopting the present invention to prepare.
Embodiment
A kind of gallium arsenide substrate mHEMT active area electric isolation method, as Figure 1-Figure 5, comprises the steps:
Step one: the cleaning of device extension sample.
Clean sample, wherein sample is the epitaxial material system of the change component sandwich construction that gallium arsenide substrate grows, and this epitaxial material system comprises cap layers, barrier layer, channel layer and resilient coating etc., and wherein cap layers is positioned at the superiors.Cap layers is that doping content is higher, is conducive to the heavily doped layer forming ohmic contact with metal.In the present invention, described cap layers is the In of 5nm
0.53ga
0.47the In of As layer and 20nm
0.65ga
0.35as layer, institute's doping is Si (silicon), and concentration is 10E+19cm
-3.The change component sandwich construction epitaxial material system sample that gallium arsenide substrate grows can be obtained by MBE (molecular beam epitaxy) growth.First, organically clean: sample is statically placed in acetone soln and soaks 5 minutes, to remove the organic pollution of sample surfaces; Sample to be statically placed in aqueous isopropanol 5 minutes, to remove the acetone on sample surfaces; With deionized water rinsing 6 times, nitrogen dries up.Secondly, carry out inorganic cleaning: utilize the ammoniacal liquor of 25%: deionized water=1:10, sample is soaked 2 minutes, deionized water rinsing 6 times, nitrogen dries up.Finally guarantee that sample clean is clean.
Step 2: active area electric isolation photoetching.See Fig. 1.
Before even glue photoetching protection table top, first HMDS (hexamethyldisiloxane) surface preparation is carried out to sample, to strengthen the adhesiveness of photoresist and sample surfaces.Even photoresist AZ5214, rotating speed is 4000 revolutions per seconds, the time is 30 seconds.Front baking, temperature is 95 DEG C, the time is 90 seconds.MA6 deep-UV lithography machine is utilized to expose 6.5 seconds.Use JZX3038 developing liquid developing 45 seconds, deionized water is fixing, and nitrogen dries up.Utilize hot plate 110 DEG C, 3 minutes for post bake.
Step 3: wet etching removes the heavily doped layer of sample surfaces.See Fig. 2.
Utilize heavily doped layer and the In of citric acid and hydrogen peroxide mixed solution erosion removal device epitaxial layers material surface
0.53ga
0.47as cap layers and In
0.65ga
0.35as cap layers.That is: C is utilized
6h
8o
7: H
2o
2=1:1 corrosive liquid corrosion In
0.53ga
0.47as cap layers and In
0.65ga
0.35as cap layers, etching time is 1 minute 45 seconds.
Step 4: ion implantation is carried out to sample.See Fig. 3.
First utilize ion implantation simulation software SRIM to carry out analog computation, calculate actual ions inject needed for energy, and be used for instructing energy and the dosage of actual ion implantation.Through calculating simulation repeatedly, for material system of the present invention, finally we adopt ion implantor, and select boron ion, Implantation Energy is 20Kev, and implantation dosage is 2.0E+14cm-2, with channel part is formed high-barrier from.
Step 6: device ohmic metal.See Figure 4 and 5.
First, the active isolated area formed is carried out to the photoetching of ohmic contact.HMDS surface preparation is carried out to sample, to strengthen the adhesiveness of photoresist and sample surfaces.Even photoresist AZ5214, rotating speed is 4000 revolutions per seconds, the time is 30 seconds.Dust-free cotton bud is used to remove the photoresist of sample edge part.Front baking, temperature is 95 DEG C, the time is 90 seconds.MA6 deep-UV lithography machine is utilized to expose 1.9 seconds.Carry out reversion to sample to dry, temperature is 110 DEG C, the time is 90 seconds.General exposure 42 seconds is carried out to sample.Use JXZ3038 developing liquid developing 50 seconds.Deionized water is fixing.Nitrogen dries up.Electron beam evaporation platform is adopted to evaporate Ni (5nm)/AuGe (100nm)/Ni (20nm)/Au (100nm) successively, to form source and drain metal and gate electrode, namely source, leakage metal are formed by stacking from bottom to top by the Au of Ni and 100nm of AuGe, 20nm of Ni, 100nm of 5nm, do not need annealing, form ohmic contact, the source-drain contact resistance utilizing TLM to test is 0.1 Ω mm, and ohmic contact resistance is 1.3E-6 Ω cm
2.
Step 5: the isolation effect test of active area electric isolation.
Utilize probe station Cascade150 and semiconductor test analyzer AgilentB1505A, carry out the electric isolation effect between adjacent devices.Spacing between adjacent devices is 17 μm, the ohmic contact contact electrode (pad) of adjacent devices adds voltage, tests size of current between them, be the isolation effect under active area.Fig. 6 is the test I-V curve of the adjacent devices isolation effect on sample.
Claims (9)
1. a gallium arsenide substrate mHEMT active area electric isolation method, is characterized in that: comprise the steps:
Step 1, carries out organic washing and inorganic cleaning to sample, to guarantee that sample clean is clean; Sample is the epitaxial material system of the change component sandwich construction that gallium arsenide substrate grows, and the superiors of this epitaxial material system are cap layers;
Step 2, the active area of even glue photoetching protection sample, and firmly treatment is carried out so that isolation technology below to the sample after photoetching;
Step 3, carries out wet etching to sample, the cap layers of removing sample, and is formed with the groove being beneficial to ion implantation;
Step 4, being injected in sample by ion by removing cap layers region, being formed with the electric isolation in source region;
Step 5, carries out the photoetching of ohmic metal growth to sample, and utilizes electron beam evaporation platform evaporated devices ohmic metal on sample.
2. a kind of gallium arsenide substrate mHEMT active area according to claim 1 electric isolation method, it is characterized in that: in step 1, described cap layers comprises In
0.53ga
0.47as cap layers and In
0.65ga
0.35as cap layers, wherein In
0.53ga
0.47as cap layers and n
0.65ga
0.35as cap layers institute doping is Si.
3. a kind of gallium arsenide substrate mHEMT active area according to claim 1 electric isolation method, is characterized in that: in step 1,
The process of sample being carried out to organic washing is specially: be first statically placed in acetone soln by sample and soak, to remove the organic pollution of sample surfaces; Again sample is statically placed in aqueous isopropanol, removes the acetone on sample surfaces; After use deionized water rinsing, and nitrogen dries up;
The process of sample being carried out to inorganic cleaning is specially: first soak sample with the mixed solution of ammoniacal liquor and deionized water, then use deionized water rinsing, and nitrogen dries up.
4. a kind of gallium arsenide substrate mHEMT active area according to claim 1 electric isolation method, is characterized in that: in step 3, utilizes the cap layers of citric acid and hydrogen peroxide mixed solution erosion removal sample surfaces.
5. a kind of gallium arsenide substrate mHEMT active area according to claim 1 electric isolation method, it is characterized in that: in step 4, the injection of boron ion need to utilize ion implantation simulation software calculate actual ions inject needed for energy, and be used for instructing energy and the dosage of actual ion implantation, to reduce the process costs of device.
6. a kind of gallium arsenide substrate mHEMT active area according to claim 1 electric isolation method, is characterized in that: in step 5, adopts electron beam evaporation platform to evaporate Ni, AuGe, Ni and Au successively from bottom to top, to form source and drain metal ohmic contact electrode.
7. a kind of gallium arsenide substrate mHEMT active area according to claim 1 electric isolation method, it is characterized in that: in step 2 and 5, the process of photoetching is specially: the surface first photoresist being coated to equably sample, recycling deep-UV lithography machine exposes sample, the rear developer solution that utilizes develops to the sample after exposure, use deionized water fixing again, and nitrogen dry up.
8. a kind of gallium arsenide substrate mHEMT active area electric isolation method according to claim 1 or 7, it is characterized in that: in step 2 and step 5, all needed to carry out to sample the preprocessing process that sample surfaces is coated with adhesive before each photoetching, to strengthen the adhesiveness of photoresist and sample surfaces, thus improve the success rate of sample photoetching.
9. a kind of gallium arsenide substrate mHEMT active area according to claim 1 electric isolation method, it is characterized in that: after step 5, also comprise further, step 6, utilize probe station and test with the electric isolation effect of semiconductor test analyzer to the adjacent devices on sample, and verifying the process of this active area isolation effect.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106257686A (en) * | 2016-04-07 | 2016-12-28 | 苏州能讯高能半导体有限公司 | Semiconductor device and manufacture method thereof |
| CN108281352A (en) * | 2018-01-26 | 2018-07-13 | 成都海威华芯科技有限公司 | A kind of device isolation method applied to gallium nitride transistor |
| CN112557496A (en) * | 2020-11-20 | 2021-03-26 | 广东先导稀材股份有限公司 | Preparation method and application of needle-shaped sample for glow discharge mass spectrometry detection |
| CN113363255A (en) * | 2021-06-02 | 2021-09-07 | 厦门市三安集成电路有限公司 | Semiconductor device and preparation method thereof |
| CN113363254A (en) * | 2021-06-02 | 2021-09-07 | 厦门市三安集成电路有限公司 | Semiconductor device and preparation method thereof |
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| CN1326229A (en) * | 2000-05-31 | 2001-12-12 | 中国科学院半导体研究所 | Transistor with high electron mobility and its preparing process |
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