CN104701174B - Method for pressing trench grate MOS processing technology in optimization - Google Patents
Method for pressing trench grate MOS processing technology in optimization Download PDFInfo
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- CN104701174B CN104701174B CN201310661168.2A CN201310661168A CN104701174B CN 104701174 B CN104701174 B CN 104701174B CN 201310661168 A CN201310661168 A CN 201310661168A CN 104701174 B CN104701174 B CN 104701174B
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- source
- silica
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000005457 optimization Methods 0.000 title description 4
- 238000003825 pressing Methods 0.000 title description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 55
- 238000001259 photo etching Methods 0.000 claims abstract description 35
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 27
- 238000001459 lithography Methods 0.000 claims abstract description 23
- 238000002347 injection Methods 0.000 claims abstract description 18
- 239000007924 injection Substances 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 11
- 230000000694 effects Effects 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 229910003978 SiClx Inorganic materials 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 19
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of method for being used in optimizing press trench grate MOS processing technology, the minimum lithographic number of plies of this method is 3 layers, is trench lithography, contact hole photoetching, metal layer lithography respectively；Define groove figure and body injection figures simultaneously using trench lithography, wherein body injection figures include protection ring structure.Then make full use of CVD silica film forming characteristics and dry method to be etched back to anisotropic principle, part body is injected in figure and fills up silica, oxide side walls are formed in groove figure region.Final realize utilizes one layer of photoetching, realizes the definition of groove and the layer patterns of body two.The present invention is improved to existing middle pressure trench grate MOS layout design and processing technology, saves one layer of photoetching process, so as to shorten technological process, reduce process costs.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing process, more particularly to one kind to be used for pressure trench grate MOS in optimizing and add
The method of work technique.
Background technology
In market competition, in order to reduce cost, the minimum lithographic number of plies is reduced to four layers by low pressure MOSFET techniques
(groove trench, source electrode source, contact hole contact, metal level metal), or even three layers of (groove trench, contact hole
Contact, metal level metal).
The existing minimum photoetching number of plies of Low-voltage trench gate MOSFET technique be four layers, trench, source, contact,
metal.Existing process flow is specific as follows：
1）Pad OX（Pad oxide）Growth, body photoetching, body injections, photoresist remove, and body annealing, are formed
Body areas 2, see Figure 1A；
2）Source photoetching, source injections, photoresist remove, and source annealing, form source areas 3, see Figure 1B；
3）Groove hard mask（Hard mask）Growth, trench lithography, groove hard mask etchings, etching groove, groove
Hard mask are removed；
4）Grid oxic horizon 4 is deposited, and grid polycrystalline silicon 5 deposits, and grid polycrystalline silicon 5 is etched back to, and sees Fig. 1 C；
5）Sacrificial oxidation film grows, sacrificial oxidation film etching；
6）Deielectric-coating (ILD) 6 deposits under metal；
7）The photoetching of contact hole 7, contact hole 7 etch, and see Fig. 1 D；
8）The growth of source class metal, photoetching, etching.
Middle pressure MOSFET element, in order to reach required breakdown voltage, it will usually increase protection ring knot in terminal area
Structure.
The figure for defining protection ring generally has two methods, when one layer of photoetching of increase, such as Guard ring photoetching
(Guard ring are a types of protection ring)；Second, pass through body（Body area）Photoetching defines.
For middle pressure MOSFET protection ring structure, one layer of photoetching certainly will be increased, can so cause process costs to rise,
Product competitiveness declines.
The content of the invention
Present invention solves the technical problem that it is to provide a kind of method for being used in optimizing press trench grate MOS processing technology, should
Method optimizes layout design and processing technology, and in the case where that need not increase Guard ring or Body photoetching, realization carries
The middle pressure MOSFET of partial pressure ring structure, so as to reduce process costs.
In order to solve the above technical problems, the present invention provides a kind of method for being used in optimizing press trench grate MOS processing technology,
The minimum lithographic number of plies of this method is 3 layers, is trench lithography, contact hole photoetching, metal layer lithography respectively；The trench lithography,
Define groove figure simultaneously by one layer of photoetching and body injects figure, the body injections figure includes protection ring structure.
Preferably, the trench lithography, groove figure is defined by one layer of photoetching simultaneously, body injects figure and source injection figures
The layer pattern of shape three.
This method specifically comprises the following steps：
Step 1, the hard mask growth of groove, trench lithography, the hard mask etching of groove；
Step 2, body injects, body annealing；
Step 3, source injects, source annealing；
Step 4, groove is silica-filled；
Step 5, groove silica is etched back to；
Step 6, etching groove；
Step 7, grid oxic horizon is deposited, and gate polycrystalline silicon deposit, grid polycrystalline silicon is etched back to；
Step 8, deielectric-coating ILD is deposited under metal；
Step 9, contact hole photoetching, contact hole etching；
Step 10, metal growth, photoetching, etching.
In step 1, the figure that the trench lithography is opened comprises at least two kinds of line widths a, b, a>B, wherein size is smaller at b
Figure only is injected as body, source, size is larger both as body, source injection figure at a, is used as again and defines groove
The figure of etching.
In step 1, a sizes are usually 0.4~1.5 μm, and b sizes are usually 0.1~0.5 μm, and a>b..
In step 3, it can increase by a step source photoetching before the source injections.
In step 4, the silica-filled technique of groove uses LPCVD or HTO to reach good conformality, after filling
Reach different effects at the groove figure of two kinds of line widths, silica is fully filled with b, and concave shape is formed at a.
In step 4, the thickness of silica is usually 1/2b~3/2b, can also be more than 3/2b, but can not be less than 1/
2b。
In step 5, after the groove silica is etched back to, different effects, b are reached at the groove figure of two kinds of line widths
Place is oxidized silicon and filled up, and monox lateral wall is formed at a.
In step 5, the etch amount being etched back to is silicon oxide deposition thickness and the over etching of increase by 30% in step 4.
Compared to the prior art, the invention has the advantages that：Present invention optimization layout design and processing technology, profit
Define groove figure and body injection figures simultaneously with trench lithography, wherein body injection figures include protection ring structure.Then
Make full use of CVD silica film forming characteristics and dry method to be etched back to anisotropic principle, part body is injected in figure and fills up oxygen
SiClx, oxide side walls are formed in groove figure region.Final realize utilizes one layer of photoetching, realizes groove and the layer patterns of body two
Definition.The present invention is improved to existing middle pressure trench grate MOS layout design and processing technology, saves one layer of photoetching work
Skill, so as to shorten technological process, reduce process costs.
Brief description of the drawings
Figure 1A-Fig. 1 D are the flow charts of existing Low-voltage trench gate MOSFET technique；Wherein, Figure 1A is step 1）Body anneals
Sectional schematic diagram afterwards；Figure 1B is step 2）Sectional schematic diagram after source annealing；Fig. 1 C are steps 4）Grid polycrystalline silicon returns
Sectional schematic diagram after etching；Fig. 1 D are steps 7）Sectional schematic diagram after contact hole etching.
Fig. 2A-Fig. 2 I are the flow charts of the inventive method；Wherein, Fig. 2A is the inventive method step 1 groove hard mask
Sectional schematic diagram after etching；Fig. 2 B are the sectional schematic diagrams after step 2body annealing of the present invention；Fig. 2 C are steps of the present invention
Sectional schematic diagram after 3source annealing；Fig. 2 D be step 4 groove of the present invention it is silica-filled after sectional schematic diagram；Fig. 2 E
It is the sectional schematic diagram after step 5 groove silica of the present invention is etched back to；Fig. 2 F are that step 7 grid polycrystalline silicon of the present invention is etched back to
Sectional schematic diagram afterwards；Fig. 2 G be step 4 groove of the present invention it is silica-filled after section effect diagram；Fig. 2 H are the present invention
Step 5 groove silica be etched back to after section effect diagram；Fig. 2 I are the section effects after step 6 etching groove of the present invention
Schematic diagram.
Description of reference numerals is as follows：
In Figure 1A-Fig. 1 D, 1 is silicon chip, and 2 be body areas, and 3 be source areas, and 4 be grid oxic horizon, and 5 be gate polycrystalline
Silicon, 6 be deielectric-coating under metal (ILD), and 7 be contact hole；
In Fig. 2A-Fig. 2 I, 21 be silicon chip, and 22 be groove, and 23 be body areas, and 24 be source areas, and 25 be silica,
25A is monox lateral wall, and 26 be grid oxic horizon, and 27 be grid polycrystalline silicon, and a is the line width of size large groove, b be size compared with
The line width of minor groove.
Embodiment
The present invention is further detailed explanation with reference to the accompanying drawings and examples.
The inventive method uses three layers of photoetching, is trench lithography, contact hole photoetching, metal layer lithography respectively.
Processing process is as follows：
1st, groove hard mask（Hard mask）Growth, trench lithography, groove hard mask etchings, schematic diagram such as Fig. 2A,
The figure that trench lithography is opened comprises at least two kinds of line widths a, b：A sizes are usually 0.4~1.5 μm, and b sizes are usually 0.1~
0.5 μm, size is smaller wherein at b only injects figure as body, source, and size is larger both as body, source note at a
Enter figure, again the figure as definition etching groove, as shown in Figure 2 A；
2nd, body injects, and body annealing, forms body areas 23, schematic diagram such as Fig. 2 B；
3rd, source injects, and source annealing, forms source areas 24, schematic diagram such as Fig. 2 C；Trench lithography, pass through one layer
Photoetching defines groove, body and the layer patterns of source tri- simultaneously, and wherein source figures can also increase by one layer of photoetching in addition
Definition；
4th, groove silica 25 is filled, schematic diagram such as Fig. 2 D, using LPCVD（Low-pressure chemical vapor phase deposition technique）Or HTO
（Thermal oxidation technology）Deposit, deposition thickness is usually 1/2b~3/2b, can also be more than 3/2b, but can not be less than 1/2b, effect
Fruit figure such as Fig. 2 G；The silica-filled technique of groove can use LPCVD or HTO to reach good conformality, fill latter two
Reach different effects at the groove figure of line width, as shown in Figure 2 D, silica is fully filled with a, and concave shape is formed at b；
5th, groove silica 25 is etched back to, schematic diagram such as Fig. 2 E, design sketch such as Fig. 2 H；Etch amount is that silica 25 deposits thickness
The over etching of degree increase by 30%, after groove silica is etched back to（Anisotropic principle is etched back to using dry method）, two kinds of line widths
Reach different effects at groove figure, being still oxidized silicon 25 as shown in Figure 2 E, at a is filled up, and monox lateral wall is formed at b
25A；
6th, etching groove, design sketch such as Fig. 2 I；
7th, grid oxic horizon 26 deposits, and grid polycrystalline silicon 27 deposits, and grid polycrystalline silicon 27 is etched back to schematic diagram such as Fig. 2 F；
8th, deielectric-coating (ILD) deposits under metal；
9th, contact hole photoetching, contact hole etching；
10th, metal growth, photoetching, etching.
Present invention optimization layout design and processing technology, groove figure and body injection figures are defined simultaneously using trench lithography
Shape, wherein body injection figure include protection ring structure.Then CVD silica film forming characteristics and dry method is made full use of to be etched back to respectively
The different in nature principle of item, part body is injected in figure and fill up silica, and oxide side walls are formed in groove figure region.It is final real
One layer of photoetching is now utilized, realizes the definition of groove and the layer patterns of body two.The present invention is to existing middle pressure trench grate MOS layout design
And processing technology is improved, one layer of photoetching process is saved, so as to shorten technological process, reduce process costs.
Claims (8)
- A kind of 1. method for being used in optimizing press trench grate MOS processing technology, it is characterised in that the minimum lithographic number of plies of this method It is trench lithography, contact hole photoetching, metal layer lithography respectively for 3 layers；The trench lithography, defined simultaneously by one layer of photoetching Go out groove figure and body injection figures, the body injections figure includes protection ring structure；This method specifically comprises the following steps：Step 1, the hard mask growth of groove, trench lithography, the hard mask etching of groove；The figure that the trench lithography is opened at least wraps Include two kinds of line widths a, b, a>B, size is smaller only as body, source injection figure wherein at b, the larger both conducts of size at a Body, source inject figure, again as the figure for defining etching groove；Step 2, body injects, body annealing；Step 3, source injects, source annealing；Step 4, groove is silica-filled；Step 5, groove silica is etched back to；Step 6, etching groove；Step 7, grid oxic horizon is deposited, and gate polycrystalline silicon deposit, grid polycrystalline silicon is etched back to；Step 8, deielectric-coating ILD is deposited under metal；Step 9, contact hole photoetching, contact hole etching；Step 10, metal growth, photoetching, etching.
- 2. the method as described in claim 1, it is characterised in that the trench lithography, ditch is defined by one layer of photoetching simultaneously Groove figure, body injection figures and the source injection layer patterns of figure three.
- 3. the method as described in claim 1, it is characterised in that in step 1, a sizes be 0.4~1.5 μm, b sizes be 0.1~ 0.5 μm, and a>b.
- 4. the method as described in claim 1, it is characterised in that in step 3, one step of increase before the source injections Source photoetching.
- 5. the method as described in claim 1, it is characterised in that in step 4, the silica-filled technique of groove uses LPCVD or HTO is filled to reach good conformality and is reached different effects at the groove figure of latter two line width, is aoxidized at b Silicon is fully filled with, and concave shape is formed at a.
- 6. method as claimed in claim 5, it is characterised in that in step 4, the thickness of the silica is 1/2b~3/2b.
- 7. the method as described in claim 1, it is characterised in that in step 5, after the groove silica is etched back to, two kinds Reach different effects at the groove figure of line width, being oxidized silicon at b is filled up, and monox lateral wall is formed at a.
- 8. the method as described in claim 1, it is characterised in that in step 5, the etch amount being etched back to is oxygen in step 4 SiClx deposition thickness simultaneously increases by 30% over etching.
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| CN201310661168.2A CN104701174B (en) | 2013-12-09 | 2013-12-09 | Method for pressing trench grate MOS processing technology in optimization |
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| CN104701174B true CN104701174B (en) | 2017-12-05 |
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| CN109545855B (en) * | 2018-11-19 | 2021-09-17 | 中国科学院微电子研究所 | Preparation method of active region of silicon carbide double-groove MOSFET device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5763915A (en) * | 1996-02-27 | 1998-06-09 | Magemos Corporation | DMOS transistors having trenched gate oxide |
| CN102544100A (en) * | 2010-12-14 | 2012-07-04 | 万国半导体股份有限公司 | Self-aligned trench MOSFET with integrated diode |
| CN102569388A (en) * | 2010-12-23 | 2012-07-11 | 无锡华润上华半导体有限公司 | Semiconductor device and manufacturing method thereof |
| CN102842611A (en) * | 2012-08-24 | 2012-12-26 | 中国电力科学研究院 | Five-mask insulated gate bipolar transistor (IGBT) chip and manufacturing method thereof |
-
2013
- 2013-12-09 CN CN201310661168.2A patent/CN104701174B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5763915A (en) * | 1996-02-27 | 1998-06-09 | Magemos Corporation | DMOS transistors having trenched gate oxide |
| CN102544100A (en) * | 2010-12-14 | 2012-07-04 | 万国半导体股份有限公司 | Self-aligned trench MOSFET with integrated diode |
| CN102569388A (en) * | 2010-12-23 | 2012-07-11 | 无锡华润上华半导体有限公司 | Semiconductor device and manufacturing method thereof |
| CN102842611A (en) * | 2012-08-24 | 2012-12-26 | 中国电力科学研究院 | Five-mask insulated gate bipolar transistor (IGBT) chip and manufacturing method thereof |
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