CN104424124A - Memory device, electronic equipment and method for controlling memory device - Google Patents
Memory device, electronic equipment and method for controlling memory device Download PDFInfo
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Abstract
The invention provides a memory device, electronic equipment and a method for controlling the memory device. The memory device comprises a block storage unit, a mapping control unit, a cache unit and a memory interface, wherein the block storage unit comprises a plurality of storage blocks; each storage block comprises a plurality of pages; the block storage unit is used for executing the read-write of data by taking the pages as units; the mapping control unit is used for receiving a command of executing the read-write of the data, establishing a mapping relationship between a memory address of the data to be read-written and a storage address of the data in the block storage unit, and controlling the read-write of the data based on the mapping relationship; the cache unit is used for caching the data to be read-written according to the control of the mapping control unit, thereby executing the data read-write of the block storage unit by taking the pages as units; the memory interface is used for connecting the mapping control unit and the cache unit to a processing unit. According to the technical scheme, the cost of the memory device can be lowered, memory capacity can be truly reflected to a user, and increase of a processing load is avoided.
Description
Technical field
The present invention relates to areas of information technology, more specifically, relate to a kind of memory device, comprising the electronic equipment of this memory device and the method for controlling described memory device.
Background technology
Internal memory is the important component part of electronic equipment.Computing machine for electronic equipment, the data that internal memory is used for temporarily depositing operational data in CPU (central processing unit) (CPU) and exchanges with the external memory storage such as hard disk.When computer run, CPU will carry out computing needing the data of computing to be transferred in internal memory, and after computing completes, result sends out by CPU again.Therefore, the performance of internal memory is very large on the impact of computing machine.
In existing technology, use the various storage unit developed based on random-access memory (ram) as internal memory, but should be expensive based on the DRAM price of random access memory, make the cost of electronic equipment higher.In addition, a kind of virtual memory techniques is also there is to improve internal memory performance in prior art, this virtual memory techniques sets up paging file (paging file) in the external memory storage of electronic equipment, and by utilizing CPU to control to exchange at the page of internal memory and external memory storage to be stored in described paging file by the partial data in internal memory, to extend the capacity of internal memory.But this virtual memory techniques adds the process load of CPU, and be not calculated as the capacity of internal memory due to the capacity of the paging file in external memory storage, therefore the visible memory size of user is lower than the actual measured results of internal memory.
Therefore, expect to there is a kind of low cost, the visible jumbo internal memory of user, and wish that it does not increase the process load of CPU.
Summary of the invention
Embodiments providing a kind of memory device, comprising the electronic equipment of this memory device and the method for controlling described memory device, its can reduce memory device cost, reflect memory size to user and do not increase process load truly.
On the one hand, provide a kind of memory device, for comprising the electronic equipment of processing unit, this processing unit is connected to this memory device, this memory device can comprise: block storage unit, comprise multiple storage block, each storage block comprises multiple page, and this block storage unit performs the read-write of data in units of the page; Mapping control unit, receives the order of the read-write for performing data, and sets up mapping relations between the memory address of the data that will read and write and its storage address in memory device, and based on the read-write of this mapping relations control data; Buffer unit, carrys out according to the control of mapping control unit the data that buffer memory will read and write, thus in units of the page, performs the reading and writing data of described piece of storage unit; Memory interface, for described mapping control unit and buffer unit are connected to described processing unit, to transmit order and the data of described processing unit.
In described memory device, described mapping control unit can comprise: static RAM, for preserving described mapping relations, thus improves the control efficiency of this mapping control unit.
In described memory device, described buffer unit can be cache memory.
In described memory device, described mapping control unit can when receiving the order for reading data, first determine whether in the cache the data that will read, if at cache memory, the data that will read described in then obtaining from cache memory, to send out via memory interface.
In described memory device, described buffer unit can be the cache memory utilizing a part for dynamic RAM to be formed, the remainder of this dynamic RAM, by the additional memory unit as described memory device, carries out reading and writing data to cooperate with described piece of storage unit.
In described memory device, described mapping control unit can when receiving the order for reading data, first determine the data that will read whether in described additional memory unit, if the data read are in described additional memory unit, then from this additional memory unit, obtain the data that will read; If the data read are not in described additional memory unit, then determine whether in the cache the data that will read, if at cache memory, then the data that will read described in obtaining from cache memory, to send out via memory interface.
In described memory device, described piece of storage unit can be made based on optimization flash memory, and the read or write speed of this optimization flash memory is greater than single layer cell flash memory, and its erasable number of times is greater than single layer cell flash memory.
On the other hand, provide a kind of electronic equipment, it comprises processing unit and any one memory device as above.
On the other hand, provide a kind of method for controlling memory device, described memory device can comprise block storage unit, memory interface, with this block storage unit with the use of buffer unit, described piece of storage unit comprises multiple storage block, each storage block comprises multiple page, this block storage unit performs the read-write of data in units of the page, this memory interface is used for described memory device to be connected to processing unit, described method can comprise: between the memory address and the data that will the read and write storage address in internal storage location of the data for reading and writing, set up mapping relations, receive the order of the read-write for performing data from processing unit via described memory interface, this order comprises the memory address for the data that will read and write, the storage address of the data that will read and write is determined based on described mapping relations, the described read-write of data in described storage address that will read and write is performed via described memory interface, wherein, when determined storage address is described piece of access unit address, perform the described read-write of data in described storage address that will read and write by means of described buffer unit.
For controlling in the method for memory device, described memory device also can comprise: static RAM described, for storing the mapping relations between described memory address and described storage address, thus improves and utilizes these mapping relations to carry out the efficiency operated.
Described for controlling in the method for memory device, described buffer unit can be cache memory.
Described for controlling in the method for memory device, when receiving the read command for reading data from described processing unit, describedly determine that based on described mapping relations the step of the storage address of the data that will read and write can comprise: first determine whether in the cache the data that will read; If the data read not in the cache, then determine that the data that will read are in described piece of storage unit, and the storage address of data in described piece of storage unit will read described in obtaining.The described step performing the described read-write of data in described storage address that will read and write via described memory interface can comprise: if determine that the data that will read in the cache, the data that will read described in then obtaining from cache memory, and send out via memory interface.
Described for controlling in the method for memory device, described buffer unit can be the cache memory utilizing a part for dynamic RAM to be formed, the remainder of this dynamic RAM, by the additional memory unit as described memory device, carries out reading and writing data to cooperate with described piece of storage unit.
Described for controlling in the method for memory device, when receiving the read command for reading data from described processing unit, describedly determine that based on described mapping relations the step of the storage address of the data that will read and write can comprise: determine the data that will read whether in described additional memory unit based on described mapping relations; If the data read are not in described additional memory unit, then determine whether in the cache the data that will read; If the data read not in the cache, then determine that the data that will read are in described piece of storage unit.The described step performing the described read-write of data in described storage address that will read and write via described memory interface can comprise: if determine that the data that will read are in described additional memory unit, the data that will read described in then obtaining from described additional memory unit, and send out via memory interface; If determine that the data that will read in the cache, then the data that will read described in obtaining from cache memory, and send out via memory interface.
Described for controlling in the method for memory device, described piece of storage unit can be made based on optimization flash memory, and the read or write speed of this optimization flash memory is greater than single layer cell flash memory, and its erasable number of times is greater than single layer cell flash memory.
The embodiment of the present invention memory device, comprise this memory device electronic equipment and for control described memory device method in, the cost of memory device can be reduced by utilizing block storage unit to form internal storage location, memory size can be reflected to user truly by docking with outside via memory interface, and not increase process load by the maintenance performing mapping relations in memory device.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the block diagram of the memory device schematically illustrated according to the embodiment of the present invention;
Fig. 2 is the block diagram schematically illustrating memory device according to another embodiment of the present invention;
Fig. 3 is the block diagram of the electronic equipment schematically illustrated according to the embodiment of the present invention;
Fig. 4 is the process flow diagram of the method for controlling memory device schematically illustrated according to the embodiment of the present invention;
Fig. 5 schematically illustrates the process flow diagram for controlling operation performed when receiving read command in the method for memory device according to the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.
Fig. 1 is the block diagram of the memory device 100 schematically illustrated according to the embodiment of the present invention.This memory device 100 can be applicable to various electronic equipment, include but not limited to intelligent telephone set, computing machine, personal digital assistant, Website server, bibliographic data base or data storage server etc., the particular type of electronic equipment is not construed as limiting the invention.Typically, this electronic equipment can comprise the processing unit of such as central processing unit and so on, thus sends various order to memory device 100 and carry out data transmission with memory device 100.
Described memory device 100 can comprise: block storage unit 110, comprises multiple storage block, and each storage block comprises multiple page, and this block storage unit performs the read-write of data in units of the page; Mapping control unit 120, receives the order of the read-write for performing data, and sets up mapping relations between the memory address of the data that will read and write and its storage address in memory device, and based on the read-write of this mapping relations control data; Buffer unit 130, carrys out according to the control of mapping control unit the data that buffer memory will read and write, thus in units of the page, performs the reading and writing data of described piece of storage unit; Memory interface 140, for described mapping control unit and buffer unit are connected to described processing unit, to transmit order and the data of described processing unit.
Described piece of storage unit 110 typically is solid state hard disc, and is described for solid state hard disc below.But the example of solid state hard disc only described piece of storage unit 110, can not as the restriction to the embodiment of the present invention, and any storage medium with the attribute of described herein piece of storage unit can as block storage unit 110.Solid state hard disc comprises multiple storage block, and each storage block comprises multiple page, and each page generally includes multiple byte.In units of the page, the read-write of data is performed in solid state hard disc.Solid state hard disc is often used as the hard disk of electronic equipment, and its price is well below internal memory.Therefore, the block storage unit of such as solid state hard disc is utilized can to reduce the price of memory device widely as the main memory unit of memory device 100.
Solid state hard disc is typically made up of control module and storage medium, and this storage medium is such as flash memory (Flash) or dynamic RAM.Along with the development of technology, the performance of solid state hard disc is also constantly upgraded.Such as develop now a kind of optimization flash memory, the read or write speed of this optimization flash memory is greater than single layer cell flash memory, and its erasable number of times is greater than single layer cell flash memory.Therefore, based on optimizing described piece of storage unit 110 making of flash memory for having more excellent performance during memory device 100.
Described mapping control unit 120 such as receives the order of the read-write for performing data from processing unit, such as the data that will read and write specify the memory address in memory device in this order, memory address specified by this processing unit is normally according to the address that more general mechanism is arranged, and it typically is logical address.But the storage address of data in memory device is the concrete address storing the position of data in memory device, and it is such as physical address.Described memory address is usually different from described storage address, and therefore needs to set up mapping relations between, thus from memory device, reads data according to the instruction of reading of processing unit and write data according to the write command of processing unit to memory device.
Because the capacity of memory device 100 is increasing gradually, the process complexity of processing unit is also rising gradually, so the described mapping relations also relative complex that this mapping control unit 120 develops and manages.And in the memory device of existing such as random access memory, carry out the read-write of data in units of byte, namely the read write command of processing unit is in units of byte; But in an embodiment of the present invention, block storage unit 110 is performed to the read-write of data in units of the page, this also further increases the maintenance difficulties of mapping control unit 120 for described mapping relations.In order to improve the control efficiency of this mapping control unit 120, described mapping control unit can comprise static RAM, for preserving described mapping relations.Static RAM has the read or write speed of very block, and its content can arbitrarily read as required or write, and the position of the speed of read-write and storage unit has nothing to do.Therefore, this mapping control unit 120 can utilize described static RAM to assist management the mapping relations between memory address and storage address, thus improves control efficiency.
After the read/write address having known the data that will read and write according to the instruction of processing unit, know the storage address of data in memory device that will read and write based on described mapping relations, thus perform reading and writing data in described storage address.About the concrete operations performing read-write, further describe below in conjunction with buffer unit 130.
The data that buffer unit 130 will be read and write for carrying out buffer memory according to the control of mapping control unit, thus in units of the page, perform the reading and writing data of described piece of storage unit.As previously mentioned, in existing memory device, carry out the read-write of data in units of byte, namely the read write command of processing unit is in units of byte; But, in an embodiment of the present invention, block storage unit 110 is performed to the read-write of data in units of the page, and each page generally includes multiple byte.That is, the reading and writing data granularity of block storage unit 110 is greater than the operation granularity of existing processing unit.Therefore, this buffer unit 130 is utilized to realize the read-write of data to assist described piece of storage unit 110.Described buffer unit 130 cache memory is typically such as dynamic RAM (DRAM), read-only storage able to programme (PROM) etc.
When receiving the digital independent in units of byte from processing unit, mapping control unit 120 controls as follows, in units of the page by the digital independent that will read that is kept in block storage unit in described buffer unit 130, the byte required for processing unit is determined, determined byte to be read away from the data of buffer memory in units of the page.When receiving the write of the data in units of byte from processing unit, mapping control unit 120 controls as follows, first determine that corresponding with the data that will write take the page as the storage address of unit, each page of this storage address can store the data of partial bytes usually; Be that unit reads in described buffer unit 130 with the page by the content in determined storage address; The byte that will write is written in buffer unit 130; Be written in block storage unit 110 by the data in buffer unit 130 in units of the page, these data comprise the data originally stored at the page and the data write afterwards.In addition, if do not have data in each page of the storage address corresponding with the data that will write, the data that mapping control unit 120 also can write directly write in block storage unit 110.As can be seen here, although the read write command that memory device receives reads and writes in units of byte, utilize this buffer unit 130 also can realize read-write in the block storage unit 110 in units of the page.
According to above about the description of buffer unit 130, the minimum capacity of this buffer unit 130 is pages in block storage unit 110.In use, if the capacity of buffer unit 130 is large, then once can performs the read-write of multiple page, thus improve the operating efficiency of internal memory.When the capacity of buffer unit 130 is larger, partial data, while being written to block storage unit 110, also may be retained in described buffer unit 130.Correspondingly, when reading data, described mapping control unit 120 first can determine the data that will read whether in buffer unit 130, if at buffer unit 130, then the data that will read described in obtaining from buffer unit 130 are to send out; If the data read are not at buffer unit 130, then buffer unit 130 is utilized from block storage unit 110, to obtain the described data that will read to send out as mentioned above.Like this, the data storage capacities that buffer unit 130 is existing can be utilized fully, improve the read-write efficiency of memory device 100.
Described memory interface 140 for described mapping control unit 120 and buffer unit 130 are connected to described processing unit, to transmit order and the data of described processing unit.As previously mentioned, although the read write command that memory device receives reads and writes in units of byte, utilize this buffer unit can realize read-write in the block storage unit in units of the page.That is, existing processing unit is without any need for change, and existing various memory interface correspondingly can be utilized as the memory interface 140 in the embodiment of the present invention.For user, the capacity of this memory device 100 can be presented truly to it by this memory interface.When all told of described buffer unit 130 is used to the data of cache blocks storage unit 110, this is the capacity of block storage unit 110 to the capacity that user presents; When the portion capacity of described buffer unit 130 is used to the data of cache blocks storage unit 110, this to the capacity that the capacity that user presents is block storage unit 110 add in buffer unit 130 except described for the residual capacity except the portion capacity of buffer memory.
In the technical scheme of the memory device of the embodiment of the present invention, the cost of memory device can be reduced by utilizing block storage unit to form internal storage location, memory size can be reflected to user truly by docking with outside via memory interface, and not increase process load by performing the maintenance of mapping relations in inside.
In order to disclose embodiments of the invention more fully, other structured flowchart of memory device is described below in conjunction with Fig. 2.Fig. 2 is the block diagram schematically illustrating memory device 200 according to another embodiment of the present invention.
In fig. 2, identical Reference numeral is employed to represent the component units identical with Fig. 1.Block storage unit 110 in Fig. 2, mapping control unit 120, buffer unit 130, memory interface 140 are identical with the corresponding part in Fig. 1, and the descriptions thereof are omitted here.The memory device 200 of Fig. 2 is to add additional memory unit 150 with the difference of the memory device 100 of Fig. 1.This additional memory unit 150 can utilize existing various memory part to be formed, can be such as Synchronous Dynamic Random Access Memory (SDRAM), double data rate random access memory (DDR SDRAM) etc., the type of this additional memory unit 150 form the restriction to the embodiment of the present invention.Under the control of mapping control unit 120, this additional memory unit 150 can carry out the read-write process of data at high speed as existing internal memory.
Increasing this additional memory unit 150 is read-write operations in order to further optimization data.In the operating process of existing electronic equipment, the capacity of required memory device is the process of a dynamic change, and such as, for the regular job of electronic equipment, it only may need the memory size of 1 gigabyte (GB); But, when utilizing electronic equipment to play games, the even more memory size of 3GB may be needed.As previously mentioned, usually will process via buffer unit 130 when utilizing block storage unit 110 to read and write, this reduces the read or write speed of data to a certain extent, although this reduction is limited.Here, described additional memory unit 150 is comprised to meet the routine request of processing unit at memory device 200.That is, in required memory size hour, utilize this additional memory unit 150 in memory device 200 to carry out the read-write of data; When required memory size becomes large, utilize both this additional memory unit 150 in memory device 200 and block storage unit 110 to carry out the read-write of data, thus while adding the capacity of memory device, also ensure that the operating performance of memory device.
This additional memory unit 150 can be independent memory devices, can also with described buffer unit 130 shared drive device.Such as, described buffer unit 130 can be the cache memory utilizing a part for dynamic RAM to be formed, and using the described additional memory unit 150 of the remainder of this dynamic RAM as memory device, carry out reading and writing data to cooperate with described piece of storage unit 110.In addition, when carrying out the read-write of data, preferentially utilize additional memory unit 150, and when this additional memory unit 150 does not have free space, make described buffer unit 130 and block storage unit 110 to carry out the read-write of data.Exemplarily, when receiving the order for reading data, first described mapping control unit determines the data that will read whether in described additional memory unit 150 120, if the data read are in described additional memory unit 150, from this additional memory unit 150, then obtain the data that will read, to send out via memory interface; If the data read are not in described additional memory unit 150, then determine the data that will read whether in cache memory 130, if at cache memory 130, then the data that will read described in obtaining from cache memory, to send out via memory interface.If the data read are not in cache memory 130, then can determine that these data that will read are in block storage unit 110, and the data that will read described in obtaining from described piece of storage unit 110, to send out via memory interface.
In the memory device shown in Fig. 2, by mixedly configuring and using dissimilar storage unit, comprise described additional memory unit 150 and block storage unit 110, the cost of memory device can be reduced while the performance ensureing internal memory, reflect memory size to user and do not increase process load truly.
Each memory device that composition graphs 1 and Fig. 2 describe above can be used in various types of electronic equipment.Correspondingly, the electronic equipment comprising any one memory device above-mentioned is also all in the open scope of the embodiment of the present invention.Fig. 3 is the block diagram of the electronic equipment schematically illustrated according to the embodiment of the present invention.As shown in Figure 3, this electronic equipment comprises processing unit and any one memory device as above.Utilize the memory device in this electronic equipment, the cost of memory device can be reduced equally, reflect memory size to user and do not increase the process load of processing unit truly.
Fig. 4 is the process flow diagram of the method 400 for controlling memory device schematically illustrated according to the embodiment of the present invention.Described memory device can comprise block storage unit, memory interface, with this block storage unit with the use of buffer unit.Described piece of storage unit can comprise multiple storage block, and each storage block comprises multiple page, and this block storage unit performs the read-write of data in units of the page, and this memory interface is used for described memory device to be connected to processing unit.Described memory device is used for temporarily preserving program, data etc. needed for running in the operational process of electronic equipment.The particular type of electronic equipment is not construed as limiting the invention.
Described piece of storage unit typically is solid state hard disc, can also be other storage medium any of the attribute with described herein piece of storage unit.Here be described for solid state hard disc.The price of solid state hard disc is well below internal memory.Therefore, the block storage unit of such as solid state hard disc is utilized can to reduce the price of memory device widely as the main memory unit of memory device.Solid state hard disc is typically made up of control module and storage medium, and this storage medium is such as flash memory or dynamic RAM.Along with the development of technology, the performance of solid state hard disc is also constantly upgraded.Such as develop now a kind of optimization flash memory, the read or write speed of this optimization flash memory is greater than single layer cell flash memory, and its erasable number of times is greater than single layer cell flash memory.Therefore, based on optimizing described piece of storage unit making of flash memory for having more excellent performance during memory device.
Buffer unit is used for the data that buffer memory will be read and write, thus in units of the page, perform the reading and writing data of described piece of storage unit.In existing memory device, in units of byte, carry out the read-write of data; But, in an embodiment of the present invention, in units of the page, carry out read-write block storage unit being performed to data, and each page generally includes multiple byte.That is, the reading and writing data granularity of block storage unit is greater than the operation granularity of existing processing unit.Therefore, this buffer unit is utilized to realize the read-write of data to assist described piece of storage unit.Described buffer unit cache memory is typically such as dynamic RAM (DRAM), read-only storage able to programme (PROM) etc.In addition, a part for dynamic RAM can be utilized to form described buffer unit, and using the additional memory unit of the remainder of this dynamic RAM as described memory device, carry out reading and writing data to cooperate with described piece of storage unit.
Described memory interface is the external connecting interface of memory device, for order and data between memory device and the parts of its outside.As previously mentioned, although the read write command that memory device receives reads and writes in units of byte, but utilize this buffer unit can realize read-write in the block storage unit in units of the page, existing processing unit, without any need for change, correspondingly can utilize existing various memory interface as described memory interface.The capacity of this memory device can be presented truly to user by this memory interface.Process flow diagram below in conjunction with Fig. 4 and Fig. 5 describes the operation of memory device.
As shown in Figure 4, the described method 400 for controlling memory device can comprise: between the memory address and the data that will the read and write storage address in internal storage location of the data for reading and writing, set up mapping relations (S410); Receive the order of the read-write for performing data from processing unit via described memory interface, this order comprises the memory address (S420) for the data that will read and write; The storage address (S430) of the data that will read and write is determined based on described mapping relations; The described read-write of data in described storage address that will read and write is performed via described memory interface, wherein, when determined storage address is described piece of access unit address, perform the described read-write (S440) of data in described storage address that will read and write by means of described buffer unit.
In S410, between the memory address and the data that will the read and write storage address in internal storage location of the data for reading and writing, set up mapping relations.This memory address being used for the data that will read and write is such as specified by the processing unit communicated with memory interface, it is such as included in the order of the read-write for performing data received from processing unit, this memory address is normally according to the address that more general mechanism is arranged, and it typically is logical address.But the storage address of data in memory device is the concrete address storing the position of data in memory device, and it is such as the physical address of data in block storage unit or buffer unit that will read and write.This storage address is different from described memory address, and therefore needs to set up mapping relations between, thus from memory device, reads data according to the instruction of reading of data and write data according to the write command of processing unit to memory device.
Because the capacity of memory device is increasing gradually, the process complexity of processing unit is also rising gradually, so the described mapping relations also relative complex developed and managed.And in the memory device of existing such as random access memory, carry out the read-write of data in units of byte, namely the read write command of processing unit is in units of byte; But in an embodiment of the present invention, carry out read-write block storage unit being performed to data in units of the page, this also further increases the maintenance difficulties of described mapping relations.In order to the operating efficiency improved, described memory device can comprise static RAM, for preserving described mapping relations.Static RAM has the read or write speed of very block, and its content can arbitrarily read as required or write, and the position of the speed of read-write and storage unit has nothing to do.Therefore, described memory device can utilize described static RAM to assist management the mapping relations between memory address and storage address, thus improves operating efficiency.Here static RAM is only schematic, can also take described mapping relations such as the storage of dynamic RAM etc.
In S420, receive the order of the read-write for performing data from processing unit via described memory interface, this order comprises the memory address for the data that will read and write.As previously mentioned, existing various memory interface can be utilized as required as described memory interface, namely processing unit that is existing and described memory interface does not need to change, thus has good compatibility.Described in receiving from processing unit via memory interface for the memory address of data that will read and write normally according to the address that more general mechanism is arranged, it typically is logical address.This memory address is the memory address that processing unit is understood.
In S430, determine the storage address of the data that will read and write based on described mapping relations.After the read/write address having known the data that will read and write according to the instruction of processing unit, know the storage address of data in memory device that will read and write based on described mapping relations, thus perform reading and writing data in described storage address.This storage address can be to read and write the address of data in block storage unit, also can be the described address of the data that will read and write in buffer unit.
In S440, the described read-write of data in described storage address that will read and write is performed via described memory interface, wherein, when determined storage address is described piece of access unit address, perform the described read-write of data in described storage address that will read and write by means of described buffer unit.S430 and S440 is described be combineding with each other below, more clearly the present invention to be described.
As previously mentioned, buffer unit is used for temporarily storing the data will read and write in block storage unit, and cooperate with block storage unit the read-write realized in units of the page in block storage unit.Particularly, when receiving the digital independent in units of byte from processing unit, the storage address determining the data that will read in S430 is block access unit address, then in S440, the data that will read be kept in block storage unit are stored in described buffer unit in units of the page, from the data of buffer memory in units of the page, determine the byte required for processing unit, and determined byte is read away.When receiving the write of the data in units of byte from processing unit, in S430, determine that the storage address corresponding with the data that will write is such as block access unit address according to mapping relations; Be then that unit reads in described buffer unit with the page by the content in determined storage address in S440, the byte that will write is written to the correspondence position in buffer unit, then be written in block storage unit by the data in buffer unit in units of the page, these data comprise the data originally stored at the page and the data write afterwards.In addition, in S440, if do not have data in each page of the storage address corresponding with the data that will write, the data that also can write directly write in block storage unit.Visible, the minimum capacity of this buffer unit is a page of block storage unit.
In use, if the capacity of buffer unit is large, then once can performs the read-write of multiple page, thus improve the operating efficiency of internal memory.When the capacity of buffer unit is larger, partial data, while being written to block storage unit, may also be retained in described buffer unit.Correspondingly, when reading data, first can determine the data that will read in this S430 whether in buffer unit, if at the buffer unit of such as cache memory, then the data that will read described in obtaining from buffer unit in S440 are to send out; In S430, if the data read are not at buffer unit, then can determine that the data that will read are in described piece of storage unit, and determine the storage address of data in described piece of storage unit that will read, thus the data that will read described in obtaining from block storage unit in S440 are to send out.Like this, the data storage capacities that can buffer unit be utilized fully existing, improves the read-write efficiency of memory device.
In addition, additional memory unit can be increased in internal memory.This additional memory unit can utilize existing various memory part to be formed, and can be such as SDRAM, DDR SDRAM etc., the type of this additional memory unit form the restriction to the embodiment of the present invention.This additional memory unit can carry out the read-write process of data at high speed as existing internal memory.Increasing this additional memory unit is read-write operation in order to further optimization data.As previously mentioned, utilize block storage unit can provide jumbo internal memory with low cost, but usually will process via buffer unit when utilizing block storage unit to read and write, this reduces the read or write speed of data to a certain extent, although this reduction is limited.In the operating process of existing electronic equipment, the capacity of required memory device is the process of a dynamic change.Therefore, in required memory size hour, utilize this additional memory unit in memory device to carry out the read-write of data; When required memory size becomes large, utilize both this additional memory unit in memory device and block storage unit to carry out the read-write of data, thus while adding the capacity of memory device, also ensure that the operating performance of memory device.
This additional memory unit can be independent memory devices, also can with described buffer unit shared drive device.Such as, described buffer unit can be the cache memory utilizing a part for dynamic RAM to be formed, and using the described additional memory unit of the remainder of this dynamic RAM as memory device, carry out reading and writing data to cooperate with described piece of storage unit.Be described below in conjunction with Fig. 5.Fig. 5 schematically illustrates the process flow diagram for controlling operation performed when receiving read command in the method for memory device according to the embodiment of the present invention.
Exemplarily, when receiving the order for reading data, first the data that will read are determined whether in described additional memory unit in S431, if the data read (being in S431) in described additional memory unit, in S441, from this additional memory unit, then obtain the data that will read, to send out via memory interface; If the data read are (no in S431) not in described additional memory unit, in S432, then determine whether in the cache the data that will read, if at cache memory (being in S432), the data that will read described in then obtaining from cache memory in S442, to send out via memory interface; If the data read are (no in S432) not in the cache, then can determine that these data that will read are in block storage unit, and obtain the storage address (S443) of these data that will read in block storage unit, the data that will read described in reading from obtained storage address, send out (S444) via memory interface to utilize buffer unit.Here, S431, S432 are each sub-steps in step S430, and S441, S442, S443, S444 are each sub-steps in step S440.In the process flow diagram shown in Fig. 5, by mixedly configuring and using dissimilar storage unit, comprise described additional memory unit and block storage unit, the cost of memory device can be reduced while the performance ensureing internal memory.
When all told of described buffer unit is used to the data of cache blocks storage unit, this is the capacity of block storage unit to the capacity that user presents; When the portion capacity of described buffer unit is used to the data of cache blocks storage unit, this to the capacity that the capacity that user presents is block storage unit add in buffer unit except described for the residual capacity except the portion capacity of buffer memory.Certainly, when memory device also comprises additional memory unit, its memory size also will add the capacity of described additional memory unit.
In the technical scheme of the method for controlling memory device of the embodiment of the present invention, the cost of memory device can be reduced by utilizing block storage unit to form internal storage location, memory size can be reflected to user truly by docking with outside via memory interface, and not increase process load by performing the maintenance of mapping relations in inside.
Those skilled in the art can be well understood to, the embodiment of the method for foregoing description be applied to the structure of memory device, can illustrate and diagram with reference to the correspondence in before-mentioned products embodiment; The equipment of foregoing description and the specific works process of unit, can corresponding process in reference method embodiment.
In several embodiments that the application provides, should be understood that disclosed apparatus and method can realize by another way.Such as, device embodiment described above is only schematic, such as, the division of described unit, be only a kind of logic function to divide, actual can have other dividing mode when realizing, such as multiple unit or assembly can in conjunction with or another system can be integrated into, or some features can be ignored, or do not perform.In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, also can be that the independent physics of unit exists, also can two or more unit in a unit integrated.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should described be as the criterion with the protection domain of claim.
Claims (15)
1. a memory device, for comprising the electronic equipment of processing unit, this processing unit is connected to this memory device, and this memory device comprises:
Block storage unit, comprises multiple storage block, and each storage block comprises multiple page, and this block storage unit performs the read-write of data in units of the page;
Mapping control unit, receives the order of the read-write for performing data, and sets up mapping relations between the memory address of the data that will read and write and its storage address in memory device, and based on the read-write of this mapping relations control data;
Buffer unit, carrys out according to the control of mapping control unit the data that buffer memory will read and write, thus in units of the page, performs the reading and writing data of described piece of storage unit;
Memory interface, for described mapping control unit and buffer unit are connected to described processing unit, to transmit order and the data of described processing unit.
2. memory device according to claim 1, wherein, described mapping control unit comprises: static RAM, for preserving described mapping relations, thus improves the control efficiency of this mapping control unit.
3. memory device according to claim 1, wherein, described buffer unit is cache memory.
4. memory device according to claim 3, wherein, described mapping control unit is when receiving the order for reading data, first determine whether in the cache the data that will read, if at cache memory, the data that will read described in then obtaining from cache memory, to send out via memory interface.
5. memory device according to claim 1, wherein, described buffer unit is the cache memory utilizing a part for dynamic RAM to be formed, the remainder of this dynamic RAM, by the additional memory unit as described memory device, carries out reading and writing data to cooperate with described piece of storage unit.
6. memory device according to claim 5, wherein, described mapping control unit is when receiving the order for reading data, first determine the data that will read whether in described additional memory unit, if the data read are in described additional memory unit, then from this additional memory unit, obtain the data that will read; If the data read are not in described additional memory unit, then determine whether in the cache the data that will read, if at cache memory, then the data that will read described in obtaining from cache memory, to send out via memory interface.
7. memory device according to claim 1, wherein, described piece of storage unit is made based on optimization flash memory, and the read or write speed of this optimization flash memory is greater than single layer cell flash memory, and its erasable number of times is greater than single layer cell flash memory.
8. an electronic equipment, comprising:
Processing unit; With
Memory device according to any one of claim 1 to 7.
9. one kind for controlling the method for memory device, described memory device comprise block storage unit, memory interface, with this block storage unit with the use of buffer unit, described piece of storage unit comprises multiple storage block, each storage block comprises multiple page, this block storage unit performs the read-write of data in units of the page, this memory interface is used for described memory device to be connected to processing unit, and described method comprises:
Mapping relations are set up between the memory address and the data that will the read and write storage address in internal storage location of the data for reading and writing;
Receive the order of the read-write for performing data from processing unit via described memory interface, this order comprises the memory address for the data that will read and write;
The storage address of the data that will read and write is determined based on described mapping relations;
The described read-write of data in described storage address that will read and write is performed via described memory interface,
Wherein, when determined storage address is described piece of access unit address, perform the described read-write of data in described storage address that will read and write by means of described buffer unit.
10. method according to claim 9, wherein, described memory device also comprises:
Static RAM, for storing the mapping relations between described memory address and described storage address, thus raising utilizes these mapping relations to carry out the efficiency operated.
11. methods according to claim 9, wherein, described buffer unit is cache memory.
12. methods according to claim 11, wherein, when receiving the read command for reading data from described processing unit, describedly determine that based on described mapping relations the step of the storage address of the data that will read and write comprises:
First determine whether in the cache the data that will read;
If the data read not in the cache, then determine that the data that will read are in described piece of storage unit, and the storage address of data in described piece of storage unit will read described in obtaining,
Wherein, the described step performing the described read-write of data in described storage address that will read and write via described memory interface comprises: if determine that the data that will read in the cache, the data that will read described in then obtaining from cache memory, and send out via memory interface.
13. methods according to claim 9, wherein, described buffer unit is the cache memory utilizing a part for dynamic RAM to be formed, the remainder of this dynamic RAM, by the additional memory unit as described memory device, carries out reading and writing data to cooperate with described piece of storage unit.
14. methods according to claim 13, wherein, when receiving the read command for reading data from described processing unit, describedly determine that based on described mapping relations the step of the storage address of the data that will read and write comprises:
The data that will read are determined whether in described additional memory unit based on described mapping relations;
If the data read are not in described additional memory unit, then determine whether in the cache the data that will read;
If the data read not in the cache, then determine that the data that will read are in described piece of storage unit, and the storage address of data in described piece of storage unit will read described in obtaining,
Wherein, the described step performing the described read-write of data in described storage address that will read and write via described memory interface comprises: if determine that the data that will read are in described additional memory unit, the data that will read described in then obtaining from described additional memory unit, and send out via memory interface; If determine that the data that will read in the cache, then the data that will read described in obtaining from cache memory, and send out via memory interface.
15. methods according to claim 9, wherein, described piece of storage unit is made based on optimization flash memory, and the read or write speed of this optimization flash memory is greater than single layer cell flash memory, and its erasable number of times is greater than single layer cell flash memory.
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