CN103762962A - Pre-amplifying latch comparator with low detuning - Google Patents
Pre-amplifying latch comparator with low detuning Download PDFInfo
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- CN103762962A CN103762962A CN201410001389.1A CN201410001389A CN103762962A CN 103762962 A CN103762962 A CN 103762962A CN 201410001389 A CN201410001389 A CN 201410001389A CN 103762962 A CN103762962 A CN 103762962A
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Abstract
The invention discloses a pre-amplifying latch comparator with low detuning. The pre-amplifying latch comparator with the low detuning comprises a base pre-amplifying latch comparator, a detuning compensation geminate transistor, a detuning calibration switch and a detuning calibration control circuit. The base pre-amplifying latch comparator comprises a primary pre-amplifier and a secondary latch. The detuning compensation geminate transistor comprises a detuning adjusting transistor, the detuning adjusting transistor is connected to the output end of the pre-amplifier in parallel, and the detuning voltage of the whole comparator is regulated by changing a grid voltage of the detuning adjusting transistor. A digital bidirectional shifter is adopted by the detuning calibration control circuit to store detuning information and control the detuning calibration control circuit to carry out detuning calibration. According to the pre-amplifying latch comparator with the low detuning, the detuning calibration control circuit based on digital storage and control is added based on an existing pre-amplifying latch comparator, the detuning of the pre-amplifying latch comparator can be reduced to one nth of original detuning, and the pre-amplifying latch comparator after calibration reduces the detuning greatly.
Description
Technical field
The present invention relates to a kind of Preamplifier-latch comparator of low imbalance, belong to comparator technology.
Background technology
Comparator is converted into digital signal by input analog signal, is an important interface of analog to digital, is widely used in analog to digital converter, the circuit such as digital to analog converter.Wherein Preamplifier-latch comparator is because prime amplifier can amplify input analog signal, isolation output numeral affects input signal, and relatively the latching fast of latch, with respect to the high-speed slow amplification type comparator of precision, can be good at bringing into play the speed advantage of latch-type comparator, and improve in precision.Thereby Preamplifier-latch comparator is used widely in Practical Project practice.But the develop rapidly along with digital circuit, to analog to digital converter, speed, the required precision of the circuit such as digital to analog converter improve constantly, utilize traditional Preamplifier-latch comparator to be difficult to meet high-precision requirement, therefore the mistuning calibration function of Preamplifier-latch comparator is played an important role in the application of high-speed, high precision.
Traditional mistuning calibration function technology is by capacitance stores, to lack of proper care in comparator work, then prime amplifier is carried out to mistuning calibration function.This method can limit the speed of comparator, and can only calibrate the imbalance of prime amplifier, latch is not carried out to mistuning calibration function.
Summary of the invention
Goal of the invention: in order to overcome the deficiencies in the prior art, the invention provides a kind of Preamplifier-latch comparator of low imbalance, improve the precision of comparator.
Technical scheme: for achieving the above object, the technical solution used in the present invention is:
A kind of Preamplifier-latch comparator of low imbalance, comprise that basic Preamplifier-latch comparator, offset compensation are to pipe, mistuning calibration function switch and mistuning calibration function control circuit, described basic Preamplifier-latch comparator comprises the prime amplifier of the first order, the latch of the second level, described offset compensation comprises imbalance adjustment pipe to pipe, the output that pipe is connected in parallel on prime amplifier is adjusted in described imbalance, the carrier of device offset compensation as a comparison, compensates the offset voltage of comparator by the lack of proper care difference grid voltage of adjusting pipe of change; The enable switch whether described mistuning calibration function switch carries out mistuning calibration function operation as mistuning calibration function control circuit; Described mistuning calibration function control circuit adopts bidirectional shift register, for storing error information and adjusting imbalance and adjust the grid voltage of pipe with the imbalance of compensation comparator.Mistuning calibration function control circuit adopts active device, can guarantee offset compensation after the calibration bias voltage V to pipe
cal_L/ V
cal_Rremain unchanged, while having avoided with electric capacity as the device of storage imbalance, in circuit, MOS leakage current makes the situation of capacity fall off.
Described mistuning calibration function control circuit comprises that offset compensation is adjusted gating switch to pipe biasing circuit, bias adjustment circuit, biasing and control module is adjusted in biasing; Described offset compensation is converted into bias voltage to pipe biasing circuit for the electric current that current source is produced; Described bias adjustment circuit, for generation of adjusting electric current, is adjusted the grid voltage of offset compensation to pipe by offset compensation to pipe biasing circuit; Described biasing is adjusted gating switch and for adjustment current source gating to the offset compensation that bias adjustment circuit is produced, pipe biasing circuit is setovered; Described biasing is adjusted control module and mainly bidirectional shift register, is consisted of, and the current supply switch of bias adjustment circuit is controlled.
Described offset compensation mainly consists of the 20 PMOS pipe M20,21 PMOS pipe M21, the 22 PMOS pipe M22, the 25 NMOS pipe M25 and the 26 NMOS pipe M26 pipe biasing circuit; The 20 PMOS pipe M20 and the 21 PMOS pipe M21 and the 22 PMOS pipe M22 form current mirror; The 25 NMOS pipe M25 and the 26 NMOS pipe M26 connect into diode form as metal-oxide-semiconductor resistance, by the electric current I of being come by current source mirror image
r1be superimposed with the offset current I being produced by imbalance Circuit tuning
cL/ I
cRbe converted into the bias voltage V of offset compensation to pipe
cal_L/ V
cal_R.
Described bias adjustment circuit comprises the adjustment current source of one group of parallel connection, and each adjusts a current supply switch of current source series connection; Each adjusts current source is a PMOS pipe, and each current supply switch is a PMOS pipe; Described the 20 PMOS pipe M20 forms current mirror with adjustment current source.The mistuning calibration function method that the present invention takes can be reduced to offset voltage the 1/N before calibration, and wherein N is for adjusting the quantity of current source.The quantity of adjusting current source depends on the precision that will reach, and the number that increases adjustment current source can improve the precision of mistuning calibration function, and the number that current source is adjusted in corresponding minimizing can reduce the effect that imbalance is proofreaied and correct; The Determines of current supply switch the adjustment current source of connecting whether effective.Design all PMOS pipes as adjusting current source with weight, weight is embodied in the breadth length ratio of PMOS pipe; Add the weight can be so that the whole comparator imbalance voltage of each step is identical, to adjust step-length identical for input offset voltage.
Described biasing is adjusted gating switch and is comprised gating switch control circuit and gating switch main body; Described gating switch control circuit comprises the first set-reset flip-floop SR1, the second rest-set flip-flop SR2, the first inverter N1, the 51 NMOS pipe M51 and the 52 NMOS pipe M52, the first set-reset flip-floop SR1 is comprised of the first NOR gate NOR1 and the second NOR gate NOR2, and the second rest-set flip-flop SR2 is comprised of the 3rd NOR gate NOR3 and four nor gate NOR4; Described gating switch main body comprises an alternative data selector, described data selector mainly consists of the 53 NMOS pipe M53 and the 55 NMOS pipe M55, the 54 NMOS that connects in data selector manages M54 and the 56 NMOS pipe M56, and described the 54 NMOS pipe M54 and the 56 NMOS pipe M56 are as the reset terminal of data selector.
Described biasing is adjusted control module and mainly bidirectional shift register and control circuit thereof, is consisted of, the number of bidirectional shift register equates with the number of current supply switch in bias adjustment circuit, represent that (imbalance after the comparator of establishing N bidirectional shift register is calibrated is a to the precision that imbalance proofreaies and correct, only having the imbalance after the comparator calibration of 1 bidirectional shift register is b, a=1b/N), each bidirectional shift register is controlled a current supply switch, the grid of the output signal access current supply switch of bidirectional shift register; Described bidirectional shift register mainly consists of alternative data selector (can design identical with the data selector structure of setovering in adjustment gating switch) and edge d type flip flop, and the output CONT that adjusts gating switch by biasing controls the first transmission gate TG1 and the second transmission gate TG2 gating OP3 or ON3 as the selection signal of alternative data selector.General design: the data selector anode of bidirectional shift register lowest order (1 end) connects the closed level of current supply switch, owing to using PMOS switch, closed level is low level; The data selector negative terminal of bidirectional shift register lowest order (0 end) connects the disconnection level of current supply switch, i.e. high level.
Beneficial effect: the Preamplifier-latch comparator of low imbalance provided by the invention, on the basis of existing Preamplifier-latch comparator, added the mistuning calibration function control circuit based on stored digital and control, the imbalance of Preamplifier-latch comparator can be reduced to original 1/N, the figure place that N is shift register; Comparator after calibration has reduced imbalance significantly, and can adjust flexibly calibration figure place N according to application scenario; Be different from traditional mistuning calibration function control circuit, the present invention does not affect the speed of comparator after having added mistuning calibration function control circuit, and after comparator calibration finishes, the adjustment control module consisting of digital circuit does not produce quiescent dissipation; Adjustment of the present invention belongs to restoration type adjustment, in the normal work of comparator, mistuning calibration function control circuit is keeping the state after mistuning calibration function, so the present invention can also carry out with the comparator course of work technical compatibility of mistuning calibration function, thereby further improves the precision of comparator.
Accompanying drawing explanation
Fig. 1 is based on a kind of Preamplifier-latch comparator mistuning calibration function circuit topological structure figure of the present invention;
Fig. 2 is based on a kind of bias adjustment circuit topology diagram of the present invention;
Fig. 3 adjusts gating switch topology diagram based on a kind of biasing of the present invention;
Fig. 4 adjusts control module topology diagram based on a kind of biasing of the present invention;
Fig. 5 is comparator imbalance voltage equivalent schematic;
Fig. 6 is Preamplifier-latch comparator mistuning calibration function circuit key node voltage oscillogram.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further described.
Be illustrated in figure 1 a kind of Preamplifier-latch comparator of low imbalance, comprise basic Preamplifier-latch comparator 1, offset compensation to managing 2, mistuning calibration function switch 3 and mistuning calibration function control circuit 4, described basic Preamplifier-latch comparator 1 comprises the prime amplifier of the first order, the latch of the second level, described offset compensation comprises imbalance adjustment pipe to managing 2, the output that pipe is connected in parallel on prime amplifier is adjusted in described imbalance, the carrier of device offset compensation as a comparison, adjusts the offset voltage of comparator by the lack of proper care grid voltage of adjusting pipe of change; The enable switch whether described mistuning calibration function switch 3 carries out mistuning calibration function operation as mistuning calibration function control circuit 4; Described mistuning calibration function control circuit 4 adopts bidirectional shift register, for storing error information and adjusting imbalance and adjust the grid voltage of pipe with the imbalance of compensation comparator.
As shown in Figure 1,1 one kinds of described basic Preamplifier-latch comparators belong to available circuit, comprise the prime amplifier of the first order, the latch of the second level and inverter.
Described prime amplifier mainly consists of a NMOS pipe M1, the 2nd NMOS pipe M2, the 6th NMOS pipe M6 and the 7th PMOS pipe MOS7 to the ten PMOS pipe M10; Wherein, the input that a NMOS pipe M1 and the 2nd NMOS pipe M2 are prime amplifier is to pipe, and the 6th NMOS pipe M6 is the tail current of prime amplifier, and the 7th PMOS pipe M7 to the ten PMOS pipe M10 form the load of prime amplifier; The input of prime amplifier is to pipe simultaneously as the differential input end of basic Preamplifier-latch comparator 1, and the input signal of a NMOS pipe M1 is IP1, and the input signal of the 2nd NMOS pipe M2 is IN1, and the output signal of prime amplifier is OP1 and ON1.
Described latch mainly consists of the 11 NMOS pipe M11 to the 14 NMOS pipe M14, the 15 PMOS pipe M15 to the 18 PMOS pipe M18 and the 19 NMOS pipe M19; Wherein, the input that the 11 NMOS pipe M11 and the 12 NMOS pipe M12 are latch, the grid input signal of the 11 NMOS pipe M11 is OP1, the grid input signal of the 12 NMOS pipe M12 is ON1; The 13 NMOS pipe M13, the 14 NMOS pipe M14, the 15 PMOS pipe M15 and the 16 PMOS pipe M16 form the positive feedback of latch; Latch connects clock signal by the 17 PMOS pipe M17, the 18 PMOS pipe M18 and the 19 NMOS pipe M19 and realizes reset; The output signal of latch is OP2 and ON2.
The output signal OP2 of described latch and ON2 prevent the output signal OP3 of large latched comparator 1, ON3 through reverser basis of formation.Through inverter, can strengthen the driving force of output, and output signal is converted into reset level is 0 output format.
As shown in Figure 1, described offset compensation comprises the 3rd NMOS pipe M3, the 4th NMOS pipe M4 and the 5th NMOS pipe M5 to managing 2, the 3rd NMOS pipe M3 and the 4th NMOS pipe M4 are connected in parallel on the output of prime amplifier, and the input signal of the 3rd NMOS pipe M3 is OP1, and the input signal of the 4th NMOS pipe M4 is ON1; The 5th NMOS pipe M5 is as the tail current of the 3rd NMOS pipe M3 and the 4th NMOS pipe M4, the total current of the 3rd NMOS pipe M3 and the 4th NMOS pipe M4 is flow through in control, avoids that common mode electrical level due to the 3rd NMOS pipe M3 and the 4th NMOS pipe M4 is excessive enters the normal work that dark linear zone affects prime amplifier; The grid of the 3rd NMOS pipe M3 meets the output signal V of calibration control circuit 4
cal_L, the grid of the 4th NMOS pipe M4 meets the output signal V of calibration control circuit 4
cal_R.
As shown in Figure 1, described mistuning calibration function switch 3 mainly forms with AND2 with door AND1 and second by first, first with door AND1 input signal be that OP3 and mistuning calibration function enable signal EN, output signal are OP4, second with door AND2 input signal be that ON3 and mistuning calibration function enable signal EN, output signal are ON4.The function of mistuning calibration function switch 3 is on the basis of basic Preamplifier-latch comparator 1 Output rusults, to add enable signal: if the EN of input is high level, output signal OP4, ON4 are identical with input OP3, ON3 respectively, 4 work of mistuning calibration function control circuit; If the EN of input is low level, output signal OP4, ON4 are always low level, and mistuning calibration function control circuit 4 is not worked, and are keeping the last state of adjusting constant.
Described mistuning calibration function control circuit 4 comprises that offset compensation is adjusted gating switch 4.3 to pipe biasing circuit 4.1, bias adjustment circuit 4.2, biasing and control module 4.4 is adjusted in biasing; Described offset compensation is converted into bias voltage to pipe biasing circuit 4.1 for the electric current that current source is produced; Described bias adjustment circuit 4.2, for generation of adjusting electric current, is adjusted offset compensation to managing 2 grid voltage by offset compensation to pipe biasing circuit 4.1; Described biasing is adjusted gating switch 4.3 and for adjustment current source gating to the offset compensation that bias adjustment circuit 4.2 is produced, pipe biasing circuit 4.1 is setovered; Described biasing is adjusted control module 4.4 and mainly bidirectional shift register, is consisted of, and the current supply switch of bias adjustment circuit 4.2 is controlled.
As shown in Figure 1, described offset compensation mainly consists of the 20 PMOS pipe M20,21 PMOS pipe M21, the 22 PMOS pipe M22, the 23 PMOS pipe M23, the 24 PMOS pipe M2, the 25 NMOS pipe M26 and the 26 NMOS pipe M26 pipe biasing circuit 4.1; The 20 PMOS pipe M20 and the 21 PMOS pipe M21 and the 22 PMOS pipe M22 form current mirror; The 23 PMOS pipe M23 being held open and the 24 PMOS pipe M24, for regulating the structure of offset compensation to pipe biasing circuit 4.1, make offset compensation consistent with the structure of bias adjustment circuit 4.2 to pipe biasing circuit 4.1; The 25 NMOS pipe M25 and the 26 NMOS pipe M26 connect into diode form as metal-oxide-semiconductor resistance, by the electric current I of being come by current source mirror image
r1be superimposed with the offset current I being produced by imbalance Circuit tuning 4.2
cL/ I
cRbe converted into offset compensation to managing 2 bias voltage V
cal_L/ V
cal_R;
As shown in Figure 2, described bias adjustment circuit 4.2 comprises the 31 PMOS pipe M31 to the 38 PMOS pipe M38, the 41 PMOS pipe M41 to the 48 PMOS pipe M48, described the 41 PMOS pipe M41 to the 48 PMOS pipe M48 are in series with the 31 PMOS pipe M31 to the 38 PMOS pipe M38 respectively, and described the 20 PMOS pipe M20 and the 31 PMOS pipe M31 to the 38 PMOS pipe M38 form current mirror; The 31 PMOS pipe M31 to the 38 PMOS pipe M38 adjust current source as eight, produce and adjust electric current I 1～I8; 41 PMOS pipe M41 to the 48 PMOS pipe M48, as the whether effective current supply switch of the electric current I 1～I8 that controls current mirror, control bias current access offset compensation to pipe biasing circuit 4.1; By adjusting the weight of current source I1～I8, can adjust the size of the 31 PMOS pipe M31 to the 38 PMOS pipe M38 so that the misalignment rate that the adjustment current source I1～I8 of access adjusts is one by one identical, make input offset voltage adjust step-length identical.
The existence that gating switch 4.3 is adjusted in biasing is owing to only having used one group to adjust current source, the biasing that must gating need to adjust; As shown in Figure 3, described biasing adjustment gating switch 4.3 comprises gating switch control circuit and gating switch main body; Described gating switch control circuit comprises the first set-reset flip-floop SR1, the second rest-set flip-flop SR2, the first inverter N1, the 51 NMOS pipe M51 and the 52 NMOS pipe M52, the first set-reset flip-floop SR1 is comprised of the first NOR gate NOR1 and the second NOR gate NOR2, the second rest-set flip-flop SR2 is comprised of the 3rd NOR gate NOR3 and four nor gate NOR4, and the first inverter N1, the 51 NMOS pipe M51 and the 52 NMOS pipe M52 are connected between the first set-reset flip-floop SR1 and the second set-reset flip-floop SR2; Described gating switch main body comprises an alternative data selector, described data selector mainly consists of the 53 NMOS pipe M53 and the 55 NMOS pipe M55, the 54 NMOS that connects in data selector manages M54 and the 56 NMOS pipe M56, and described the 54 NMOS pipe M54 and the 56 NMOS pipe M56 are as the reset terminal of above-mentioned data selector; Because the control signal of gating switch consists of set-reset flip-floop, once reset, finish, gating switch 4.3 is adjusted in biasing will keep this strobe state, until the arrival of next reset signal.
As shown in Figure 4, described biasing is adjusted control module 4.4 and mainly bidirectional shift register, is consisted of, the number of described bidirectional shift register equates with the number of current supply switch in bias adjustment circuit 4.2, equates with the tail current number of bias adjustment circuit 4.2, represents the precision of mistuning calibration function; The output signal of eight bidirectional shift registers is respectively Q1 to Q8, and described Q1 to Q8 connects respectively the grid input of the 41 PMOS pipe M41 to the 48 PMOS pipe M48, controls the current supply switch of bias adjustment circuit 4.2; Described bidirectional shift register mainly consists of alternative data selector and edge d type flip flop, and the output CONT that adjusts gating switch 4.3 by biasing controls the first transmission gate TG1 and the second transmission gate TG2 gating OP3 or ON3 as the control signal of alternative data selector; The first data selector MUX1 to the eight data selector MUX8 are corresponding the 41 PMOS pipe M41 to the 48 PMOS pipe M48 respectively.By chose signal, controlling bidirectional shift register is that displacement is moving or moving from a high position to low displacement from low level to height: bidirectional shift register lowest order positive input terminal is fixed on the closed current potential of current supply switch, what the first data selector MUX1 anode (1 end) in Fig. 4 connected is low level, and in corresponding diagram 2, the 41 PMOS pipe M41 is closed; Bidirectional shift register highest order negative input end is fixed on the disconnection current potential of current supply switch, and what the 8th data selector MUX8 negative terminal (0 end) in Fig. 4 connected is high level, and in corresponding diagram 2, the 48 PMOS pipe M48 disconnects; Therefore when clock signal is high level from low transition, if bidirectional shift register is moving to height displacement by low level, current source is adjusted in biasing in bias adjustment circuit 4.2 multiple access one tunnels; If bidirectional shift register is moving to low displacement by a high position, bias adjustment circuit 4.2 can disconnect closed current highest order and adjust current supply switch, and bias adjustment circuit 4.2 can reduce a road Circuit tuning.OP4 and ON4 be the clock signal ck as the first d type flip flop DF1 to the eight d type flip flop DF8 through NOR gate.
As shown in Figure 5, when starting to carry out mistuning calibration function, enable signal EN, the reset signal RST of input are all high level, the differential input signal IP of basic Preamplifier-latch comparator 1 and IN are accessed to the input common mode electrical level V of basic Preamplifier-latch comparator 1
cOM, and the offset voltage equivalence of basic Preamplifier-latch comparator 1 is arrived to input, be expressed as input offset voltage V
os, as shown in Figure 5.
Suppose V
osfor (V just
osfor negative situation and V
osfor the class of operation of positive situation comparator calibration circuit seemingly, no longer repeat specification), when clock signal clk is low level, basis Preamplifier-latch comparator 1 resets, output signal OP2, ON2 are moved to high level by the 17 PMOS pipe M17 and the 18 PMOS pipe M18, after inverter, output signal is low level OP3, ON3, and biasing is adjusted gating switch 4.3 and disconnected and inclined to one side V
cal_L, V
cal_Rconnection, and reset to supply voltage.When clock signal clk is high level, offset voltage passes through basic Preamplifier-latch comparator 1, obtains Output rusults and is: OP2 is high level, and ON2 is low level; After inverter, output signal is: OP3 is low level, and ON3 is high level; Because enable signal EN is high level, OP4, ON4 are identical with the value of OP3, ON3 respectively; Now reset signal is still high, and the first data selector MUX1 to the eight data selector MUX8 are output as reset output, i.e. high level; The input of the first d type flip flop DF1 to the eight d type flip flop DF8 is all reset high level; The clock of d type flip flop consists of through the 5th NOR gate NOR5 ON4, OP4; Therefore, after CLK high level finishes, the first d type flip flop DF1 to the eight d type flip flop DF8 all reset, make the 41 PMOS pipe M41 to the 48 PMOS pipe M48 all by; Now Circuit tuning has completed the reset to digital circuit part; When the input RST that resets keeps high, circuit remains on reset mode always.
When reset signal, RST jumps to low level from high level, and enable signal EN remains high level.Before next CLK clock is from low transition to high level, comparator output keeps OP3 low level, ON3 high level.OP4 after mistuning calibration function switch 3, ON4 respectively with OP3, the value of ON3 is identical.In biasing, adjust gating switch 4.3, because OP4 is low level, ON4 is high level, and therefore after reset signal RST saltus step is low level, gating control signal CONT is for maintaining low level, the alternative data selector gates V of correspondence
jO-end, connects grid voltage V corresponding to the 4th NMOS pipe M4
cal_Rbiasing circuit.After gating, gating switch 4.3 is adjusted in biasing will keep this strobe state until next reset signal RST is high level.
When CLK clock is from low transition to high level, owing to also not calibrating, the output of the large latched comparator of basis prevention is still OP3 low level, ON3 high level.Therefore OP4, ON4 are respectively low level, high level.The data selector control end chose that control module 4.4 is adjusted in biasing is high level through transmission gate one TG1 and transmission gate two TG2.Data selector in bidirectional shift register is selected the signal of 1 end thereby in the saltus step of the clock ck of this shift register rising edge, bidirectional shift register forward moves one, the first bidirectional shift register DF1 to the eight bidirectional shift register DF8 are from status to one of high displacement, the 1 input termination low level due to data selector MUX1, therefore the output Q1 saltus step of the first register DF1 is low level, and Q7～Q8 remain high level.Therefore switch the 41 PMOS pipe M41 of the control of Q1 is conducting, and the electric current that flow into the 26 NMOS pipe M26 is the electric current that the electric current of the 22 PMOS pipe M22 adds the 31 PMOS pipe M31.V
cal_Rthe voltage electric current that increased by the 31 PMOS pipe M31 be multiplied by the resistance of the 26 NMOS pipe M26.
After this, clock CLK is from low transition to high level, and two kinds of situations may appear in the output of basic Preamplifier-latch comparator 1.The first situation is OP3 low level, ON3 high level; The second situation is OP3 high level, ON3 low level.
In the first situation, the bidirectional shift register output Q1 to Qk-1 that supposes preceding state is that (k is between 1 to 8 for low level, when occurring Q0, Q1 to Q8 is all low level), the bidirectional shift register of biasing adjustment control module 4.4 will be shifted one again from low level to height so, lowest order saltus step low level in bidirectional shift register output high level is that Qk is that saltus step is low level, the output of other bidirectional shift registers keeps preceding state, now Q1 is low level to Qk, Qk+1 is that high level is (when occurring Q9 to Q8, Q1 to Q8 is all high level).The adjustment current supply switch the 40 that Qk controls adds PMOS (M40+k) conducting of k, and the electric current that flow into the 26 NMOS pipe M26 is that the electric current of the 22 PMOS pipe M22 adds that the 31 PMOS pipe M31 to the 30 adds the electric current of the PMOS pipe (M30+k) of k.With respect to preceding state, V
cal_Rvoltage increased the resistance that the 30 electric current that adds k PMOS pipe (M30+k) is multiplied by the 26 NMOS pipe M26.
In the second situation, the bidirectional shift register output Q1 to Qk that supposes preceding state is low level, the bidirectional shift register of biasing adjustment control module 4.4 will be from a high position to one of low displacement so, highest order saltus step high level in bidirectional shift register output low level, be that Qk saltus step is high level, the output of other shift registers keeps preceding state, and now Q1 works as and occurs that time Q0 be that whole Q1～Q8 are all high level to Qk-1() be low level, Qk is high level to Q8.The PMOS (M40+k) that the adjustment current supply switch the 40 that Qk controls adds k by, the electric current that flow into the 26 NMOS pipe M26 is that the electric current of the 22 PMOS pipe M22 adds that the 31 PMOS pipe M31 to the 30 adds the electric current of the PMOS pipe (M30+k-1) of k-1.So with respect to preceding state, V
cal_Rvoltage reduced the resistance that the 30 electric current that adds k PMOS pipe (M30+k) is multiplied by the 26 NMOS pipe M26.
When input enable signal EN saltus step is low level, the mistuning calibration function of basic Preamplifier-latch comparator 1 is finished, mistuning calibration function control circuit 4 is low level adjustment state constantly by keeping Enable Pin saltus step, basic Preamplifier-latch comparator 1 starts normal work.
Fig. 6 be shown in each key node voltage of the present invention along with the change curve of time.Input IP1, the IN1 of comparator of being in course of adjustment accesses the common mode input V of basic Preamplifier-latch comparator 1
cOMin.The output low level of output signal OP3, the ON3 that can find out basic Preamplifier-latch comparator 1 from curve from maintaining respectively before calibration, high level is exported OP3, ON3 and is interweaved and be output as high level to having calibrated rear comparator.By offset compensation to managing 2 grid voltage (V
cal_L, V
cal_R) relative value change, the imbalance of basic Preamplifier-latch comparator 1 is calibrated.
The above is only the preferred embodiment of the present invention; be noted that for those skilled in the art; under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1. the Preamplifier-latch comparator of a low imbalance, comprise basic Preamplifier-latch comparator (1), offset compensation is to pipe (2), mistuning calibration function switch (3) and mistuning calibration function control circuit (4), described basic Preamplifier-latch comparator (1) comprises the prime amplifier of the first order, the latch of the second level, it is characterized in that: described offset compensation comprises imbalance adjustment pipe to pipe (2), the output that pipe is connected in parallel on prime amplifier is adjusted in described imbalance, the carrier of device offset compensation as a comparison, by the lack of proper care difference grid voltage of adjusting pipe of change, compensate the offset voltage of comparator, the enable switch whether described mistuning calibration function switch (3) carries out mistuning calibration function operation as mistuning calibration function control circuit (4), described mistuning calibration function control circuit (4) adopts bidirectional shift register, for storing error information and adjusting imbalance and adjust the grid voltage of pipe with the imbalance of compensation comparator.
2. the Preamplifier-latch comparator of low imbalance according to claim 1, is characterized in that: described mistuning calibration function control circuit (4) comprises that offset compensation is adjusted gating switch (4.3) to pipe biasing circuit (4.1), bias adjustment circuit (4.2), biasing and control module (4.4) is adjusted in biasing; Described offset compensation is converted into bias voltage to pipe biasing circuit (4.1) for the electric current that current source is produced; Described bias adjustment circuit (4.2), for generation of adjusting electric current, is adjusted the grid voltage of offset compensation to pipe (2) by offset compensation to pipe biasing circuit (4.1); Described biasing is adjusted gating switch (4.3) and for adjustment current source gating to the offset compensation that bias adjustment circuit (4.2) is produced, pipe biasing circuit (4.1) is setovered; Described biasing is adjusted control module (4.4) and mainly bidirectional shift register, is consisted of, and the current supply switch of bias adjustment circuit (4.2) is controlled.
3. the Preamplifier-latch comparator of low imbalance according to claim 2, is characterized in that: described offset compensation mainly consists of the 20 PMOS pipe M20,21 PMOS pipe M21, the 22 PMOS pipe M22, the 25 NMOS pipe M25 and the 26 NMOS pipe M26 pipe biasing circuit (4.1); The 20 PMOS pipe M20 and the 21 PMOS pipe M21 and the 22 PMOS pipe M22 form current mirror; The 25 NMOS pipe M25 and the 26 NMOS pipe M26 connect into diode form as metal-oxide-semiconductor resistance, by the electric current I of being come by current source mirror image
r1be superimposed with the offset current I being produced by imbalance Circuit tuning (4.2)
cL/ I
cRbe converted into the bias voltage V of offset compensation to pipe (2)
cal_L/ V
cal_R.
4. the Preamplifier-latch comparator of low imbalance according to claim 3, is characterized in that: described bias adjustment circuit (4.2) comprises the adjustment current source of one group of parallel connection, and each adjusts a current supply switch of current source series connection; Each adjusts current source is a PMOS pipe, and each current supply switch is a PMOS pipe; Described the 20 PMOS pipe M20 forms current mirror with adjustment current source.
5. the Preamplifier-latch comparator of low imbalance according to claim 4, is characterized in that: described biasing is adjusted gating switch (4.3) and comprised gating switch control circuit and gating switch main body; Described gating switch control circuit comprises the first set-reset flip-floop SR1, the second rest-set flip-flop SR2, the first inverter N1, the 51 NMOS pipe M51 and the 52 NMOS pipe M52, the first set-reset flip-floop SR1 is comprised of the first NOR gate NOR1 and the second NOR gate NOR2, and the second rest-set flip-flop SR2 is comprised of the 3rd NOR gate NOR3 and four nor gate NOR4; Described gating switch main body comprises an alternative data selector, described data selector mainly consists of the 53 NMOS pipe M53 and the 55 NMOS pipe M55, the 54 NMOS that connects in data selector manages M54 and the 56 NMOS pipe M56, and described the 54 NMOS pipe M54 and the 56 NMOS pipe M56 are as the reset terminal of data selector.
6. the Preamplifier-latch comparator of low imbalance according to claim 5, it is characterized in that: described biasing is adjusted in control module (4.4), the number of bidirectional shift register equates with the number of current supply switch in bias adjustment circuit (4.2), each bidirectional shift register is controlled a current supply switch, the grid of the output signal access current supply switch of bidirectional shift register; Described bidirectional shift register mainly consists of alternative data selector and edge d type flip flop, by biasing, adjusts the first transmission gate TG1 of gating switch (4.3) CONT output control and the control signal of the second transmission gate TG2 gating alternative data selector.
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105119602A (en) * | 2015-08-28 | 2015-12-02 | 西安启微迭仪半导体科技有限公司 | Switched capacitor comparator circuit in analog to digital converter |
| WO2016134605A1 (en) * | 2015-02-27 | 2016-09-01 | Huawei Technologies Co., Ltd. | Comparator apparatus and method |
| CN107241098A (en) * | 2017-05-24 | 2017-10-10 | 东南大学 | The mistuning calibration function circuit of comparator in a kind of asynchronous gradual approaching A/D converter |
| CN110061739A (en) * | 2019-05-20 | 2019-07-26 | 长沙景美集成电路设计有限公司 | The PLL circuit and its implementation that a kind of pair of technique causes mos capacitance electric leakage of the grid insensitive |
| TWI672002B (en) * | 2018-09-17 | 2019-09-11 | 創意電子股份有限公司 | Comparator circuitry |
| CN110474638A (en) * | 2019-07-30 | 2019-11-19 | 成都铭科思微电子技术有限责任公司 | The Background calibration circuit and method of latch-type comparator imbalance error |
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| CN112764447A (en) * | 2021-04-07 | 2021-05-07 | 上海艾为微电子技术有限公司 | Dynamic offset calibration circuit, method, chip and electronic equipment |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316992B1 (en) * | 1999-07-29 | 2001-11-13 | Tripath Technology, Inc. | DC offset calibration for a digital switching amplifier |
| US20060186928A1 (en) * | 2005-02-23 | 2006-08-24 | Via Technologies Inc. | Comparators capable of output offset calibration |
| CN101034890A (en) * | 2007-02-16 | 2007-09-12 | 东南大学 | Disorder bit compensation circuit for gradual approaching A/D converter |
| CN101282117A (en) * | 2007-04-05 | 2008-10-08 | 中国科学院微电子研究所 | Dynamic comparator |
| CN101562441A (en) * | 2008-10-08 | 2009-10-21 | 西安电子科技大学 | Ultrahigh-speed comparator with low offset |
| CN101917195A (en) * | 2010-08-18 | 2010-12-15 | 中国电子科技集团公司第五十八研究所 | High-precision and low-offset charge comparator circuit |
-
2014
- 2014-01-03 CN CN201410001389.1A patent/CN103762962B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316992B1 (en) * | 1999-07-29 | 2001-11-13 | Tripath Technology, Inc. | DC offset calibration for a digital switching amplifier |
| US20060186928A1 (en) * | 2005-02-23 | 2006-08-24 | Via Technologies Inc. | Comparators capable of output offset calibration |
| CN101034890A (en) * | 2007-02-16 | 2007-09-12 | 东南大学 | Disorder bit compensation circuit for gradual approaching A/D converter |
| CN101282117A (en) * | 2007-04-05 | 2008-10-08 | 中国科学院微电子研究所 | Dynamic comparator |
| CN101562441A (en) * | 2008-10-08 | 2009-10-21 | 西安电子科技大学 | Ultrahigh-speed comparator with low offset |
| CN101917195A (en) * | 2010-08-18 | 2010-12-15 | 中国电子科技集团公司第五十八研究所 | High-precision and low-offset charge comparator circuit |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016134605A1 (en) * | 2015-02-27 | 2016-09-01 | Huawei Technologies Co., Ltd. | Comparator apparatus and method |
| US9467133B2 (en) | 2015-02-27 | 2016-10-11 | Huawei Technologies Co., Ltd. | Comparator apparatus and method |
| CN105119602B (en) * | 2015-08-28 | 2019-01-29 | 西安启微迭仪半导体科技有限公司 | Switching capacity comparator circuit in a kind of analog-digital converter |
| CN105119602A (en) * | 2015-08-28 | 2015-12-02 | 西安启微迭仪半导体科技有限公司 | Switched capacitor comparator circuit in analog to digital converter |
| CN107241098A (en) * | 2017-05-24 | 2017-10-10 | 东南大学 | The mistuning calibration function circuit of comparator in a kind of asynchronous gradual approaching A/D converter |
| TWI672002B (en) * | 2018-09-17 | 2019-09-11 | 創意電子股份有限公司 | Comparator circuitry |
| US10924099B2 (en) | 2019-01-02 | 2021-02-16 | Boe Technology Group Co., Ltd. | Comparator and analog-to-digital converter |
| WO2020140469A1 (en) * | 2019-01-02 | 2020-07-09 | 京东方科技集团股份有限公司 | Comparator and analog-to-digital converter |
| CN110061739A (en) * | 2019-05-20 | 2019-07-26 | 长沙景美集成电路设计有限公司 | The PLL circuit and its implementation that a kind of pair of technique causes mos capacitance electric leakage of the grid insensitive |
| CN110061739B (en) * | 2019-05-20 | 2023-12-01 | 长沙景美集成电路设计有限公司 | PLL circuit insensitive to MOS capacitor grid leakage caused by process |
| CN110474638A (en) * | 2019-07-30 | 2019-11-19 | 成都铭科思微电子技术有限责任公司 | The Background calibration circuit and method of latch-type comparator imbalance error |
| CN110474638B (en) * | 2019-07-30 | 2023-04-25 | 成都铭科思微电子技术有限责任公司 | Background correction circuit and method for offset error of latch comparator |
| CN110855274A (en) * | 2019-10-23 | 2020-02-28 | 广西师范大学 | Low-offset rail-to-rail dynamic latch comparator |
| CN110855274B (en) * | 2019-10-23 | 2024-05-14 | 广西师范大学 | Low-loss track-to-track dynamic latching comparator |
| CN111614333A (en) * | 2020-01-03 | 2020-09-01 | 东南大学 | High-speed sampling amplifier with offset cancellation function |
| CN111899776A (en) * | 2020-08-03 | 2020-11-06 | 安徽大学 | Circuit structure for reducing offset voltage of sense amplifier in static random access memory |
| CN111899776B (en) * | 2020-08-03 | 2022-09-16 | 安徽大学 | Circuit structure for reducing offset voltage of sense amplifier in static random access memory |
| CN112466363A (en) * | 2020-12-01 | 2021-03-09 | 西安紫光国芯半导体有限公司 | Sense amplifier, data receiving circuit, electronic device, and data receiving method |
| CN112764447A (en) * | 2021-04-07 | 2021-05-07 | 上海艾为微电子技术有限公司 | Dynamic offset calibration circuit, method, chip and electronic equipment |
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