CN103489777A - Stress memory technology method - Google Patents
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- CN103489777A CN103489777A CN201210190197.0A CN201210190197A CN103489777A CN 103489777 A CN103489777 A CN 103489777A CN 201210190197 A CN201210190197 A CN 201210190197A CN 103489777 A CN103489777 A CN 103489777A
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000005516 engineering process Methods 0.000 title abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000009826 distribution Methods 0.000 claims description 9
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 4
- 238000004151 rapid thermal annealing Methods 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 14
- 238000000151 deposition Methods 0.000 abstract description 4
- 230000003446 memory effect Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 description 10
- 239000007789 gas Substances 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical group O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a stress memory technology method which comprises the steps of providing a substrate, depositing and forming a polycrystalline silicon gate of which the germanium content is distributed in a gradient way on the substrate, forming a source and a drain in the substrate, forming a stress memory layer covering the substrate and the gate and performing thermal annealing. The stress memory technology method of the invention can overcome the dependency on the strength of constraining materials, namely, people do not need to worry too much about whether a stress can be borne by a constraining material when the stress is introduced, and the risk of stress release caused by constraining materials is reduced so that an ideal stress memory effect is achieved.
Description
Technical field
The present invention relates to a kind of technical field of manufacturing semiconductors, more precisely, the present invention relates to a kind of stress memory technique method.
Background technology
Along with the development of semiconductor device technology and in proportion size dwindle, stress engineering is playing increasing effect aspect semiconductor technology and device performance.The stress memory effect is a kind of method of stress of introducing in semiconductor fabrication process, for example stress is put on to the performance that field-effect transistor can improve them, when stress application on raceway groove (Channel) direction, tensile stress can improve electron mobility, and compression can improve hole mobility.In traditional polysilicon gate is manufactured, or even in the metal gate manufacture, it is all indispensable technological means.
Because the crystal grain of growing in recrystallization process and its impurity effect are greater than silicon atom, be polysilicon gate generation deformation, and the deformation of raising polysilicon gate is the reason that realizes the performance improvement of N type semiconductor in stress memory technique.
Therefore, the improvement of stress memory technique effect can realize with the deformation that improves polysilicon by the doping that improves polysilicon gate, if but the insufficient strength of constraint material and can not limit polysilicon deformation, as shown in Figure 2, particularly, at the top of polycrystalline, so caused stress will be released.
Summary of the invention
In view of above problem, the invention provides a kind of stress memory technique method, comprise a substrate is provided; On described substrate, deposition forms the polysilicon gate with Ge content distribution gradient; Form source-drain electrode in described substrate; Form the stress memory layer that covers described substrate and described grid; Carry out the steps such as thermal annealing.
Preferably, deposit the gas used in the step that forms the polysilicon gate with Ge content distribution gradient and comprise GeH4; The amount that passes into GeH4 gas in deposition process reduces gradually; The content of the germanium of distribution gradient is higher near raceway groove; The silicon nitride that described stress memory layer is silicon nitride layer, silicon dioxide, doping or the silica of doping can be also other suitable materials; The method of described thermal annealing is rapid thermal annealing or laser annealing; After described thermal annealing, also comprise the step of removing described stress memory layer.
This method can overcome the dependence to constraint material intensity, whether when introducing stress, needn't too much take care it is that constraint material can be born, and reduce the risk due to the former of constraint material thereby the Stress Release that causes, and obtain desirable stress memory effect.
The accompanying drawing explanation
Fig. 1 is the principle schematic of stress memory technique;
Fig. 2 is the principle schematic of Stress Release;
Fig. 3 is the polysilicon gate with Ge content distribution gradient of the present invention;
Fig. 4 is the schematic diagram of polysilicon deformation situation of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, detailed step will be proposed in following description, so that the stress memory technique method that explaination the present invention proposes.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet, except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.Next, in connection with accompanying drawing, the present invention is more intactly described.
At first, as shown in Figure 1, provide a substrate 101.Described substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Can be formed with doped region and/or isolation structure in described substrate, described isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Can also be formed with cmos device in described substrate, cmos device is for example transistor (for example, NMOS and/or PMOS) etc.In order to simplify, only with a blank, mean described substrate herein.In addition, the upper surface of described substrate also comprises the insulating barrier (not shown), and insulating barrier can comprise silica, sapphire and/or other applicable insulating material.
Then, carry out the step of the deposit spathic silicon grid 102 on described substrate.Described deposition can comprise chemical vapour deposition technique (CVD), as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD), also can use such as the general similarity method such as sputter and physical vapour deposition (PVD) (PVD).Use in one embodiment of the invention low-pressure chemical vapor phase deposition (LPCVD) technique to form described polysilicon gate, its process conditions comprise: reacting gas is silane (SiH4), the range of flow of described silane can be 100～200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700～750 degrees centigrade; The reaction chamber internal pressure can be 250～350 milli millimetress of mercury (mTorr), as 300mTorr; Also can comprise buffer gas in described reacting gas, described buffer gas can be helium (He) or nitrogen, and the range of flow of described helium and nitrogen can be 5～20 liter/mins (slm), as 8slm, 10slm or 15slm.In addition, also pass into gas GeH4.And the flow that passes into gas GeH4 is controlled, and the flow velocity that makes GeH4 in this deposition process is near slowly, thus make germanic amount in formed polysilicon gate near raceway groove higher and distribution gradient from high to low, as shown in Figure 3.In addition, can also comprise the step that forms side wall.
The step of Implantation is carried out in the zone of then, carrying out forming source-drain electrode in described substrate.Can comprise by ion implantation technology and form source drain region in the Semiconductor substrate around grid.
Then, form the step of the stress memory layer 103 that covers described substrate and described grid.The method of described formation stress memory layer can be the method for deposition.The material of stress memory layer can be the silicon nitride of silicon nitride, silicon dioxide, doping or the suitable materials such as silicon dioxide of doping.Preferred nitrogen SiClx here, in one embodiment of the invention, the stress memory layer is 350 to 450 ℃ of temperature by plasma reinforced chemical vapour deposition (PECVD) technique, power 50 is to 150W, reaction chamber pressure 4 is to 10Torr, the SiH4 flow is 50-100sccm, and the NH3 flow is 400-700sccm, under the condition of N2 flow 800-1500sccm, forms.The thickness of stress memory layer is not less than 300 dusts, is preferably 300 to 800 dusts, and its stress value is 500 to 800MPa, by parameter improvement, can also regulate stress types and stress intensity that the stress memory layer brings out bottom transistor especially.
Finally, after the stress memory layer of removing on PMOS, carry out the step of thermal annealing.Grid and source-drain electrode area being carried out to thermal anneal process and make the stress that the stress memory layer brings out be remembered to corresponding field-effect transistor, is NMOS here.Wherein thermal annealing can be the method for rapid thermal annealing or LASER HEAT annealing.What in the LASER HEAT annealing of one embodiment of the present of invention, use is carbon dioxide laser, in this process, by laser beam arc or linear scan, completes this thermal annealing process.The method of the rapid thermal annealing used in a further embodiment adopts in the admixture of gas atmosphere of NH3 under the condition of 1100 to 1150 ℃ of temperature and Ar carries out.The heating of described atmosphere with per second approximately the speed of 50 ℃ be increased to 1100 to 1150 ℃ from 800 ℃, its temperature-fall period is that the speed of per second 10-70 ℃ is down to 800 ℃.
Due to the germanic amount in the formed polysilicon gate of above step near raceway groove higher and distribution gradient from high to low, therefore can there is in the place near raceway groove the effect that strengthens the polycrystalline diffusion.
In ensuing technique, the stress memory layer is etched away, but the stress of memory in polysilicon gate, still can be transmitted among the raceway groove of NMOS semiconductor device, be transmitted to compression that the stress in raceway groove is the vertical-channel in-plane and the tensile stress on channel direction, impact by above-mentioned stress on the semiconductor device carrier mobility can draw, such stress effect is useful to improving N type semiconductor device electron mobility.Wherein Fig. 4 shows the schematic direction of polysilicon deformation in an embodiment, so can obtain desirable stress memory effect, and needn't too much depend on the intensity of constraint material, whether be constraint material can bear, and reduction is due to the risk of the former of constraint material thereby the Stress Release that causes if when introducing stress, needn't too much take care it.
For the purpose of illustration and description, provided the above description of various aspects of the present invention.It is not intended to exclusive list or limits the invention to disclosed precise forms, and significantly, can carry out numerous modifications and variations.The present invention is intended to it will be apparent to those skilled in the art that these modifications and variations are included in the scope of the present invention be defined by the following claims.
Claims (7)
1. a stress memory technique method comprises:
One substrate is provided;
On described substrate, deposition forms the polysilicon gate with Ge content distribution gradient;
Form source-drain electrode in described substrate;
Form the stress memory layer that covers described substrate and described grid;
Carry out thermal annealing.
2. method according to claim 1, wherein deposit the gas used in the step that forms the polysilicon gate with Ge content distribution gradient and comprise GeH4.
3. method according to claim 2, the amount that wherein in deposition process, passes into GeH4 gas reduces gradually.
4. method according to claim 1, wherein the content of the germanium of distribution gradient is higher near raceway groove.
5. method according to claim 1, the silicon nitride that wherein said stress memory layer is silicon nitride, silicon dioxide, doping or the silica of doping.
6. method according to claim 1, wherein said thermal annealing is rapid thermal annealing or laser annealing.
7. method according to claim 1, wherein, after described thermal annealing, also comprise the step of removing described stress memory layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210190197.0A CN103489777A (en) | 2012-06-11 | 2012-06-11 | Stress memory technology method |
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| CN201210190197.0A CN103489777A (en) | 2012-06-11 | 2012-06-11 | Stress memory technology method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863593A (en) * | 2019-04-30 | 2020-10-30 | 芯恩（青岛）集成电路有限公司 | Stress film with gradient distribution of chemical components, semiconductor device and forming method thereof |
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| US20090020820A1 (en) * | 2007-07-16 | 2009-01-22 | Samsung Electronics Co., Ltd. | Channel-stressed semiconductor devices and methods of fabrication |
| US20090085122A1 (en) * | 2007-10-01 | 2009-04-02 | Vincent Ho | Poly profile engineering to modulate spacer induced stress for device enhancement |
| US20090230427A1 (en) * | 2008-03-13 | 2009-09-17 | International Business Machines Corporation | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing |
| US20100207214A1 (en) * | 2009-02-18 | 2010-08-19 | United Microelectronics Corp. | Semiconductor device and method of fabricating the same |
| CN102169888A (en) * | 2011-03-10 | 2011-08-31 | 清华大学 | Strain geoi structure and forming method thereof |
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2012
- 2012-06-11 CN CN201210190197.0A patent/CN103489777A/en active Pending
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| US20050042849A1 (en) * | 2002-06-25 | 2005-02-24 | Amberwave Systems Corporation | Reacted conductive gate electrodes |
| US20050032321A1 (en) * | 2003-08-08 | 2005-02-10 | Chien-Chao Huang | Strained silicon MOS devices |
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| US20090020820A1 (en) * | 2007-07-16 | 2009-01-22 | Samsung Electronics Co., Ltd. | Channel-stressed semiconductor devices and methods of fabrication |
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| US20090230427A1 (en) * | 2008-03-13 | 2009-09-17 | International Business Machines Corporation | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing |
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| CN111863593B (en) * | 2019-04-30 | 2023-03-14 | 芯恩（青岛）集成电路有限公司 | Stress film with gradient distribution of chemical components, semiconductor device and forming method thereof |
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