CN103091533B - Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices - Google Patents
Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices Download PDFInfo
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- CN103091533B CN103091533B CN201110342681.6A CN201110342681A CN103091533B CN 103091533 B CN103091533 B CN 103091533B CN 201110342681 A CN201110342681 A CN 201110342681A CN 103091533 B CN103091533 B CN 103091533B
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- 238000005070 sampling Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title abstract description 3
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 238000002347 injection Methods 0.000 claims abstract description 62
- 239000007924 injection Substances 0.000 claims abstract description 62
- 230000003139 buffering effect Effects 0.000 claims description 22
- 238000010276 construction Methods 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 238000000926 separation method Methods 0.000 abstract description 9
- 230000005611 electricity Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 239000010410 layer Substances 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 101100194625 Rattus norvegicus Rgs19 gene Proteins 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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Abstract
The invention discloses a current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices. Both a first LDMOS device used for sampling currents and a P-shaped trap of a second LDMOS device used for comparing the currents are encircled by an N-shaped injection region, and the source region of the first LDMOS device is encircled by grid electrodes and arranged in the middle of the whole current sampling circuits. The drain region of the first LDMOS device and the drain region of the second LDMOS device are a sharing structure, the drift region of the drain region of the second LDMOS device is connected with the drift region of the drain region of the first LDMOS device to form a closed structure which is connected end to end, the drain region of the second LDMOS device is sealed at the inner side of the closed structure, and the source region of the second LDMOS device is arranged at the outer side of the closed structure. The current sampling circuit achieved by the LDMOS devices can achieve a complete separation between the two LDMOS devices and eliminate the leakage of electricity between the source ends of the first LDMOS device and the second LDMOS device.
Description
Technical field
The present invention relates to a kind of SIC (semiconductor integrated circuit), particularly relate to a kind of current sampling circuit of realizing with LDMOS device.
Background technology
LDMOS device is a kind of high withstand voltage field effect transistor, can be used to form current sampling circuit.As shown in Figure 1, be the schematic diagram of the existing current sampling circuit of realizing with LDMOS device.Existingly with the current sampling circuit that LDMOS device is realized, comprise LDMOS device 1 and electric current LDMOS device 2 for contrast for current sample, current sample with LDMOS device 1 and electric current contrast with the grid 3 of LDMOS device 2 connect altogether, drain terminal 4 connects altogether, source 5A, 5B divide to open and pick out.As can be seen from Figure 1, current sample contrasts with also having a parasitic substrate resistance in series 10 between the substrate of LDMOS device 2 with LDMOS device 1 and electric current.
As shown in Figure 2, be the domain structure schematic diagram of the existing current sampling circuit of realizing with LDMOS device.Region shown in dashed rectangle 6 is the formation region that LDMOS device 2 is used in electric current contrast, and region shown in dashed rectangle 7 is the formation region that current sample is used LDMOS device 1.Described current sample is all formed at the outside of described grid 13 with source region 9 and the contrast of described electric current of LDMOS device 1 with the source region 8 of LDMOS device 2.Described current sample shares with the 11He drain region, drift region, drain region 12 of LDMOS device 2 with LDMOS device 1 and electric current contrast.Drift region, described drain region 11 is by many strip structure parallel arranged and join end to end and form, and is an enclosed construction.Enclosed construction inner side in drift region, described drain region 11 is described drain region 12.Above the drift region, described drain region 11 between described grid 13 and described drain region 12, be formed with an oxidation separation layer, described grid 13 is comprised of polysilicon, the polysilicon of described grid 13 also extends on described oxidation separation layer, and extension is the polysilicon field plate near source region one side; On described oxidation separation layer of the side near described drain region 12, be also formed with another polysilicon field plate 14.Described grid 13 and described polysilicon field plate 14 are all also enclosed construction, respectively identical around structure with the outside of drift region, described drain region 11 and inner side edge edge.In Fig. 2, can find out, described current sample is to be all formed on P type silicon substrate with source region 9 and the contrast of described electric current of LDMOS device 1 with the P type trap in the source region 8 of LDMOS device 2, and be all positioned at the outside of described grid 13, between the two, there is no isolation structure, between described source region 8 and described source region 9, can form a parasitic substrate resistance in series 10 like this.Formation described drain terminal 4, described grid 4 and described source 5A, 5B as shown in Figure 1 drawn with metal connecting line respectively in described drain region 12, described grid 13, described source region 9 and described source region 8.
While using the above-mentioned existing current sampling circuit with the realization of LDMOS device to adopt, drain terminal need to be received very high voltage, some application will be received over 600V, existence due to described parasitic substrate resistance in series 10, when normal work, between two source 5A and 5B, can have very large electric leakage and cause loss.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of current sampling circuit of realizing with LDMOS device, can make isolation completely between a LDMOS device that current sample uses and the 2nd LDMOS device of electric current contrast use, eliminate the electric leakage between a LDMOS device and the source of the 2nd LDMOS device.
For solving the problems of the technologies described above, the invention provides a kind of current sampling circuit of realizing with LDMOS device, current sampling circuit comprises the 2nd LDMOS device of a LDMOS device that current sample is used and electric current contrast use, and the grid of a described LDMOS device and described the 2nd LDMOS device connects altogether, drain terminal connects altogether, source separately picks out.
On P type silicon substrate, be formed with one first N-type injection region, the 2nd P type trap by a P type trap of a described LDMOS device and described the 2nd LDMOS device of described the first N-type injection region is all surrounded, and a described P type trap and described the 2nd P type trap are kept apart completely by PN junction mutually.
In a described P type trap, be formed with the source region of a described LDMOS device; On a described P type trap, be coated with the grid of a described LDMOS device, the region for the raceway groove of the described LDMOS device of formation by this grid overlay area of a described P type trap; The drain region of a described LDMOS device is formed in the second N-type injection region, is positioned at the drift region, drain region that described the second N-type injection region between the drain region of a described P type trap and a described LDMOS device forms a described LDMOS device.
In described the 2nd P type trap, be formed with the source region of described the 2nd LDMOS device; On described the 2nd P type trap, be coated with the grid of described the 2nd LDMOS device, the region for the raceway groove of described the 2nd LDMOS device of formation by this grid overlay area of described the 2nd P type trap; The drain region of described the 2nd LDMOS device is formed in described the second N-type injection region, is positioned at the drift region, drain region that described the second N-type injection region between the drain region of described the 2nd P type trap and described the 2nd LDMOS device forms described the 2nd LDMOS device.
In top plan view, the domain structure of described current sampling circuit is:
A described LDMOS device is positioned at centre position, in the middle of the source region of a described LDMOS device is centered around by an end to end grid that is closed figures structure, the drift region, drain region of a described LDMOS device is the grid of strip structure and a described LDMOS device and source region all in the drift region, drain region in a described LDMOS device, in the both sides of the drift region, drain region of a described LDMOS device, is two drain regions that are strip structure of a described LDMOS device.
Described the 2nd LDMOS device is connected in parallel and is formed by many strip elements, described in each, the source region of strip element, drift region, drain region, drain region are all identical strip structure, and the drain region of two described strip elements of inner side shares with two bar shaped drain regions of a described LDMOS device respectively; From two bar shaped drain regions of a described LDMOS device, start outward, described in each, strip element is arranged successively outward according to: the arrangement mode in drain region, drift region, drain region, source region, drift region, drain region, drain region; Described in each, the drift region, drain region of the drift region, drain region of strip element and a described LDMOS device links together and is an end to end enclosed construction, and the source region that the drain region of described the 2nd LDMOS device is closed in described the 2nd LDMOS device in inboard of described enclosed construction is positioned to the outside of described enclosed construction.
Further improve and be, the closed figures structure of the grid of a described LDMOS device is racetrack shape or ring-type, and the long axis direction of the closed figures structure of the grid of a described LDMOS device is along the long side direction of the drift region, drain region of a described LDMOS device; In the drift region, drain region of the described LDMOS device at the arc-shaped head place along long axis direction of the grid of a described LDMOS device, be formed with a buffering withstand voltage zone, described buffering withstand voltage zone is comprised of the described P type silicon substrate that does not form described the second N-type injection region, and the drift region, drain region of a described LDMOS device of outside, described buffering withstand voltage zone is all comprised of described the second N-type injection region.
Further improvement is, the curved structure in junction of the described enclosed construction that described in each, drift region, drain region of the drift region, drain region of strip element and a described LDMOS device forms, described in each, the grid of strip element also links together according to the connected mode of drift region, drain region described in each, also curved structure of the junction of the grid of strip element described in each, described in each, described in corresponding each in the arc junction that bends towards described source region one side of the grid of strip element, in the drift region, drain region of strip element, be formed with respectively a buffering withstand voltage zone, described buffering withstand voltage zone is comprised of the described P type silicon substrate that does not form described the second N-type injection region, and outside, described buffering withstand voltage zone other each described in the drift region, drain region of strip element all by described the second N-type injection region, formed.
Further improve and be, the part that described the first N-type injection region is described the second N-type injection region and described the first N-type injection region are by extending to source region one side of a described LDMOS device and described the 2nd LDMOS device and described the second N-type injection region that a described P type trap and described the 2nd P type trap are surrounded completely being formed.
Further improve and be, the grid of the grid of a described LDMOS device and described the 2nd LDMOS device is all comprised of polysilicon, forming between the grid of a described LDMOS device and the polysilicon of the grid of described the 2nd LDMOS device is independently, between the grid of a described LDMOS device and the grid of described the 2nd LDMOS device, by metal connecting line, links together.
The present invention uses N-type injection region to surround by the P type trap of the 2nd LDMOS device of a LDMOS device that current sample is used and electric current contrast use, and by the source region of a LDMOS device with grid around and be placed in the centre of whole current sampling circuit, the drain region of the drain region of a LDMOS device and the 2nd LDMOS device is shared simultaneously, the drift region, drain region of the drift region, drain region of the 2nd LDMOS device and a LDMOS device is linked together and is an end to end enclosed construction, make the drain region of the 2nd LDMOS device be closed in the inboard of enclosed construction, the source region of the 2nd LDMOS device is positioned at the outside of enclosed construction, thereby can realize the isolation completely between two LDMOS devices, eliminate the electric leakage between a LDMOS device and the source of the 2nd LDMOS device.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the schematic diagram of the existing current sampling circuit of realizing with LDMOS device;
Fig. 2 is the domain structure schematic diagram of the existing current sampling circuit of realizing with LDMOS device;
Fig. 3 is the schematic diagram of the current sampling circuit of LDMOS device realization for the embodiment of the present invention;
Fig. 4 is the domain structure schematic diagram of the current sampling circuit of LDMOS device realization for the embodiment of the present invention;
Fig. 5 is the sectional structure chart along the device of the AA line in Fig. 4;
Fig. 6 is the sectional structure chart along the device of the BB line in Fig. 4;
Fig. 7 is the sectional structure chart along the device of the CC line in Fig. 4.
Embodiment
As shown in Figure 3, be the schematic diagram of the current sampling circuit of LDMOS device realization for the embodiment of the present invention.The embodiment of the present invention comprises a LDMOS device 301 that current sample is used and the 2nd LDMOS device 302 of electric current contrast use with the current sampling circuit that LDMOS device is realized, and the grid end 303 of a described LDMOS device 301 and described the 2nd LDMOS device 302 connects altogether, drain terminal 304 connects altogether, source 305a and 305b divide to open and pick out.
The domain structure schematic diagram of the current sampling circuit of LDMOS device realization for the embodiment of the present invention as shown in Figure 4; As shown in Figures 5 to 7, be respectively the sectional structure chart along the device of the AA line in Fig. 4, BB line and CC line.
In Fig. 4, region shown in dashed rectangle 201 is the formation region of a LDMOS device 301, and region shown in dashed rectangle 202 is the formation region of described the 2nd LDMOS device 302.
On P type silicon substrate 101, be formed with one first N-type injection region 102, one end, source region that described the first N-type injection region 102 extends to device by the second N-type injection region 102 that is used to form the drift region, drain region 205 of device forms, described the first N-type injection region 102 and described the second N-type injection region 102 are an integral body in embodiments of the present invention, all use identical mark.
The 2nd P type trap 103 by a P type trap 103a of a described LDMOS device 301 and described the 2nd LDMOS device 302 of described the first N-type injection region 102 is all surrounded, and a described P type trap 103a and described the 2nd P type trap 103 are kept apart completely by PN junction mutually.
In a described P type trap 103a, be formed with the source region 210 of a described LDMOS device 301; On a described P type trap 103a, be coated with the grid 209 of a described LDMOS device 301, the region for the raceway groove of the described LDMOS device 301 of formation by these grid 209 overlay areas of a described P type trap 103a; The drain region 206 of a described LDMOS device 301 is formed in the second N-type injection region 102, and described the second N-type injection region 102 that is positioned at 206, the drain region of a described P type trap 103a and a described LDMOS device 301 forms the drift region, drain region 205 of a described LDMOS device 301.
In described the 2nd P type trap 103, be formed with the source region 203 of described the 2nd LDMOS device 302; On described the 2nd P type trap 103, be coated with the grid 204 of described the 2nd LDMOS device 302, the region for the raceway groove of described the 2nd LDMOS device 302 of formation by these grid 204 overlay areas of described the 2nd P type trap 103; The drain region 206 of described the 2nd LDMOS device 302 is formed in described the second N-type injection region 102, and described the second N-type injection region 102 that is positioned at 206, the drain region of described the 2nd P type trap 103 and described the 2nd LDMOS device 302 forms the drift region, drain region 205 of described the 2nd LDMOS device 302.
In top plan view, the domain structure of described current sampling circuit is:
A described LDMOS device 301 is positioned at centre position, in the middle of the source region 210 of a described LDMOS device 301 is centered around by an end to end grid 209 that is closed figures structure.In the embodiment of the present invention, the closed figures structure of the grid 209 of a described LDMOS device 301 is racetrack shape, certainly also can replace by ring-type or other closed figures.
The drift region, drain region 205 of a described LDMOS device 301 is the grid 209 of strip structure and a described LDMOS device 301 and source region all in the drift region, drain region 205 in a described LDMOS device 301, in the both sides of the drift region, drain region 205 of a described LDMOS device 301, is two drain regions 206 that are strip structure of a described LDMOS device 301.
The long axis direction of the closed figures structure of the grid 209 of a described LDMOS device 301 is along the long side direction of the drift region, drain region 205 of a described LDMOS device 301; In the drift region, drain region 205 of the described LDMOS device 301 at the arc-shaped head place along long axis direction of the grid 209 of a described LDMOS device 301, be formed with a buffering withstand voltage zone 208, described buffering withstand voltage zone 208 is comprised of the described P type silicon substrate 101 that does not form described the second N-type injection region 102, and the drift region, drain region 205 of a described LDMOS device 301 of 208 outsides, described buffering withstand voltage zone is all comprised of described the second N-type injection region 102.
Described the 2nd LDMOS device 302 is connected in parallel and is formed by many strip elements, described in each, the source region 203 of strip element, drift region, drain region 205, drain region 206 are all identical strip structure, and the drain region 206 of two described strip elements of inner side shares with two bar shaped drain regions 206 of a described LDMOS device 301 respectively; From two bar shaped drain regions 206 of a described LDMOS device 301, start outward, described in each strip element according to: the arrangement mode in drain region 206, drift region, drain region 205, source region 203, drift region, drain region 205, drain region 206 is arranged successively outward.Described in each, the drift region, drain region 205 of the drift region, drain region 205 of strip element and a described LDMOS device 301 links together and is an end to end enclosed construction, this end to end enclosed construction is: one end of the drift region, drain region 205 of current strip element is connected with one end of the homonymy of the drift region, drain region 205 of last strip element in parallel, the other end of the drift region, drain region 205 of current strip element is connected with one end of the homonymy of the drift region, drain region 205 of next strip element in parallel, the drift region, drain region 205 of outermost two strip elements in last both sides is all also connected in same one end.The source region 203 that the described enclosed construction that drift region, described drain region 205 is connected to form is closed in described the 2nd LDMOS device 302 in inboard of described enclosed construction by the drain region of described the 2nd LDMOS device 302 206 is positioned at the outside of described enclosed construction.
The curved structure in junction of the described enclosed construction that described in each, drift region, drain region 205 of the drift region, drain region 205 of strip element and a described LDMOS device 301 forms, described in each, the grid 204 of strip element also links together according to the connected mode of drift region, drain region 205 described in each, also curved structure of the junction of the grid 204 of strip element described in each, described in each, described in corresponding each in the arc junction that bends towards described source region 203 1 sides of the grid 204 of strip element, in the drift region, drain region 205 of strip element, be formed with respectively a buffering withstand voltage zone 208, described buffering withstand voltage zone 208 is comprised of the described P type silicon substrate 101 that does not form described the second N-type injection region 102, and 208 outsides, described buffering withstand voltage zone other each described in the drift region, drain region 205 of strip element all by described the second N-type injection region 102, formed.
The grid 209 of a described LDMOS device 301 and the grid 204 of described the 2nd LDMOS device 302 are all comprised of polysilicon, forming between the grid 209 of a described LDMOS device 301 and the polysilicon of the grid 204 of described the 2nd LDMOS device 302 is independently, is linked together and is formed grid end 303 draw between the grid 209 of a described LDMOS device 301 and the grid 204 of described the 2nd LDMOS device 302 by metal connecting line.
Described grid 204 and 209 and described drain region 206 between drift region, described drain region 205 above be formed with an oxidation separation layer 105, described grid 204 and 209 polysilicon also extend on described oxidation separation layer 105, and extension be the polysilicon field plate of close source region one side.On described oxidation separation layer 105 of the side near described drain region 206, be also formed with another polysilicon field plate 207.The grid 204 of described the 2nd LDMOS device 302 and described polysilicon field plate 207 are all also enclosed construction, respectively identical around structure with the outside of drift region, described drain region 205 and inner side edge edge.
As shown in Figure 5, be the sectional structure chart along the device of the AA line in Fig. 4; The cross-section structure that has shown a strip element of described the 2nd LDMOS device 302.
Described drain region 206 is comprised of the described N+ district 107 being formed in the second N-type injection region 102; Described source region 203 forms by being formed at described the 2nd P type trap 103 Zhong N+ districts 106, in described the 2nd P type trap 103, also forms P+ district 108, described P+ district 108 link together with described N+ district 106 and together with form described source.
In drift region, described drain region 205, be positioned at described oxidation separation layer 105 belows and be formed with a P type injection region 104, when described drain region 206 adds high pressure, P type injection region 104 provides the electronics neutralization of hole more easily and in N-type drift region 205, and generation depletion region is withstand voltage to improve drain region 206.
In described source region, be also formed with P type injection region 104a for 203 times, described P type injection region 104a and described P type injection region 104 keep certain distance.Described grid 204 and the polysilicon field plate extending to form thereof can cover described P type injection region 104a and described P type injection region 104.Described polysilicon field plate 207 near drain region 206 also covers described P type injection region 104.
Also comprise an interlayer film 109, described interlayer film 109 all covers the polycrystalline substance of device, as grid 204 as described in having covered, polysilicon field plate 207,203He drain region, source region 206 and as described in an oxidation separation layer 105.In described interlayer film 109, being formed with contact hole is connected with described grid 204, polysilicon field plate 207,203He drain region, source region 206 respectively.In described interlayer film 109, be formed with metal level.Finally draw by metal 111 in described source region 203, and draw by metal 112 in described drain region 207.Side at described metal 111 is also formed with Metal field plate 113, and described Metal field plate 113 is connected with described grid 204; Described Metal field plate 113 and described grid 204 connect together, and have both formed metal field version, again because reduce resistance with grid parallel connection.Described polysilicon field plate 207 is also connected with described metal 112.
As shown in Figure 6, be the sectional structure chart along the device of the BB line in Fig. 4; A strip element of described the 2nd LDMOS device 302 and the cross-section structure of a described LDMOS device 301 have been shown.
The structure of described the 2nd LDMOS device 302 and as shown in Figure 5 identical.
The structure of a described LDMOS device 301 is:
The drain region 206 of described drain region 206 and described the 2nd LDMOS device 302 shares.By the described N+ district 107 being formed in the second N-type injection region 102, formed; Described source region 210 forms by being formed at a described P type trap 103a Zhong N+ district 106a, in described the 2nd P type trap 103a, also forms P+ district, GaiP+ district link together with described N+ district 106a and together with form source.
In described source region, be also formed with P type injection region 104b for 210 times, described P type injection region 104b and described P type injection region 104 keep certain distance.Described grid 209 and the polysilicon field plate extending to form thereof can cover described P type injection region 104b and described P type injection region 104.
Finally also draw by metal level in described source region 210, and the side of drawing metal level in described source region 210 is also formed with Metal field plate 113a, and described Metal field plate 113a is connected with described grid 209; Described Metal field plate 113a and described grid 209 connect together, and have both formed metal field version, again because reduce resistance with grid parallel connection.
As shown in Figure 7, it is respectively the sectional structure chart along the device of the CC line in Fig. 4, can find out, described buffering withstand voltage zone 208 is comprised of the described P type silicon substrate 101 that does not form described the second N-type injection region 102, and 208 outsides, described buffering withstand voltage zone other each described in the drift region, drain region 205 of strip element all by described the second N-type injection region 102, formed.The described P type injection region 104 being formed in the drift region, described drain region 205 of the 208 weeks sides in described buffering withstand voltage zone all extends in described buffering withstand voltage zone 208.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (6)
1. a current sampling circuit of realizing with LDMOS device, it is characterized in that: current sampling circuit comprises the 2nd LDMOS device of a LDMOS device that current sample is used and electric current contrast use, and the grid of a described LDMOS device and described the 2nd LDMOS device connects altogether, drain terminal connects altogether, source separately picks out;
On P type silicon substrate, be formed with one first N-type injection region, the 2nd P type trap by a P type trap of a described LDMOS device and described the 2nd LDMOS device of described the first N-type injection region is all surrounded, and a described P type trap and described the 2nd P type trap are kept apart completely by PN junction mutually;
In a described P type trap, be formed with the source region of a described LDMOS device; On a described P type trap, be coated with the grid of a described LDMOS device, the region for the raceway groove of the described LDMOS device of formation by this grid overlay area of a described P type trap; The drain region of a described LDMOS device is formed in the second N-type injection region, is positioned at the drift region, drain region that described the second N-type injection region between the drain region of a described P type trap and a described LDMOS device forms a described LDMOS device;
In described the 2nd P type trap, be formed with the source region of described the 2nd LDMOS device; On described the 2nd P type trap, be coated with the grid of described the 2nd LDMOS device, the region for the raceway groove of described the 2nd LDMOS device of formation by this grid overlay area of described the 2nd P type trap; The drain region of described the 2nd LDMOS device is formed in described the second N-type injection region, is positioned at the drift region, drain region that described the second N-type injection region between the drain region of described the 2nd P type trap and described the 2nd LDMOS device forms described the 2nd LDMOS device;
In top plan view, the domain structure of described current sampling circuit is:
A described LDMOS device is positioned at centre position, in the middle of the source region of a described LDMOS device is centered around by an end to end grid that is closed figures structure, the drift region, drain region of a described LDMOS device is strip structure, and the grid of a described LDMOS device and source region be all in the drift region, drain region in a described LDMOS device, in the both sides of the drift region, drain region of a described LDMOS device, be two drain regions that are strip structure of a described LDMOS device;
Described the 2nd LDMOS device is connected in parallel and is formed by many strip elements, described in each, the source region of strip element, drift region, drain region, drain region are all identical strip structure, and the drain region of two described strip elements of inner side shares with two bar shaped drain regions of a described LDMOS device respectively; From two bar shaped drain regions of a described LDMOS device, start outward, described in each, strip element is arranged successively outward according to: the arrangement mode in drain region, drift region, drain region, source region, drift region, drain region, drain region; Described in each, the drift region, drain region of the drift region, drain region of strip element and a described LDMOS device links together and is an end to end enclosed construction, and the drain region of described the 2nd LDMOS device being closed in to the inboard of described enclosed construction, the source region of described the 2nd LDMOS device is positioned at the outside of described enclosed construction.
2. the current sampling circuit of realizing with LDMOS device as claimed in claim 1, is characterized in that: the closed figures structure of the grid of a described LDMOS device is ring-type.
3. the current sampling circuit of realizing with LDMOS device as claimed in claim 2, it is characterized in that: the closed figures structure of the grid of a described LDMOS device is racetrack shape, and the long axis direction of the closed figures structure of the grid of a described LDMOS device is along the long side direction of the drift region, drain region of a described LDMOS device; In the drift region, drain region of the described LDMOS device at the arc-shaped head place along long axis direction of the grid of a described LDMOS device, be formed with a buffering withstand voltage zone, described buffering withstand voltage zone is comprised of the described P type silicon substrate that does not form described the second N-type injection region, and the drift region, drain region of a described LDMOS device of outside, described buffering withstand voltage zone is all comprised of described the second N-type injection region.
4. the current sampling circuit of realizing with LDMOS device as claimed in claim 1, is characterized in that: the curved structure in junction of the described enclosed construction that described in each, drift region, drain region of the drift region, drain region of strip element and a described LDMOS device forms, described in each, the grid of strip element also links together according to the connected mode of drift region, drain region described in each, also curved structure of the junction of the grid of strip element described in each, described in each, described in corresponding each in the arc junction that bends towards described source region one side of the grid of strip element, in the drift region, drain region of strip element, be formed with respectively a buffering withstand voltage zone, described buffering withstand voltage zone is comprised of the described P type silicon substrate that does not form described the second N-type injection region, and outside, described buffering withstand voltage zone other each described in the drift region, drain region of strip element all by described the second N-type injection region, formed.
5. the current sampling circuit of realizing with LDMOS device as claimed in claim 1 or 2 or 3 or 4, it is characterized in that: described the first N-type injection region is a part for described the second N-type injection region, and described the first N-type injection region is by extending to source region one side of a described LDMOS device and described the 2nd LDMOS device and described the second N-type injection region that a described P type trap and described the 2nd P type trap are surrounded completely being formed.
6. the current sampling circuit of realizing with LDMOS device as claimed in claim 1 or 2 or 3 or 4, it is characterized in that: the grid of the grid of a described LDMOS device and described the 2nd LDMOS device is all comprised of polysilicon, forming between the grid of a described LDMOS device and the polysilicon of the grid of described the 2nd LDMOS device is independently, between the grid of a described LDMOS device and the grid of described the 2nd LDMOS device, by metal connecting line, links together.
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| CN104714073B (en) * | 2013-12-17 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | The current sampling circuit realized with LDMOS device |
| CN104752518B (en) * | 2013-12-31 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | Isolated form high withstand voltage FET |
| CN111710720B (en) * | 2020-07-10 | 2022-07-19 | 杰华特微电子股份有限公司 | Lateral double diffused transistor and method of fabricating the same |
| CN113394291A (en) * | 2021-04-29 | 2021-09-14 | 电子科技大学 | Lateral power semiconductor device |
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