CN103035279B - Transmission line structure capable of eliminating DDR3 (Double Data Rate 3) load difference influence as well as forming method and internal storage structure thereof - Google Patents
Transmission line structure capable of eliminating DDR3 (Double Data Rate 3) load difference influence as well as forming method and internal storage structure thereof Download PDFInfo
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Abstract
The invention provides a transmission line structure capable of eliminating DDR3 (Double Data Rate 3) load difference influence as well as a forming method and an internal storage structure thereof. The forming method comprises the following steps of: determining intrinsic parameters of a first-type transmission line and a second-type transmission line; determining first equivalent parameters of the first-type transmission line according to the intrinsic parameters of the first-type transmission line and the load capacity of a first load; determining second equivalent parameters of the second-type transmission line according to the intrinsic parameters of the second-type transmission line and the load capacity of a second load; determining the target delay of the first-type transmission line under the first load according to the first equivalent parameters; regulating the second equivalent parameters to third first equivalent parameters, so as to enable the equivalent delay of the second-type transmission line under the second load to be matched with the target delay of the first-type transmission line under the first load; and forming a basic transmission line and a special transmission line respectively based on the first equivalent parameters and the third equivalent parameters, wherein the basic transmission line and the special transmission line constitute the transmission line structure. By utilizing the technical scheme, the time sequence integrality of signals in signal transmission is improved.
Description
Technical field
The present invention relates to memory techniques field, particularly a kind of transmission line structure and formation method, internal storage structure eliminating the impact of DDR3 load difference.
Background technology
Internal memory is one of parts important in computing machine, and in computing machine, the operation of all programs is all carried out in internal memory, and therefore the performance quality of internal memory is very large for the impact of computing machine.Internal memory generally adopts semiconductor memory cell, comprises random access memory (RAM), ROM (read-only memory) (ROM) and high-speed cache (Cache).Wherein, random access memory is most important storer, and the CPU of computing machine therefrom can read data, also can write data, but when turning off the computer, the data be stored in wherein will be lost.Along with the development of technology, the access speed of random access memory improving constantly, its capacity is also in continuous increase.
Nowadays, synchronous DRAM (Synchronous Dynamic Random AccessMemory, SDRAM) in field widespread uses such as computing machine, personal communication, consumption electronic products (smart card, digital camera, multimedia player), wherein synchronously refer to that memory operation needs synchronous clock, the inner transmission of order and the transmission of data are all benchmark with synchronous clock; Dynamically refer to that storage array needs constantly to refresh to ensure that data are not lost; Refer to that data are not linearly store successively at random, but free assigned address carries out reading and writing data.At present, SDRAM has developed into forth generation, namely usually said DDR3 SDRAM, and compared to last generation product DDR2 SDRAM, DDR3 SDRAM has higher Operating ettectiveness and lower voltage.
But in prior art, along with the frequency of DDR3 SDRAM high-speed interface signal constantly increases, the requirement of the sequential integrality (memory operation namely mentioned above needs synchronous clock, and the inner transmission of order and the transmission of data are all benchmark with synchronous clock) of docking port signal is more and more stricter.Usually in the transmission of the address/command/control/clock signal of DDR3, what adopt is that the Signal transmissions that sent by Memory Controller Hub of transmission line structure that a kind of string pushes away form is in memory modules, but the signal load number (i.e. the number of storer) driven due to different types of signal is different, such as, the load that address/command signal drives is more, and control/clock signal drive load less, such load difference will cause the difference of signal transmission delay deflection.
More technical schemes about internal memory and transmission line structure can be the U.S. Patent application file of US2007263475A1 with reference to publication number: the transmission (Using Common Mode Differential Data Signals OfDDR2 SDRAM For Control Signal Transmission) using the data-signal control signal of the DDR2 SDRAM of common-mode differential, but do not solve the problem equally.
Summary of the invention
The problem that the present invention solves is at Memory Controller Hub in memory modules transmission signal process, eliminates the transmission delay deflection difference that transmission line causes due to the load difference of variety classes signal driving, improves the sequential integrality of signal in Signal transmissions.
For solving the problem, the embodiment of the present invention provides a kind of formation method eliminating the transmission line structure of DDR3 load difference impact, described transmission line structure comprises first kind transmission line and Equations of The Second Kind transmission line, be suitable for signal transmission under the first load and the second load respectively, described first load is greater than described second load; Comprise: the intrinsic parameters determining described first kind transmission line and Equations of The Second Kind transmission line; The first equivalent parameters of described first kind transmission line is determined based on the intrinsic parameters of described first kind transmission line and the load capacitance of described first load; The second equivalence ginseng of described Equations of The Second Kind transmission line is determined based on the intrinsic parameters of described Equations of The Second Kind transmission line and the load capacitance of described second load; The target delay of described first kind transmission line under the first load is determined according to described first equivalent parameters; Adjust described second equivalent parameters to the 3rd equivalent parameters, match to make the equivalent delay of described Equations of The Second Kind transmission line under the second load and the target delay of described first kind transmission line under the first load; Form basic transmission line and special transmission line based on described first equivalent parameters and described 3rd equivalent parameters respectively, described basic transmission line and special transmission line form described transmission line structure.
Alternatively, describedly determine that the intrinsic parameters of described first kind transmission line and Equations of The Second Kind transmission line comprises: the intrinsic parameters determining described first kind transmission line according to the unit inductance values of described first kind transmission line and unit capacitance values; The intrinsic parameters of described Equations of The Second Kind transmission line is determined according to the unit inductance values of described Equations of The Second Kind transmission line and unit capacitance values.
Alternatively, determine that the first equivalent parameters of described first kind transmission line comprises based on the intrinsic parameters of described first kind transmission line and the load capacitance of described first load: the first equivalent parameters determining described first kind transmission line according to the unit inductance values of described first kind transmission line and the load capacitance of unit capacitance values and described first load.
Alternatively, determine that the second equivalent parameters of described Equations of The Second Kind transmission line comprises based on the intrinsic parameters of described Equations of The Second Kind transmission line and the load capacitance of described second load: the second equivalent parameters determining described Equations of The Second Kind transmission line according to the unit inductance values of described Equations of The Second Kind transmission line and the load capacitance of unit capacitance values and described second load.
Alternatively, describedly determine that the target delay of described first kind transmission line under the first load comprises according to described first equivalent parameters: determine the target delay of described first kind transmission line under the first load according to the length of described first kind transmission line and the transmission speed of signal on described first kind transmission line.
Alternatively, described second equivalent parameters of described adjustment, to the 3rd equivalent parameters, comprises to make the equivalent delay of described Equations of The Second Kind transmission line under the second load and the target delay of described first kind transmission line under the first load match: the target delay under the first load matches with the equivalent delay making described Equations of The Second Kind transmission line under the second load and described first kind transmission line to adjust the parameter of described Equations of The Second Kind transmission line.
Alternatively, the parameter of described adjustment described Equations of The Second Kind transmission line: adjust the line length of described Equations of The Second Kind transmission line or live width or line thick, be changing into the 3rd equivalent parameters to make described second equivalent parameters.
Alternatively, the parameter of the described Equations of The Second Kind transmission line of described adjustment comprises: the material changing the base material of printed board, to make described second equivalent parameters be changing into the 3rd equivalent parameters, wherein said printed board carries described Equations of The Second Kind transmission line.
Alternatively, described respectively based on described first equivalent parameters with described 3rd equivalent parameters forms basic transmission line and special transmission line specifically comprises: under the first load, to form basic transmission line according to described first equivalent parameters; Under the second load, form special transmission line according to described 3rd equivalent parameters.
Alternatively, described first kind transmission line is used for being used for DDR3 SDRAM transmit clock signal and control signal to DDR3 SDRAM transport address signal and command signal, described Equations of The Second Kind transmission line.
The embodiment of the present invention additionally provides a kind of transmission line structure eliminating the impact of DDR3 load difference, described transmission line structure comprises first kind transmission line and Equations of The Second Kind transmission line, be suitable for signal transmission under the first load and the second load respectively, described first load is greater than described second load; In described transmission line structure, under the first load, described first kind transmission line is the basic transmission line formed based on the first equivalent parameters; Under the second load, described Equations of The Second Kind transmission line is the special transmission line formed based on the 3rd equivalent parameters, and the equivalent delay of wherein said special transmission line signal transmission under the second load and the target delay of described basic transmission line signal transmission under the first load match.
Alternatively, the first equivalent parameters of described basic transmission line determines according to the unit inductance values of described first kind transmission line and the load capacitance of unit capacitance values and described first load.
Alternatively, the 3rd equivalent parameters of described special transmission line be according to adjustment after the unit inductance values of described Equations of The Second Kind transmission line and the load capacitance of unit capacitance values and described second load determine.
The embodiment of the present invention additionally provides a kind of internal storage structure, comprises Memory Controller Hub, memory modules and above-mentioned transmission line structure; Wherein said Memory Controller Hub is by memory modules described in the first kind transmission line in described transmission line structure and the control and management of Equations of The Second Kind transmission line.
Alternatively, described Memory Controller Hub by described first kind transmission line to described memory modules transport address signal and command signal; Described Memory Controller Hub by described Equations of The Second Kind transmission line to described memory modules transmit clock signal and control signal.
Alternatively, described memory modules comprises multiple storer, and wherein said storer is synchronous DRAM or dynamic RAM.
Compared with prior art, technical solution of the present invention has following beneficial effect: for the first kind transmission line of signal transmission and Equations of The Second Kind transmission line under the first load and the second load respectively, wherein the first load is greater than the second load; The transmission delay of its signal transmission is determined according to the first equivalent parameters of the first kind transmission line of signal transmission under described first load, and as target delay; Second equivalent parameters of adjustment Equations of The Second Kind transmission line of signal transmission under described second load, to the 3rd equivalent parameters, makes the equivalent delay of signal transmission and described target delay match; Basic transmission line is set according to the first equivalent parameters, according to the 3rd equivalent optimum configurations special transmission line, forms transmission line structure, thus eliminate the transmission delay deflection difference that transmission line causes due to the load difference of variety classes signal driving.
Accompanying drawing explanation
Fig. 1 is the structural representation of the specific embodiment of a kind of internal storage structure of the present invention;
Fig. 2 is a kind of schematic flow sheet eliminating the embodiment of the formation method of the transmission line structure of DDR3 load difference impact of the present invention;
Fig. 3 is the schematic diagram of the specific embodiment of the RLCG parameter model of first kind transmission line or Equations of The Second Kind transmission line in the transmission line structure of elimination DDR3 load difference of the present invention impact.
Embodiment
Inventor finds in the prior art, usually in the transmission of the address/command/control/clock signal of DDR3 SDRAM, what adopt is the transmission line structure that a kind of string pushes away form, the Signal transmissions sent by Memory Controller Hub is in memory modules, but the signal load number (i.e. the number of storer) driven due to different types of signal is different, such as, the load that address/command signal drives is more, and control/clock signal drive load less, such load difference will cause the difference of signal transmission delay deflection.
For the problems referred to above, inventor is through research, provide a kind of transmission line structure and the formation method of eliminating the impact of DDR3 load difference, the transmission delay deflection difference that transmission line causes due to the load difference of variety classes signal driving can be eliminated by the transmission line structure of the technical program.
On this basis, additionally provide a kind of internal storage structure, comprise Memory Controller Hub, internal memory and above-mentioned transmission line structure; Wherein, described Memory Controller Hub by memory modules described in the first kind transmission line in described transmission line structure and the control and management of Equations of The Second Kind transmission line, thus eliminates the transmission delay deflection difference that transmission line causes due to the load difference of variety classes signal driving.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
The structural representation of the specific embodiment of of the present invention a kind of internal storage structure as shown in Figure 1.As shown in Figure 1, described internal storage structure comprises Memory Controller Hub 21, memory modules 22a, 22b and first kind transmission line 23a and Equations of The Second Kind transmission line 23b.In the present embodiment, described memory modules 22a comprises N number of storer (such as, synchronous DRAM or dynamic RAM), described memory modules 22b also comprises N number of storer (such as synchronous DRAM or dynamic RAM).In actual applications, usual N value is 9.
Particularly, described Memory Controller Hub 21 sends different types of signal to memory modules 22a, 22b, and these signals at least comprise address signal, control signal, command signal and clock signal.Wherein, by described first kind transmission line 23a to described memory modules 22a, 22b transport address signal and command signal, by described Equations of The Second Kind transmission line 23b to described memory modules 22a transmission of control signals and clock signal.Can find out, the load of described first kind transmission line 23a in signal transmission (address/command signal) process is 2N storer, and the load of described Equations of The Second Kind transmission line 23b in signal transmission (control/clock signal) process is N number of storer.It will be appreciated by those skilled in the art that, because first kind transmission line 23a and Equations of The Second Kind transmission line 23b is signal transmission under different loads, can cause like this time storer (such as storer 1 and storer n+1) on the upper same position of signal arrival memory modules 22a, 22b and produce different delay deflections, thus have impact on signal sequence integrality in Signal transmissions.
For this reason in the invention process, for the different loads that transmission line carries in transmission signal process, different transmission lines is set respectively, by described first kind transmission line 23a as basic transmission line, transport address/control signal, using described Equations of The Second Kind transmission line 23b as special transmission line, transmission command/clock signal, with the delay deflection avoiding different types of signal to reach the storer on memory modules on same position.The method specifically arranging different transmission lines describes in the embodiment described in Fig. 2.
Of the present invention a kind of schematic flow sheet eliminating the embodiment of the formation method of the transmission line structure of DDR3 load difference impact as shown in Figure 2.With reference to figure 2, the formation method of described transmission line structure comprises:
Step S1: the intrinsic parameters determining described first kind transmission line and Equations of The Second Kind transmission line.
Particularly, in conjunction with the schematic diagram of the specific embodiment of the RLCG parameter model of first kind transmission line or Equations of The Second Kind transmission line in the transmission line structure with reference to the elimination DDR3 load difference impact shown in figure 3.This reference model comprises resistance 11 (R), inductance 12 (L), electric capacity 13 (C) and conductance 14 (G), described resistance 11 (R) and inductance 12 (L) are resistance and the inductance of transmission line itself, and described electric capacity 13 (C) and conductance 14 (G) are transmission line electric capacity over the ground and conductance; Wherein said resistance 11 (R) and inductance 12 (L) series connection, described electric capacity 13 (C) and conductance 14 (G) parallel connection.Further, it will be understood by those skilled in the art that transmission line also only can carry out modeling, such as Ideal Transmission Line with electric capacity (C) and inductance (L).Described Ideal Transmission Line is a kind of loss-free transmission line, and its energy is just changed between inductance/capacitance (L/C), and the signal of transmission above-the-line promotion does not distort, and signal is not attenuated in transmitting procedure.
In the present embodiment, for Ideal Transmission Line, describedly determine that the intrinsic parameters of described first kind transmission line and Equations of The Second Kind transmission line comprises: the intrinsic parameters 1) determining described first kind transmission line according to the unit inductance values of described first kind transmission line and unit capacitance values; 2) intrinsic parameters of described Equations of The Second Kind transmission line is determined according to the unit inductance values of described Equations of The Second Kind transmission line and unit capacitance values.It should be noted that, in embodiments of the present invention, the unit inductance values of described first kind transmission line or Equations of The Second Kind transmission line and unit capacitance values be according to above-mentioned RLCG parameter model determine that the length of the inductance value of first kind transmission line or Equations of The Second Kind transmission line and capacitance and described first kind transmission line or Equations of The Second Kind transmission line is determined.In other words, the inductance value of described first kind transmission line or Equations of The Second Kind transmission line and capacitance are evenly distributed in the length of first kind transmission line or Equations of The Second Kind transmission line, unit inductance values and the unit capacitance values of described first kind transmission line or Equations of The Second Kind transmission line can be obtained.
In actual applications, if described first kind transmission line and Equations of The Second Kind transmission line are not Ideal Transmission Line, namely, when the reference model of transmission line comprises resistance, inductance, electric capacity and conductance, so determine that the unitary resistance value according to first kind transmission line, unit inductance values, unit capacitance values and Their unit conductance value are determined by the intrinsic parameters of described first kind transmission line; Correspondingly, determine that the unitary resistance value according to Equations of The Second Kind transmission line, unit inductance values, unit capacitance values and Their unit conductance value are determined by the intrinsic parameters of described Equations of The Second Kind transmission line and Equations of The Second Kind transmission line.It should be noted that, according to above-mentioned, the unitary resistance value of wherein said first kind transmission line or Equations of The Second Kind transmission line and Their unit conductance value also can determine that the unit inductance values of described first kind transmission line or Equations of The Second Kind transmission line and the method for unit capacitance values obtain, do not repeat them here.
Step S2: the first equivalent parameters determining described first kind transmission line based on the intrinsic parameters of described first kind transmission line and the load capacitance of described first load.
Particularly, in the present embodiment, because described first kind transmission line is suitable for signal transmission under the first load, therefore, on the basis of intrinsic parameters determining described first kind transmission line, also need to determine under the load capacitance of described first load, the first equivalent parameters of described first kind transmission line.Wherein, the load capacitance of described first load refers to the capacitance of the storer (storer 1 such as shown in Fig. 1, storer 2 ..., storer n+1 ..., storer 2n) that described first kind transmission line carries in transmission signal process.
Equally, for Ideal Transmission Line, this step comprises: the first equivalent parameters determining described first kind transmission line according to the unit inductance values of described first kind transmission line and the load capacitance of unit capacitance values and described first load.Particularly, as described in above-mentioned steps S1, the intrinsic parameters of described first kind transmission line can be determined according to the unit inductance values of described first kind transmission line and unit capacitance values; Further, according to the length of described first kind transmission line, also need to determine, by the average load capacitance of the load capacitance of described first load in the length of described first kind transmission line, namely to determine the load capacitance of the first load that the first kind transmission line of unit length carries.The first equivalent parameters of described first kind transmission line is determined based on the above-mentioned intrinsic parameters of the described first kind transmission line determined and the load capacitance of described first load.
Step S3: the second equivalent parameters determining described Equations of The Second Kind transmission line based on the intrinsic parameters of described Equations of The Second Kind transmission line and the load capacitance of described second load.Wherein, the load capacitance of described second load refers to the capacitance of the storer (storer 1 such as shown in Fig. 1, storer 2 ..., storer n) that described Equations of The Second Kind transmission line carries in transmission signal process.
Particularly, in the present embodiment, equally for Ideal Transmission Line, the second equivalent parameters of described Equations of The Second Kind transmission line is determined according to the unit inductance values of described Equations of The Second Kind transmission line and the load capacitance of unit capacitance values and described second load.The specific implementation of this step can with reference to the implementation process of above-mentioned steps S2, and therefore not to repeat here.
Step S4: determine the target delay of described first kind transmission line under the first load according to described first equivalent parameters.
Particularly, in the present embodiment, this step comprises: determine the target delay of described first kind transmission line under the first load according to the length of described first kind transmission line and the transmission speed of signal on described first kind transmission line.Wherein, the transmission speed of signal on described first kind transmission line can be determined according to the first equivalent parameters of described first kind transmission line, then the length of described first kind transmission line just can be obtained the target delay of described first kind transmission line under the first load divided by this transmission speed.
Step S5: adjust described second equivalent parameters to the 3rd equivalent parameters, matches to make the equivalent delay of described Equations of The Second Kind transmission line under the second load and the target delay of described first kind transmission line under the first load.
Particularly, in the present embodiment, first, the equivalent delay of described Equations of The Second Kind transmission line under the second load is determined according to described second equivalent parameters.Can be specifically: determine the target delay of described Equations of The Second Kind transmission line under the second load according to the length of described Equations of The Second Kind transmission line and the transmission speed of signal on described Equations of The Second Kind transmission line.Wherein, the transmission speed of signal on described Equations of The Second Kind transmission line can be determined according to the second equivalent parameters of described Equations of The Second Kind transmission line, then the length of described Equations of The Second Kind transmission line just can be obtained the equivalent delay of described Equations of The Second Kind transmission line under the second load divided by this transmission speed.
Then, the target delay under the first load matches with the equivalent delay making described Equations of The Second Kind transmission line under the second load and described first kind transmission line to adjust the parameter of described Equations of The Second Kind transmission line.
Particularly, the parameter adjusting described Equations of The Second Kind transmission line comprises: adjust the line length of described Equations of The Second Kind transmission line, live width, line are thick, be changing into the 3rd equivalent parameters to make described second equivalent parameters.In embodiments of the present invention, the load capacitance due to described second load is less than the load capacitance of described first load, and this load capacitance is all determined value.Therefore, by adjust the line length of described Equations of The Second Kind transmission line, live width, line thick in a kind of parameter or many kinds of parameters, described second equivalent parameters is made to be changing into the 3rd equivalent parameters, described 3rd equivalent parameters and described first equivalent parameters match, and the equivalent delay of the described Equations of The Second Kind transmission line determined based on described 3rd equivalent parameters like this under the second load and the target delay of described first kind transmission line under the first load match.
Further, it will be appreciated by those skilled in the art that in practical application, the base material carrying the different printed boards of described transmission line structure also can have an impact for transmission line equivalent parameters under different loads.Therefore, can also by changing the second equivalent parameters that the material of described base material make described Equations of The Second Kind transmission line under described second load and first equivalent parameters of described first kind transmission line under the first load matches, thus the equivalent delay of described Equations of The Second Kind transmission line under the second load and the target delay of described first kind transmission line under the first load match.
Step S6: form basic transmission line and special transmission line based on described first equivalent parameters and described 3rd equivalent parameters respectively, described basic transmission line and special transmission line form described transmission line structure.
Particularly, in the present embodiment, this step comprises: 1) under the first load, forms basic transmission line according to described first equivalent parameters; 2) under the second load, special transmission line is formed according to described 3rd equivalent parameters.Compared with prior art, the technical program is for different load capacitances, basic transmission line and special transmission line are set respectively, first equivalent parameters of wherein said basic transmission line under the first load and the three equivalent match parameters of described special transmission line under the second load, thus described basic transmission line and the transmission delay of special transmission line in transmission signal process are matched, improve the sequential integrality of signal in Signal transmissions.
According to the method for above-mentioned formation transmission line structure, the embodiment of the present invention additionally provides a kind of transmission line structure eliminating the impact of DDR3 load difference, described transmission line structure comprises first kind transmission line and Equations of The Second Kind transmission line, be suitable for signal transmission under the first load and the second load respectively, described first load is greater than described second load; In described transmission line structure, under the first load, described first kind transmission line is the basic transmission line formed based on the first equivalent parameters; Under the second load, described Equations of The Second Kind transmission line is the special transmission line formed based on the 3rd equivalent parameters, and the equivalent delay of wherein said special transmission line signal transmission under the second load and the target delay of described basic transmission line signal transmission under the first load match.
Wherein, the first equivalent parameters of described basic transmission line determines according to the unit inductance values of described first kind transmission line and the load capacitance of unit capacitance values and described first load; 3rd equivalent parameters of described special transmission line be according to adjustment after the unit inductance values of described Equations of The Second Kind transmission line and the load capacitance of unit capacitance values and described second load determine.Concrete forming process can be described in reference diagram 2 embodiment, therefore not to repeat here.
In sum, according to internal storage structure, transmission line structure and formation method that the technical program provides, the transmission delay deflection difference that transmission line causes due to the load difference of variety classes signal driving can be eliminated, improve the sequential integrality of signal in Signal transmissions.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (11)
1. eliminate the formation method of the transmission line structure of DDR3 load difference impact for one kind, described transmission line structure comprises first kind transmission line and Equations of The Second Kind transmission line, be suitable for signal transmission under the first load and the second load respectively, described first load is greater than described second load; It is characterized in that, comprising:
Determine the intrinsic parameters of described first kind transmission line and Equations of The Second Kind transmission line, particularly, determine the intrinsic parameters of described first kind transmission line according to the unitary resistance value of described first kind transmission line, unit inductance values, unit capacitance values and Their unit conductance value, determine the intrinsic parameters of described Equations of The Second Kind transmission line according to the unitary resistance value of described Equations of The Second Kind transmission line, unit inductance values, unit capacitance values and Their unit conductance value;
The first equivalent parameters of described first kind transmission line is determined based on the intrinsic parameters of described first kind transmission line and the load capacitance of described first load;
The second equivalent parameters of described Equations of The Second Kind transmission line is determined based on the intrinsic parameters of described Equations of The Second Kind transmission line and the load capacitance of described second load;
The target delay of described first kind transmission line under the first load is determined according to described first equivalent parameters;
Adjust described second equivalent parameters to the 3rd equivalent parameters, match to make the equivalent delay of described Equations of The Second Kind transmission line under the second load and the target delay of described first kind transmission line under the first load;
Form basic transmission line and special transmission line based on described first equivalent parameters and described 3rd equivalent parameters respectively, described basic transmission line and special transmission line form described transmission line structure.
2. the formation method of transmission line structure according to claim 1, it is characterized in that, describedly determine that the target delay of described first kind transmission line under the first load comprises according to described first equivalent parameters: determine the target delay of described first kind transmission line under the first load according to the length of described first kind transmission line and the transmission speed of signal on described first kind transmission line.
3. the formation method of transmission line structure according to claim 1, it is characterized in that, described second equivalent parameters of described adjustment, to the 3rd equivalent parameters, comprises to make the equivalent delay of described Equations of The Second Kind transmission line under the second load and the target delay of described first kind transmission line under the first load match: the target delay under the first load matches with the equivalent delay making described Equations of The Second Kind transmission line under the second load and described first kind transmission line to adjust the parameter of described Equations of The Second Kind transmission line.
4. the formation method of transmission line structure according to claim 3, it is characterized in that, the parameter of described adjustment described Equations of The Second Kind transmission line comprises: adjust the line length of described Equations of The Second Kind transmission line or live width or line thick, be changing into the 3rd equivalent parameters to make described second equivalent parameters.
5. the formation method of transmission line structure according to claim 3, it is characterized in that, the parameter of the described Equations of The Second Kind transmission line of described adjustment comprises: the material changing the base material of printed board, to make described second equivalent parameters be changing into the 3rd equivalent parameters, wherein said printed board carries described Equations of The Second Kind transmission line.
6. the formation method of transmission line structure according to claim 1, is characterized in that, described respectively based on described first equivalent parameters with described 3rd equivalent parameters forms basic transmission line and special transmission line specifically comprises:
Under the first load, form basic transmission line according to described first equivalent parameters;
Under the second load, form special transmission line according to described 3rd equivalent parameters.
7. the formation method of transmission line structure according to claim 1, it is characterized in that, described first kind transmission line is used for being used for DDR3SDRAM transmit clock signal and control signal to DDR3SDRAM transport address signal and command signal, described Equations of The Second Kind transmission line.
8. eliminate a transmission line structure for DDR3 load difference impact, described transmission line structure comprises first kind transmission line and Equations of The Second Kind transmission line, is suitable for signal transmission under the first load and the second load respectively, and described first load is greater than described second load; It is characterized in that, in described transmission line structure, under the first load, described first kind transmission line is the basic transmission line formed based on the first equivalent parameters; Under the second load, described Equations of The Second Kind transmission line is the special transmission line formed based on the 3rd equivalent parameters, and the equivalent delay of wherein said special transmission line signal transmission under the second load and the target delay of described basic transmission line signal transmission under the first load match;
Wherein, determine the intrinsic parameters of described first kind transmission line according to the unitary resistance value of described first kind transmission line, unit inductance values, unit capacitance values and Their unit conductance value, determine the first equivalent parameters of described first kind transmission line based on the intrinsic parameters of described first kind transmission line and the load capacitance of described first load;
Determine the intrinsic parameters of described Equations of The Second Kind transmission line according to the unitary resistance value of described Equations of The Second Kind transmission line, unit inductance values, unit capacitance values and Their unit conductance value, determine the second equivalent parameters of described Equations of The Second Kind transmission line based on the intrinsic parameters of described Equations of The Second Kind transmission line and the load capacitance of described second load.
9. an internal storage structure, is characterized in that, comprises Memory Controller Hub, memory modules and transmission line structure as claimed in claim 8; Wherein said Memory Controller Hub is by memory modules described in the first kind transmission line in described transmission line structure and the control and management of Equations of The Second Kind transmission line.
10. internal storage structure according to claim 9, is characterized in that, described Memory Controller Hub by described first kind transmission line to described memory modules transport address signal and command signal; Described Memory Controller Hub by described Equations of The Second Kind transmission line to described memory modules transmit clock signal and control signal.
11. internal storage structures according to claim 9, is characterized in that, described memory modules comprises multiple storer, and wherein said storer is synchronous DRAM or dynamic RAM.
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