CN102765695B - Method of manufacturing wafer-level low-dimensional nano-structure based on self-focusing of electrostatic field singular-point - Google Patents
Method of manufacturing wafer-level low-dimensional nano-structure based on self-focusing of electrostatic field singular-point Download PDFInfo
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Abstract
The invention relates to a method of manufacturing a low-dimensional nano-structure and is used for solving the problems that existing orderly low-dimensional nano-structure is only produced in small area, the cost is high and the pollution is serious. The method of manufacturing a wafer-level low-dimensional nano-structure based on the self-focusing of an electrostatic field singular-point comprises the following steps of: firstly, obtaining a self-assembled physical substrate template of the low-dimensional nano-structure on a wafer-level silicon slice substrate by a photo-etching process and an etching process; secondly, putting the self-assembled physical substrate template on a magnetic control sputtering device target, and automatically depositing synthesized noble metal nano-particles onto a tip structure to obtain a noble metal film; and at last, annealing. According to the manufacturing method provided by the invention, the synthesized nano-particles are used, and a traditional MEMS (micro electro mechanical system) processing technology is adopted, so that the wafer-level large-scale low-dimensional nanometer material structure with low cost, zero pollution, high reliability and orderly height is obtained; and the manufacturing method can be widely suitable for manufacturing the orderly low-dimensional nano-structure in large area.
Description
Technical field
The present invention relates to the preparation method of low-dimensional nano structure, be specially a kind of preparation method of the low-dimensional nano-structure based on the self-focusing of electrostatic field singular point.
Background technology
Ordered nano self-assembled structures has become one of the emphasis and focus of research both at home and abroad in recent years, and scientific research personnel have studied the synthesis technique of the low-dimensional nano structure ordered fabrications such as nano particle, quantum dot, nano wire.At present, orderly low-dimensional nano structure has been widely applied to the every field such as micro-nano electronics, photoelectron, biochemical sensor, and has shown tempting prospect and considerable society, economic worth.
Along with low-dimensional nano structure and device progressively to highly integrated and practical development, at present low-dimensional nanoassemble technique is all emphasized to be applied as guiding, to a great extent low-dimensional nanoassemble technology is had higher requirement, this not only needs the low-dimensional nanoassemble technique guaranteeing that low cost, high-sequential, large area manufacture, compatibility that also will be good with traditional MEMS processing technology.But at present in order the preparation method of low-dimensional nano structure can only small size manufacture, greatly waste resource and cost is higher, and low with traditional MEMS processing technology compatibility; Adopt chemical synthesis process can remain a large amount of chemical refuses during preparation simultaneously; and preparation cost is higher; and the earth that we depend on for existence is faced with severe environmental issue; Everybody is responsible for protection of the environment, so the research mission that research cost is low, consumptive material is few, the nanosecond science and technology of no pollution also become our each earth sons and daughters.
Summary of the invention
The present invention in order to solve existing orderly low-dimensional nano structure can only small size manufacture, cost high, seriously polluted and with the problem of traditional MEMS processing technology poor compatibility, provide a kind of preparation method of the low-dimensional nano-structure based on the self-focusing of electrostatic field singular point.
The present invention adopts following technical scheme to realize: based on the preparation method of the low-dimensional nano-structure of electrostatic field singular point self-focusing, comprise the steps:
(1), the preparation (its process chart is as shown in Figure 1) of low-dimensional nano structure physics substrate template:
Step one: the wafer level silicon chip substrate (1) that cut-off footpath is 3inch ~ 6inch, thickness is 300 ~ 600 μm, (thermal oxidation method of silicon refers to: silicon and the gas containing oxidation material to adopt thermal oxidation method, such as steam and oxygen at high temperature carry out chemical reaction, and produce the silica membrane of one deck densification at silicon chip surface) all grow at the front and back of wafer level silicon chip substrate the SiO that a layer thickness is 300nm ~ 500nm
2mask layer.
Step 2: the front of wafer level silicon chip substrate is carried out surface cleaning process (surface cleaning process is the technology that those skilled in the art easily realize, and is usually cleaned by ultrasonic wave acetone, alcohol, deionized water successively) and be coated with one deck positive photoresist afterwards; (photoetching process is coated with one deck positive photoresist on the totally smooth silicon chip of a slice, is radiated on silicon chip with relief ultraviolet light by the mask plate that a piece is carved with figure to utilize photoetching process; After silicon chip being put into developer solution reaction, rotten being corroded can be there is in the part photoresist be irradiated to, the photoresist be not irradiated to then can still stick in above silicon chip), make the front of wafer level silicon chip substrate to obtain the identical litho pattern of shape upper with mask plate (figure on mask plate can be designed as square array or vertical bar array etc. as required).
Step 3: using plasma dry etching method is by the SiO in wafer level silicon chip substrate front
2the exposed portion of mask layer erodes, thus exposes the front of the wafer level silicon chip substrate that will be etched.
Step 4: adopt wet anisotropic caustic solution wafer level silicon chip substrate to be put into corrosive liquid and circle level silicon wafer substrate is etched, thus exposed portion on the front of wafer level silicon chip substrate is eroded and the partial corrosion that wafer level silicon chip substrate top contacts with litho pattern is become tip-shape structure; Wherein corrosive liquid is KOH:IPA:H by mass percent
2o=23%:14%:63% mixes.Wafer level silicon chip substrate is made up of monocrystalline silicon, and wherein monocrystalline silicon has three crystal faces: 100,110,111, and wherein horizontal plane is (110) face, (100) face perpendicular to (110) face, with the angle in (100) face be 54.74 ° for (111) face; Because atomic arrangement density difference result in silicon single crystal anisotropy on various crystal face, show as corrosion rate difference highlightedly; Corrosive liquid is far longer than (111) face to the corrosion rate in (100) face in wafer level silicon chip substrate, so corrosive liquid corrodes on (100) face, form V-type groove along (111) face, taper off to a point when two V-shaped grooves link together shape structure like this.
Step 5: wafer level silicon chip substrate is put into the stripper supporting with positive photoresist and reacts, thus the litho pattern removing wafer level silicon chip substrate front.
Step 6: wafer level silicon chip substrate being put into by percent by volume is HF:H
2the SiO in wafer level silicon chip substrate front is removed in the hydrofluoric acid solution that O=1:5 mixes
2mask layer, thus obtain the low-dimensional nano structure physics substrate template with tip-shape structure.
(2), low-dimensional nano structure physics substrate template is placed in establish on the target of the magnetic control sputtering device of noble metal target material (noble metal can select Au, Ag, Pt etc.), inert gas argon gas will be passed in magnetic control sputtering device, bombard noble metal target material after ionized inert gas thus be deposited on low-dimensional nanometer physics substrate template after the noble metal nano particles of disengaging noble metal target material is synthesized, on the cutting-edge structure depositing to tip-shape structure that the noble metal nano particles synthesized under electrostatic field singular point effect is compact in order, thus obtain one deck noble metal film.As shown in Figure 9, the noble metal nano particles of synthesis can attach negative electrical charge automatically, when the noble metal nano particles with electrostatic charge is to low-dimensional nanometer physics substrate template apparent motion with tip-shape structure, charged noble metal nano particles will form an electron cloud, the electrostatic field formed by this electron cloud will be polarized low-dimensional nano structure physics substrate template further, in field singularities effect, (field singularities effect refers in the large place of body surface curvature, as close in equipotential face, top that is sharp-pointed, fines, electric-field intensity increases severely; On the contrary, in the place that curvature is little, if the charge density such as recess, even surface is close to zero, electric-field intensity reduces sharply) effect under can form electrostatic field singular point at the tip place of cutting-edge structure; The noble metal nano particles of synthesis understands the tip place of autodeposition to cutting-edge structure under the effect of field singularities effect, and finally reach electrostatic equilibrium distribution, form one deck noble metal film, thus realize the orderly self assembly from synthesis of nano particle to low-dimensional nano structure.
(3), low-dimensional nano structure physics substrate template is carried out annealing process, the grain spacing of self-assembled nano structures noble metal film inside and the electrons transport property of the way of contact and nano structured unit inside are changed, realize the inner transformation from nanoparticle aggregate to densification of nanostructured, thus finally obtain low-dimensional nano-structure.
Described thermal oxidation method, photoetching process, plasma dry etch, wet anisotropic caustic solution are the technology of well known to a person skilled in the art.
Preparation method of the present invention makes full use of noble metal nano particles self charging characteristic and the electrostatic field singular point effect principle of synthesis, under the prerequisite well compatible with traditional MEMS processing technology, adopt physical method, obtain the noble metal low-dimension nano material structure of low cost, no pollution, wafer level large area, high reliability and high-sequential; Breach low-dimensional nano structure inefficiency, the jejune technical barrier of technology in large area self-assembly process, achieve the self assembly manufacture of low-dimensional nano-structure; Solve existing orderly low-dimensional nano structure can only small size manufacture, cost high, seriously polluted and with the problem of traditional MEMS processing technology poor compatibility, the large area manufacture of orderly low-dimensional nano structure can be widely used in.
Accompanying drawing explanation
Fig. 1 is the process chart of the first step of the present invention.
Fig. 2 is the structural representation of wafer level silicon chip substrate.
Fig. 3 is the structural representation of step one in the first step of the present invention.
Fig. 4 is the structural representation of step 2 in the first step of the present invention.
Fig. 5 is the structural representation of step 3 in the first step of the present invention.
Fig. 6 is the structural representation of step 4 in the first step of the present invention.
Fig. 7 is the structural representation of step 5 in the first step of the present invention.
Fig. 8 is the structural representation of step 6 in the first step of the present invention.
Fig. 9 is the schematic diagram of noble metal nano particles self-focusing under field singularities effect.
Figure 10 is the stereogram of one-dimensional nano line physics substrate template in embodiment 1.
Figure 11 is the structural representation of the small size low-dimensional nano structure unit that embodiment 1 obtains.
Figure 12 is the stereogram of zero-dimension nano point physics substrate template in embodiment 2.
Figure 13 is the structural representation of the small size low-dimensional nano structure unit that embodiment 2 obtains.
In figure: 1-wafer level silicon chip substrate; 2-SiO
2mask layer; 3-litho pattern; The tip-shape structure of 4-; 5-cross section is leg-of-mutton tip-shape structure; 6-Crystal structure; The tip-shape structure of 7-rectangular pyramid nano dot; 8-silver nano lattice arranges.
Detailed description of the invention
Embodiment 1:
Based on the preparation method of the low-dimensional nano-structure of electrostatic field singular point self-focusing, comprise the steps:
(1) preparation of one-dimensional nano line physics substrate template:
Step one: the wafer level silicon chip substrate 1 that cut-off footpath is 3inch, thickness is 600 μm, adopts thermal oxidation method all to grow at the front and back of wafer level silicon chip substrate 1 SiO that a layer thickness is 300nm
2mask layer 2;
Step 2: be coated with one deck positive photoresist after surface cleaning process is carried out in the front of wafer level silicon chip substrate 1; Select vertical bar array-like mask plate, utilize photoetching process, make the front of wafer level silicon chip substrate 1 to be formed vertical bar array-like litho pattern;
Step 3: using plasma dry etching method is by the SiO in wafer level silicon chip substrate front
2the exposed portion of mask layer 2 erodes;
Step 4: adopt wet anisotropic caustic solution that wafer level silicon chip substrate 1 is put into corrosive liquid and wafer level silicon chip substrate 1 is etched, thus exposed portion on the front of wafer level silicon chip substrate 1 is eroded and becomes cross section to be leg-of-mutton tip-shape structure 5 partial corrosion that wafer level silicon chip substrate 1 top contacts with vertical bar array-like litho pattern; Wherein corrosive liquid is KOH:IPA:H by mass percent
2o=23%:14%:63% mixes;
Step 5: wafer level silicon chip substrate 1 is put into the stripper supporting with positive photoresist and reacts, thus the vertical bar array-like litho pattern removing wafer level silicon chip substrate 1 front;
Step 6: wafer level silicon chip substrate 1 being put into by percent by volume is HF:H
2the SiO of wafer level silicon chip substrate 1 front and back is removed in the hydrofluoric acid solution that O=1:5 mixes
2mask layer 2, thus obtain being the one-dimensional nano line physics substrate template of leg-of-mutton tip-shape structure 5 with cross section; As shown in Figure 10;
(2), one-dimensional nano line physics substrate template is placed in establish on the target of the magnetic control sputtering device of gold target material, inert gas argon gas will be passed in magnetic control sputtering device, bombard gold target material after ionized inert gas thus be deposited on one-dimensional nano line physics substrate template after the gold nano grain of disengaging gold target material is synthesized, the gold nano grain synthesized under electrostatic field singular point effect is compact in order to be deposited on tip that cross section is leg-of-mutton tip-shape structure 5 thus to obtain one deck Crystal structure 6;
(3) one-dimensional nano line physics substrate template is carried out annealing process, thus obtain low-dimensional nano-structure.
During use, above-mentioned obtained low-dimensional nano-structure is carried out cutting whole into sections, obtain small size low-dimensional nano structure unit as shown in figure 11, to be applied in MEMS, thus realize real through engineering approaches application.
Embodiment 2:
Based on the preparation method of the low-dimensional nano-structure of electrostatic field singular point self-focusing, comprise the steps:
(1) preparation of zero-dimension nano point physics substrate template:
Step one: the wafer level silicon chip substrate 1 that cut-off footpath is 6inch, thickness is 300 μm, adopts thermal oxidation method all to grow at the front and back of wafer level silicon chip substrate 1 SiO that a layer thickness is 500nm
2mask layer 2;
Step 2: be coated with one deck positive photoresist after surface cleaning process is carried out in the front of wafer level silicon chip substrate 1; Select square array mask plate, utilize photoetching process, make the front of wafer level silicon chip substrate 1 to be formed square array-like litho pattern;
Step 3: using plasma dry etching method is by the SiO in wafer level silicon chip substrate 1 front
2the exposed portion of mask layer 2 erodes;
Step 4: adopt wet anisotropic caustic solution that wafer level silicon chip substrate 1 is put into corrosive liquid and wafer level silicon chip substrate 1 is etched, thus exposed portion on the front of wafer level silicon chip substrate 1 is eroded and the partial corrosion that wafer level silicon chip substrate 1 top contacts with square array-like litho pattern is become the tip-shape structure 7 of rectangular pyramid nano dot; Wherein corrosive liquid is KOH:IPA:H by mass percent
2o=23%:14%:63% mixes;
Step 5: wafer level silicon chip substrate 1 is put into the stripper supporting with positive photoresist and reacts, thus the square array-like litho pattern removing wafer level silicon chip substrate 1 front;
Step 6: wafer level silicon chip substrate 1 being put into by percent by volume is HF:H
2the SiO of wafer level silicon chip substrate 1 front and back is removed in the hydrofluoric acid solution that O=1:5 mixes
2mask layer 2, thus obtain the zero-dimension nano point physics substrate template with the tip-shape structure 7 of rectangular pyramid nano dot; As shown in figure 12;
(2) zero-dimension nano point physics substrate template is placed in establish on the target of the magnetic control sputtering device of silver-colored target, inert gas argon gas will be passed in magnetic control sputtering device, bombard silver-colored target after ionized inert gas thus be deposited on zero-dimension nano point physics substrate template after the silver nano-grain of disengaging silver target is synthesized, the tip depositing to the tip-shape structure 7 of rectangular pyramid nano dot that the silver nano-grain synthesized under electrostatic field singular point effect is compact in order obtains one deck silver nano lattice row 8;
(3) zero-dimension nano point physics substrate template is carried out annealing process, thus obtain low-dimensional nano-structure.
During use, above-mentioned obtained low-dimensional nano-structure is carried out cutting whole into sections, obtain small size low-dimensional nano structure unit as shown in fig. 13 that, to be applied in MEMS, thus realize real through engineering approaches application.
Claims (2)
1., based on the preparation method of the low-dimensional nano-structure of electrostatic field singular point self-focusing, it is characterized in that: comprise the steps:
(1), the preparation of low-dimensional nano structure physics substrate template:
Step one: the wafer level silicon chip substrate (1) that cut-off footpath is 3inch ~ 6inch, thickness is 300 ~ 600 μm, adopts thermal oxidation method all to grow at the front and back of wafer level silicon chip substrate (1) SiO that a layer thickness is 300nm ~ 500nm
2mask layer (2);
Step 2: be coated with one deck positive photoresist after surface cleaning process is carried out in the front of wafer level silicon chip substrate (1); Utilize photoetching process, make the front of wafer level silicon chip substrate (1) to obtain the litho pattern (3) identical with shape on mask plate;
Step 3: using plasma dry etching method is by the SiO in wafer level silicon chip substrate (1) front
2the exposed portion of mask layer (2) erodes;
Step 4: adopt wet anisotropic caustic solution that wafer level silicon chip substrate (1) is put into corrosive liquid and wafer level silicon chip substrate (1) is etched, thus exposed portion on the front of wafer level silicon chip substrate (1) is eroded and the partial corrosion that wafer level silicon chip substrate (1) top contacts with litho pattern (3) is become tip-shape structure (4); Wherein corrosive liquid is KOH:IPA:H by mass percent
2o=23%:14%:63% mixes;
Step 5: wafer level silicon chip substrate (1) is put into the stripper supporting with positive photoresist and reacts, thus the litho pattern (3) removing wafer level silicon chip substrate (1) front;
Step 6: putting into by percent by volume by wafer level silicon chip substrate (1) is HF:H
2the SiO of wafer level silicon chip substrate (1) front and back is removed in the hydrofluoric acid solution that O=1:5 mixes
2mask layer (2), thus obtain the low-dimensional nano structure physics substrate template with tip-shape structure (4);
(2), low-dimensional nano structure physics substrate template is placed in establish on the target of the magnetic control sputtering device of noble metal target material, inert gas argon gas will be passed in magnetic control sputtering device, bombard noble metal target material after ionized inert gas thus be deposited on low-dimensional nano structure physics substrate template after the noble metal nano particles of disengaging noble metal target material is synthesized, the tip depositing to tip-shape structure (4) that the noble metal nano particles synthesized under electrostatic field singular point effect is compact in order obtains one deck noble metal film;
(3), by low-dimensional nano structure physics substrate template carry out annealing process, thus finally obtain low-dimensional nano-structure.
2. the preparation method of the low-dimensional nano-structure based on the self-focusing of electrostatic field singular point according to claim 1, is characterized in that: described magnetic control sputtering device adopts Qprep400-BASE type nanocluster depositing system.
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| CN103030097B (en) * | 2012-12-12 | 2015-06-17 | 中北大学 | Method for preparing wafer level low-dimensional nanostructures based on electrostatic field self-focusing |
| CN103048308B (en) * | 2013-01-11 | 2014-11-05 | 中国科学院光电技术研究所 | Manufacturing method of surface enhanced Raman probe based on secondary enhancement |
| CN103934472B (en) * | 2014-04-10 | 2016-04-06 | 陕西师范大学 | The method of the silver-colored micro-nano granules of a kind of electric field-assisted annealing preparation |
| CN110002393A (en) * | 2019-04-04 | 2019-07-12 | 中国科学院微电子研究所 | The preparation method of method for selective etching and nanometer pinpoint structure |
| CN111188006B (en) * | 2020-01-08 | 2021-07-06 | 电子科技大学 | Preparation method of micro-nano metal particles in periodic arrangement |
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