CN102569407A - Silicon-based graphene field effect transistor and production method thereof - Google Patents
Silicon-based graphene field effect transistor and production method thereof Download PDFInfo
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- CN102569407A CN102569407A CN2012100330248A CN201210033024A CN102569407A CN 102569407 A CN102569407 A CN 102569407A CN 2012100330248 A CN2012100330248 A CN 2012100330248A CN 201210033024 A CN201210033024 A CN 201210033024A CN 102569407 A CN102569407 A CN 102569407A
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Abstract
The invention provides a silicon-based graphene field effect transistor and a production method of the transistor. The transistor comprises a gate electrode, a low-resistance silicon layer, a grid oxide layer and a graphene layer from bottom to top. A source region and a drain region of the transistor are positioned in the graphene layer, and a channel region is positioned between the source region and the drain region.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly silica-based graphene field effect transistor and preparation method thereof.
Background technology
Graphene (Graphene) is a kind of by individual layer or the several layers of thin slice that (being lower than 100 layers) carbon atom is formed; Two-dimentional graphite flake like this has been proved many superpower attributes; Electronics like it transports with the trajectory mode in the sub-micron distance; Do not have any scattering, have very attracting conductive capability, this provides condition for making ultra performance transistor.The Graphene transistor can at room temperature be worked, and finally substituted for silicon of prophesy graphene film is arranged, because the Graphene transistor is more efficient than silicone tube, consumes energy lower sooner.Graphene has brought a new opportunity to semicon industry, when the silicon processing procedure of following 65nm, 45nm even 32nm can not satisfy the semi-conductor industry demand, perhaps just should substitute it by Graphene.
Summary of the invention
The invention provides a kind of silica-based graphene field effect transistor and preparation method thereof.
Silica-based graphene field effect transistor according to the present invention comprises from bottom to top: gate electrode, low-resistance silicon layer, gate oxide level and graphene layer, and this transistorized source region and drain region are arranged in this graphene layer, and channel region is between source region and drain region.
Alternatively, said low-resistance silicon layer is made up of the silicon substrate with (111) or (100) or (110) crystal face.
Alternatively, the silicon dioxide layer that forms by the part of the said low-resistance silicon layer of oxidation of said gate dielectric layer, be deposited on silicon dioxide layer on the said low-resistance silicon layer, or the high-k dielectric layer that is deposited on the said low-resistance silicon layer constitute.
Alternatively, said graphene layer is made up of Graphene two dimensional crystal material.
Alternatively, the Graphene two dimensional crystal material that formed by the silicon carbide film thermal decomposition of said graphene layer constitutes.
Alternatively, the number of plies of said Graphene two dimensional crystal material is by the carbon silicon diatomic number of plies decision of said silicon carbide film.
Alternatively, the thickness of said silicon carbide film is 1～100 carbon silicon diatomic layer.
Method according to silica-based graphene field effect transistor of the present invention comprises the steps:
On the first surface of low-resistance silicon substrate, form gate dielectric layer;
On said gate dielectric layer, form silicon carbide film;
Said silicon carbide film is carried out thermal annealing to be decomposed to form Graphene two dimensional crystal material layer;
Graphical said Graphene two dimensional crystal material layer is to form source region and drain region; And
Said low-resistance silicon substrate with said first surface opposing second surface on form gate electrode.
Alternatively, the first surface of said low-resistance silicon substrate is (111) or (100) or (110) face.
Alternatively, the thickness of said silicon carbide layer is the thickness of 1-100 carbon silicon diatomic layer.
Description of drawings
Fig. 1 shows the schematic cross sectional view of making one of the step of silica-based graphene field effect transistor according to embodiments of the invention, wherein on the low-resistance silicon substrate, has formed silicon dioxide layer.
Fig. 2 shows two the schematic cross sectional view of making the step of silica-based graphene field effect transistor according to embodiments of the invention, wherein on silicon dioxide layer, has formed silicon carbide layer.
Fig. 3 shows three the schematic cross sectional view of making the step of silica-based graphene field effect transistor according to embodiments of the invention, and wherein the carborundum thermal decomposition is after annealing reconstruct forms Graphene.
Fig. 4 shows the schematic cross sectional view of silica-based graphene field effect transistor according to an embodiment of the invention.
Embodiment
In order to make technical scheme provided by the invention clear more and understand, below with reference to accompanying drawing and combine specific embodiment, the present invention is described in more detail.Accompanying drawing is schematically, might not draw in proportion, runs through the identical Reference numeral of accompanying drawing and representes same or analogous part.
At first as shown in Figure 1; On silicon substrate 100, form silicon dioxide layer 200; This silicon dioxide layer 200 is as transistorized gate-dielectric, and it can form through the part of the said silicon substrate 100 of oxidation or directly on said silicon substrate 100, form through chemical vapour deposition (CVD) deposit silicon dioxide.As transistorized gate-dielectric, said silicon dioxide layer 200 also can use other high-k dielectrics (for example aluminium nitride, hafnium oxide etc.) layer to replace.Said silicon substrate 100 is for having the low-resistance p or the low-resistance n type substrate of (111) or (100) or (110) face, and resistivity is 0.01-10 Ω cm, and perhaps doping content is 1E18-1E20/cm
3
Then, as shown in Figure 2, growing silicon carbide film 300 ' on said silicon dioxide layer 200.The growth conditions of this silicon carbide film for example can be selected: temperature is 1100～1300 ℃, pressure 10
-2To 10 handkerchiefs.Preferably, the thickness of this silicon carbide film 300 ' is 1～100 carbon silicon diatomic layer.
Next; As shown in Figure 3; Adopt the method for thermal decomposition in the high temperature and super vacuum environment, to remove the silicon atom in the silicon carbide film 300 ' then, the carbon atom that stays reconstruct under the condition of thermal annealing forms the Graphene two dimensional crystal layer 300 with layered graphite structure.Heat decomposition temperature for example is 1280-1350 ℃, and thermal decomposition pressure for example is 10
-3To 10
-6Handkerchief, annealing reconstruct temperature for example are 10 for 1300-1380 ℃, pressure for example
-5To 10
-7Handkerchief.
At last through for example electron beam lithography and the graphical said graphene layer 300 of plasma etching; Graphene layer 300 graphical backs are for example being etched source, drain region and preparing corresponding metal electrode 310 and 320 in the oxygen plasma atmosphere; Preparation grid metal electrode 400 and annealing on the back side of said silicon substrate 100 then can be prepared silica-based graphene field effect transistor of the present invention.The metal electrode in source, drain region can adopt electron beam evaporation method on the source-drain area of graphene layer 300, to evaporate metal such as the platinum or the gold etc. of thick about 100-500 nanometer; About 1 minute of short annealing under 600-1050 ℃ of temperature, vacuum or Ar atmosphere then is to form ohmic contact.Said grid metal electrode 400 can be by for example constituting thick 0.5-1 micron with magnetically controlled sputter method at the metal level that the back spatter of said low-resistance silicon substrate 100 forms.Said metal can be aluminium or silver, at 300-600 ℃ of temperature, Ar atmosphere or N
2Under the atmosphere short annealing 1-5 minute, with and said low-resistance silicon substrate 100 between form ohmic contact.Said metal also can be gold or nickel or platinum etc., under 600-1050 ℃ of temperature, vacuum or Ar atmosphere the about 1-5 of short annealing minute, with and said low-resistance silicon substrate 100 between form ohmic contact.
More than described transistor of the present invention and made transistorized method through exemplary embodiment, yet this is not intended to limit protection scope of the present invention.Any modification of the foregoing description that it may occur to persons skilled in the art that or modification all fall in the scope of the present invention that is defined by the following claims.
Claims (10)
1. silica-based graphene field effect transistor; It is characterized in that; Comprise from bottom to top: gate electrode, low-resistance silicon layer, gate oxide level and graphene layer, this transistorized source region and drain region are arranged in this graphene layer, and channel region is between source region and drain region.
2. transistor according to claim 1 is characterized in that: said low-resistance silicon layer is made up of the silicon substrate with (111) or (100) or (110) crystal face.
3. transistor according to claim 1 is characterized in that: the silicon dioxide layer that said gate dielectric layer is formed by the part of the said low-resistance silicon layer of oxidation, be deposited on silicon dioxide layer on the said low-resistance silicon layer, or the high-k dielectric layer that is deposited on the said low-resistance silicon layer constitute.
4. according to each described transistor among the claim 1-3, it is characterized in that: said graphene layer is made up of Graphene two dimensional crystal material.
5. transistor according to claim 4 is characterized in that: the Graphene two dimensional crystal material that said graphene layer is formed by the silicon carbide film thermal decomposition constitutes.
6. transistor according to claim 5 is characterized in that: the number of plies of said Graphene two dimensional crystal material is by the carbon silicon diatomic number of plies decision of said silicon carbide film.
7. transistor according to claim 6 is characterized in that: the thickness of said silicon carbide film is 1～100 carbon silicon diatomic layer.
8. the method for a silica-based graphene field effect transistor comprises the steps:
On the first surface of low-resistance silicon substrate, form gate dielectric layer;
On said gate dielectric layer, form silicon carbide film;
Said silicon carbide film is carried out thermal annealing to be decomposed to form Graphene two dimensional crystal material layer;
Graphical said Graphene two dimensional crystal material layer is to form source region and drain region; And
Said low-resistance silicon substrate with said first surface opposing second surface on form gate electrode.
9. method as claimed in claim 8, the first surface of wherein said low-resistance silicon substrate are (111) or (100) or (110) face.
10. like claim 8 or 9 described methods, the thickness of wherein said silicon carbide layer is the thickness of 1-100 carbon silicon diatomic layer.
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| CN104319290A (en) * | 2014-10-29 | 2015-01-28 | 上海集成电路研发中心有限公司 | Three-grid graphene fin type field effect transistor and manufacturing method thereof |
| CN105826368A (en) * | 2016-05-11 | 2016-08-03 | 广东工业大学 | Two-dimensional material field effect transistor and preparation method thereof |
| US10900927B2 (en) | 2018-03-21 | 2021-01-26 | University Of South Carolina | Graphene field effect transistors for detection of ions |
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Application publication date: 20120711 |