CN101566768B - Pixel structure for thin film transistor liquid crystal display and manufacturing method thereof - Google Patents
Pixel structure for thin film transistor liquid crystal display and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a pixel structure for a thin film transistor liquid crystal display, wherein a pixel electrode and a transparent conducting layer are formed on a substrate; a drain electrode isformed on the pixel electrode, a data scanning line and a source electrode are formed on the transparent conducting layer, the source electrode is connected with the data scanning line, and the drain electrode is connected with the pixel electrode; an ohmic contact layer and a semiconductor layer are formed on the source electrode and the drain electrode respectively, and the contact part of the ohmic contact layer and the source electrode is not connected with the contact part of the ohmic contact layer and the drain electrode; a passivation layer is formed on the parts of the source electrode and the drain electrode which are not covered by the ohmic contact layer, the part of the ohmic contact layer which is not covered by the semiconductor layer, and the semiconductor layer respectively; and a grid scanning line, a grid electrode and a grid electrode insulating layer are sequentially formed on the passivation layer. Simultaneously, the invention provides a method for manufacturingthe pixel structure for the thin film transistor liquid crystal display, and the pixel structure and the manufacturing method can save the manufacturing technological process and enlarge the storage capacitance.
Description
Technical Field
The present invention relates to a Thin Film Transistor (TFT) Liquid Crystal Display (LCD) array substrate, and more particularly, to a TFT liquid crystal display pixel structure and a method of fabricating the same.
Background
At present, the world has entered the information revolution era, and display technologies and display devices have occupied a very important position in the development process of the information technologies. Among them, flat panel displays have become the development of display technology due to their advantages of light weight, thin thickness, small volume, no radiation, no flicker, etc. In the flat panel display technology, the TFT LCD has a dominant position in the flat panel display market due to its characteristics of low power consumption, relatively low manufacturing cost, and no radiation.
The TFT LCD device is formed by assembling an array glass substrate and a color filter glass substrate, and fig. 1 to 1B are schematic sectional views of a single pixel top view and a-a and B-B portions thereof of an currently mainstream amorphous silicon TFT structure. As shown in fig. 1 to 1b, the amorphous silicon TFT structure employs a back channel etched bottom gate structure, and the array structure includes: a group of gate scan lines 1 and a group of data scan lines 5 perpendicular thereto, and the adjacent gate scan lines 1 and data scan lines 5 define a pixel region. Each pixel comprises a TFT switching device, a pixel electrode 10 and a part of a common electrode lead 11, wherein the TFT switching device consists of a gate electrode 2, an ohmic contact layer 14, a semiconductor layer 3, a gate electrode insulating layer 4, a source electrode 6 and a drain electrode 7; a passivation layer 8 covers the gate electrode 2, the ohmic contact layer 14, the semiconductor layer 3, the gate electrode insulating layer 4, and the source and drain electrodes 6 and 7, and a passivation layer via hole 9 is formed above the drain electrode 7; the pixel electrode 10 is connected with the drain electrode 7 of the TFT through the passivation layer via hole 9; a part of the pixel electrode 10 forms a storage capacitor (not shown) together with the gate scan line 1. In order to further reduce light leakage between pixels behind the cell, light blocking bars 12 are formed at both sides of the pixels parallel to the data scan lines 5.
The pixel structures shown in FIGS. 1-1 b are typically fabricated using a 5-Mask process. The 5-Mask process is a typical process technology for manufacturing a TFT, and the main process steps are shown in fig. 2, and include:
step 201-202: forming a gate electrode and a lead thereof, and forming a gate electrode insulating layer, an ohmic contact layer and a semiconductor layer;
step 203-205: forming a source electrode, a drain electrode and a data scanning line; and forming a passivation layer and a pixel electrode.
Each step shown in fig. 2 includes a thin film deposition process, and a patterning process such as exposure and etching. In addition to the 5-Mask technology shown in fig. 2, in the prior art, other Mask process technologies can also be generated by changing the Mask design and the process flow, and are not described herein again.
In the pixel structures shown in fig. 1 to 1b manufactured by the above-mentioned 5-Mask process, since the gate electrode insulating layer 4 and the passivation layer 8 exist between the pixel electrode 10 and the gate scan line 1, the storage capacitance (not shown) is small, and further the step voltage is large, which may affect the display quality of the picture.
Disclosure of Invention
In view of the above, the present invention provides a pixel structure of a thin film transistor liquid crystal display and a method for fabricating the same, which can simplify the process and improve the display quality of the image.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the invention provides a pixel structure of a thin film transistor liquid crystal display, which comprises a substrate; a pixel electrode and a transparent conductive layer are formed on the substrate, the pixel electrode and the transparent conductive layer are parts made of the same material, and the pixel electrode and the transparent conductive layer are not connected with each other;
a drain electrode is formed on the pixel electrode, a data scanning line and a source electrode are formed on the transparent conductive layer, the source electrode is connected with the data scanning line, and the drain electrode is connected with the pixel electrode;
an ohmic contact layer and a semiconductor layer are sequentially formed on the source electrode and the drain electrode, and the ohmic contact layer is not connected with the contact parts of the source electrode and the drain electrode respectively;
a passivation layer is formed on the source electrode, the part of the drain electrode, which is not covered by the ohmic contact layer, the part of the ohmic contact layer, which is not covered by the semiconductor layer, and the semiconductor layer;
a grid scanning line and a grid electrode are formed on the passivation layer;
a gate electrode insulating layer is formed on the gate scan line and the gate electrode.
The ohmic contact layer between the source electrode and the drain electrode comprises a semiconductor doping area, and the semiconductor doping area enables the ohmic contact layer to be not connected with the parts of the source electrode and the drain electrode which are respectively connected with each other.
The substrate structure further includes:
light blocking strips and common electrode leads are further formed on the passivation layer and below the gate electrode insulating layer, the light blocking strips are parallel to the data scanning lines, and the common electrode leads are parallel to the gate scanning lines.
The grid scanning lines, the data scanning lines, the source electrodes, the drain electrodes, the common electrode leads or the light blocking strips are single layers formed by one of aluminum, chromium, tungsten, tantalum, titanium, molybdenum and aluminum nickel, or single layers or composite layers formed by any combination of the metal materials.
The invention also provides a manufacturing method of the pixel structure of the thin film transistor liquid crystal display, which comprises the following steps:
A. sequentially depositing a pixel electrode layer and a metal film on a substrate, forming a pixel electrode, a source electrode, a drain electrode and a data scanning line on the substrate through a composition process, connecting the source electrode with the data scanning line, connecting the drain electrode with the pixel electrode, wherein the pixel electrode layer below the data scanning line and the source electrode is a transparent conducting layer, and the pixel electrode and the transparent conducting layer are not connected with each other;
B. depositing an ohmic contact layer film on the substrate which is subjected to the step A, enabling the ohmic contact layer film to be not connected with the parts which are respectively connected with the source electrode and the drain electrode through a certain process, then depositing a semiconductor layer film, and forming an ohmic contact layer and a semiconductor layer on the source electrode and the drain electrode through a composition process;
C. depositing a passivation layer film on the substrate after the step B to form a passivation layer;
D. depositing a metal film on the substrate after the step C is finished, and forming a grid scanning line and a grid electrode through a composition process;
E. and forming a gate electrode insulating layer on the substrate after the step D is completed.
The specific steps of making the parts of the ohmic contact layer film, which are respectively connected with the source electrode and the drain electrode, not connected with each other through a certain process are as follows:
firstly, coating a layer of photoresist on a deposited ohmic contact layer film, exposing the ohmic contact layer film corresponding to a semiconductor doping region through an exposure and development process, forming the semiconductor doping region on the exposed ohmic contact layer film by using a semiconductor doping process, and then stripping the photoresist on the ohmic contact layer film.
The specific steps of making the parts of the ohmic contact layer film, which are respectively connected with the source electrode and the drain electrode, not connected with each other through a certain process are as follows:
coating a layer of photoresist on the deposited ohmic contact layer film, exposing the ohmic contact layer film corresponding to the semiconductor doping region through an exposure and development process, etching the exposed ohmic contact layer film by using a patterning process, and stripping the photoresist on the ohmic contact layer film.
And in the step B, after the ohmic contact layer and the semiconductor layer are used for forming the peninsula doped region, the ohmic contact layer and the semiconductor layer are simultaneously formed in a composition process by using the same mask plate.
The step A specifically comprises the following steps:
sequentially depositing a pixel electrode layer and a metal film on a substrate, coating a layer of photoresist on the metal film, and fully exposing a data scanning line, a source electrode, a drain electrode and a pixel area by using a mask plate;
and carrying out ashing treatment on the pixel area, removing the photoresist on the pixel area, and etching the metal film layer of the pixel area to form a pixel electrode.
And D, forming a common electrode lead and a light blocking strip at the same time of forming a grid scanning line and a grid electrode through a composition process.
The forming of the gate electrode insulating layer specifically includes:
depositing a gate electrode insulating layer, and forming via holes at the periphery of the substrate through a composition process to expose signal leads at the periphery of the substrate; or,
a gate electrode insulating layer is formed using a mask growth process.
The invention provides a pixel structure of a thin film transistor liquid crystal display and a manufacturing method thereof.A data scanning line, a source electrode, a drain electrode and a pixel electrode are formed in a one-time exposure process, but the data scanning line, the source electrode and the drain electrode are formed in the one-time exposure process and the pixel electrode is formed in the other-time exposure process as in the prior art; the ohmic contact layer and the semiconductor layer are formed in one etching process instead of being formed in two etching processes respectively, so that the process is greatly simplified. In addition, because the data scanning lines, the source electrode, the drain electrode and the pixel electrode are formed in the one-time exposure process, and the gate insulating layer and the passivation layer through hole are eliminated, only the passivation layer exists between the pixel electrode and the gate scanning line, the distance between the pixel electrode and the gate scanning line is reduced, the storage capacitance is increased, the jump voltage is reduced, and the picture display quality can be effectively improved and enhanced.
Drawings
FIG. 1 is a top view of a prior art single pixel structure on a TFT LCD array substrate;
FIG. 1a is a schematic cross-sectional view of portion A-A of FIG. 1;
FIG. 1B is a schematic cross-sectional view of portion B-B of FIG. 1;
FIG. 2 is a schematic view of a prior art 5-Mask process flow;
FIG. 3 is a top view of a single pixel structure on a TFT LCD array substrate according to the present invention;
FIG. 3a is a schematic cross-sectional view of portion C-C of FIG. 3;
FIG. 3b is another schematic cross-sectional view of portion C-C of FIG. 3;
FIG. 3c is a schematic cross-sectional view of portion D-D of FIG. 3;
FIG. 4 is a schematic flow chart of a manufacturing method of a TFT LCD pixel structure according to the present invention;
FIG. 5a is a top view of the pixel structure after the pixel electrode layer is patterned according to the method of FIG. 4;
FIG. 5b is a schematic cross-sectional view of portion E-E of the present invention after full exposure;
FIG. 5c is a schematic cross-sectional view of portion E-E of the present invention after an ashing process;
FIG. 5d is a schematic cross-sectional view of portion E-E of the present invention after removal of the metal film layer;
FIG. 5e is a schematic cross-sectional view of a portion of a pixel structure C-C after a patterning process is performed on a pixel electrode layer according to the method of FIG. 4;
FIG. 6a is a top view of the pixel structure after forming an ohmic contact layer and a semiconductor layer by a patterning process according to the manufacturing method shown in FIG. 4;
FIG. 6b is a schematic cross-sectional view of a portion of a pixel structure C-C after forming an ohmic contact layer and a semiconductor layer by a patterning process according to the method of FIG. 4;
FIG. 6C is a schematic cross-sectional view of a portion C-C after a semiconductor doping process is performed to form a semiconductor doped region in the manufacturing method shown in FIG. 4 according to the present invention;
FIG. 6d is a schematic cross-sectional view of a portion C-C after etching away the semiconductor doped region in the method of FIG. 4 according to the present invention;
FIG. 7 is a schematic cross-sectional view of a portion C-C after deposition of a passivation layer according to the method of FIG. 4;
fig. 8 is a partial cross-sectional view of the pixel structure C-C after the gate metal film is subjected to a patterning process according to the manufacturing method shown in fig. 4.
Reference numerals: 1. a gate scan line; 2. a gate electrode; 3. a semiconductor layer; 4. a gate insulating layer; 5. a data scanning line; 6. a source electrode; 7. a drain electrode; 8. a passivation layer; 9. a passivation layer via hole; 10. a pixel electrode; 11. a common electrode lead; 12. a light blocking strip; 14. an ohmic contact layer; 15. a semiconductor doped region; 16. photoresist; 17. a transparent conductive layer; 18. a metal film layer.
Detailed Description
The basic idea of the invention is: the data scanning line, the source electrode, the drain electrode and the pixel electrode are formed in a primary exposure process, the semiconductor layer and the ohmic contact layer are formed in a primary etching process, and the storage capacitance is increased while the process is simplified.
Furthermore, when the source electrode and the drain electrode are respectively connected with the ohmic contact layer, a semiconductor doping process can be applied to the ohmic contact layer between the source electrode and the drain electrode, so that the ohmic contact layers are not connected with each other, and the normal work of the pixel structure is ensured.
The following describes a pixel structure of a tft-lcd and a method for fabricating the same in detail by using specific embodiments and with reference to the accompanying drawings.
FIG. 3 is a top view of a single pixel structure on a TFT LCD array substrate according to the present invention; fig. 3a and 3b are a schematic cross-sectional view of part C-C and a schematic cross-sectional view of part D-D of fig. 3, respectively. As shown in fig. 3 to 3b, the array substrate of the TFT LCD has a set of gate scan lines 1 and common electrode leads 11 parallel thereto, and a set of data scan lines 5 and light blocking bars 12 perpendicular thereto; each adjacent grid scanning line 1 and data scanning line 5 intersect to define a pixel region; a pixel region includes a TFT switching device composed of a gate electrode 2, a semiconductor layer 3, a gate insulating layer 4, an ohmic contact layer 14, and source and drain electrodes 6 and 7, a pixel electrode 10, and a common electrode lead 11.
As shown in fig. 3 to 3b, the pixel structure provided by the present invention specifically includes:
the pixel electrode 10 and the transparent conductive layer 17 are arranged on the glass substrate, the drain electrode 7 is arranged on the pixel electrode 10, the data scanning line 5 and the source electrode 6 are arranged on the transparent conductive layer 17, the source electrode 6 is connected with the data scanning line 5, the drain electrode 7 is connected with the pixel electrode 10, and the pixel electrode 10 is not connected with the transparent conductive layer 17. In addition, depending on the manufacturing method, for example, when the manufacturing method shown in fig. 4 of the present invention is used, the transparent conductive layer 17 included under the data scanning line 5 and the source electrode 6 may be a pixel electrode layer where the pixel electrode 10 is located, but the transparent conductive layer 17 under the data scanning line 5 and the source electrode 6 is not connected to the drain electrode 7 and the pixel electrode 10, and only the portion of the pixel electrode layer connected to the drain electrode 7 is the pixel electrode 10, that is, the transparent conductive layer 17 is not connected to the pixel electrode 10. The pixel electrode 10, the source electrode 6, the drain electrode 7 and the data scanning line 5 are different material parts which are manufactured in the same film coating, mask photoetching, etching and other patterning processes. The material of the pixel electrode 10 and the transparent conductive layer 17 is typically indium tin oxide, indium zinc oxide, or aluminum zinc oxide. The data scanning line 5, the source electrode 6 and the drain electrode 7 are single layers formed by one of aluminum, chromium, tungsten, tantalum, titanium, molybdenum and aluminum nickel, or single layers or composite layers formed by any combination of the above metal materials.
The ohmic contact layer 14 and the semiconductor layer 3 are sequentially formed on the source electrode 6 and the drain electrode 7, and the portions of the ohmic contact layer 14 connected to the source electrode 6 and the drain electrode 7 are not connected to each other, wherein the ohmic contact layer 14 may be disconnected from each other by: forming a semiconductor doping region 15 as shown in fig. 3a through a semiconductor doping process, wherein the semiconductor doping region 15 belongs to the ohmic contact layer 14, and the ohmic contact layers 14 are not connected with each other; alternatively, the semiconductor doped region 15 shown in fig. 3a is directly etched away by a patterning process to form a cross-sectional view of the pixel structure shown in fig. 3b, so that the ohmic contact layers are not connected to each other. The ohmic contact layer 14 and the semiconductor layer 3 are portions of different materials which are manufactured by using the same mask in the photolithography and etching processes. The specific materials used are known in the art, and are not described herein.
The source electrode 6, the portion of the drain electrode 7 not covered by the ohmic contact layer 14, the portion of the ohmic contact layer 14 not covered by the semiconductor layer 3, and the semiconductor layer 3 are all covered with the passivation layer 8. The material of the passivation layer 8 is generally: silicon nitride, silicon dioxide or aluminum oxide.
The gate scan line 1, the gate electrode 2, the light blocking stripe 12, and the common electrode wiring 11 are included over the passivation layer 8, and the light blocking stripe is parallel to the data scan line 5. The gate electrode insulating layer 4 covers an uncovered portion of the passivation layer 8, the gate scan lines 1, the gate electrodes 2, the light blocking bars 12, and the common electrode lead 11. The gate scan lines 1, the common electrode leads 11, and the light blocking bars 12 are made of the same material in the same patterning process such as plating, mask lithography, and etching, and may be a single layer made of one of aluminum, chromium, tungsten, tantalum, titanium, molybdenum, and aluminum nickel, or a single layer or a composite layer made of any combination of the above metal materials.
In the prior art, as shown in fig. 1 to 1b, a semiconductor active layer 14 is arranged below a source electrode 6 and a drain electrode 7, and a pixel electrode 10 is connected with the drain electrode 7 through a passivation layer via hole 9; in the pixel structure of the invention, as shown in fig. 3 to 3b, the pixel electrode 10, the source electrode 6 and the drain electrode 7 are completed in the same film coating, mask lithography and etching processes, the passivation layer via hole 9 is eliminated, and a top gate structure is adopted, so that one-step exposure process is saved.
The TFT LCD pixel structure shown in fig. 3 to 3b is only a typical structure of the present invention, and in practical applications, pixel structures with other shapes and patterns may be adopted, as long as the source electrode is connected to the data scanning line, the drain electrode is connected to the pixel electrode, and the ohmic contact layer and the semiconductor layer are located on the data scanning line; if the ohmic contact layer is connected to the source electrode and the drain electrode, the portion of the ohmic contact layer connected to the source electrode and the portion of the ohmic contact layer connected to the drain electrode are not connected to each other.
Fig. 4 is a method for manufacturing a pixel structure of a tft-lcd according to the present invention, and referring to fig. 3 to 3b, the method includes:
step 401: a pixel electrode layer and a metal film are sequentially deposited on the substrate, and a pixel electrode 10, a source electrode 6, a drain electrode 7 and a data scanning line 5 are formed on the substrate through a patterning process such as an exposure process and an etching process.
Depositing a pixel electrode layer on a glass substrate by a metal deposition method, such as magnetron sputtering, and forming a mask with a transparent electrode
To
To (c) to (d); then, a layer of the film is deposited on the pixel electrode layer by a magnetron sputtering method to form a layer
To
A metal thin film; then, a layer of photoresist 16 is coated on the metal thin film, a data scanning line 5, a source electrode 6, a drain electrode 7 and a pixel area are fully exposed by a mask plate, the pixel area is a part corresponding to the pixel electrode 10 in fig. 5b, a metal thin film layer 18 with the same material as the data scanning line 5 covers the pixel electrode 10, the data scanning line 5, the source electrode 6, the drain electrode 7 and the pixel area are all of a double-layer metal structure, a pixel electrode layer located below the data scanning line 5 and the source electrode 6 is a transparent conductive layer 17, the pixel area is connected with the drain electrode 7, and the data scanning line 5 and the metal thin film layer 18 after the full exposure are covered with complete photoresist, as shown in fig. 5 b. Thereafter, ashing treatment is performed to remove the photoresist 16 covering the metal thin film layer 18, and the cross-sectional view of the portion E-E is shown in FIG. 5 c. Finally, the first metal layer on the double-layer metal of the pixel region, i.e. the metal thin film layer 18 on the pixel electrode 10, is removed by physical or chemical etching method to form the pattern of the pixel electrode 10, and the schematic cross-sectional view of the part E-E is shown in fig. 5 d.
The schematic diagram of the top view of the pixel structure and the cross-section of the part C-C after completing step 401 are shown in fig. 5a and 5e, and it can be known from fig. 5d that: the source electrode 6 is connected with the data line 5, the lower parts of the source electrode 6 and the drain electrode 7 comprise pixel electrode layers, the pixel electrode layers included under the data scanning line 5 and the source electrode 6 are the transparent conductive layers 17 in the invention, the transparent conductive layers 17 are not connected with the drain electrode 7 and are not included in the pixel electrode 10, and only the pixel electrode layer part connected with the drain electrode 7 is called the pixel electrode 10.
A commonly used pixel electrode 10 material is Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO); the metal material used for the metal thin film may be molybdenum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, copper, or other metal, or a combination of these metal material thin films may be used.
Specifically, how to use the magnetron sputtering method for deposition, how to perform exposure, and how to use the etching method belong to the known technologies, and are not described herein again.
Step 402: depositing an ohmic contact layer film on the substrate after the step 401, forming a semiconductor doping region 15 through a semiconductor doping process, then depositing a semiconductor layer film again, and forming an ohmic contact layer 14 and a semiconductor layer 3 on the source electrode 6 and the drain electrode 7 through patterning processes such as an exposure process and an etching process.
Depositing on the array substrate by a certain deposition method, such as chemical vapor deposition
ToThe N + a-Si thin film is coated with a layer of photoresist 16, and the semiconductor doping region 15 in the ohmic contact layer thin film is exposed through an exposure and development process. Performing a semiconductor doping process on the semiconductor doping region 15 to dope the semiconductor doping region 15 with P-type silicon, wherein the cross-sectional view of the C-C portion is shown in FIG. 6C, and then stripping off the light on the ohmic contact layer filmAnd (6) etching glue 16. Depositing on the array substrate using a metal deposition process, such as chemical vapor deposition
To
The amorphous silicon thin film is subjected to dry etching after being exposed by using a mask of the semiconductor layer 3, and the ohmic contact layer 14 and the semiconductor layer 3 are formed at the same time, wherein the ohmic contact layer 14 and the semiconductor layer 3 are different material parts which are manufactured by using the same mask in the composition processes of photoetching, etching and the like.
The ohmic contact layer 14 partially covered on the source electrode 6 and the drain electrode 7 is N-type amorphous silicon, and the semiconductor doping region 15 of the ohmic contact layer 14 between the source electrode 6 and the drain electrode 7 is P-type amorphous silicon. The top view of the pixel structure after this step is completed is shown in fig. 6a, and the schematic cross-sectional view of part C-C is shown in fig. 6 b.
Specifically, how to perform the deposition by using a chemical vapor deposition method, and how to perform the etching process and the doping process belong to the known technologies, and are not described herein again.
Step 403: sequential deposition on an array substrate using a deposition process, such as chemical vapor deposition
To
Of (3) a passivation layer.
A schematic cross-sectional view of a portion C-C of the pixel structure after completion of this step is shown in fig. 7, where a passivation layer 8 is deposited on the portions of the source electrode 6 and the drain electrode 7 not covered by the ohmic contact layer 14, the portion of the pixel electrode 10 not covered by the drain electrode 7, the portion of the ohmic contact layer 14 not covered by the semiconductor layer 3, and the semiconductor layer 3.
The material of the passivation layer is generally silicon nitride, silicon dioxide or aluminum oxide.
Step 404: a metal film is deposited on the substrate after step 403, and gate scan lines 1, gate electrodes 2, common electrode leads 11, and light blocking bars 12 are formed through patterning processes such as an exposure process and an etching process.
Using a metal deposition process, such as a magnetron sputtering process, a layer of a thickness of
To
The gate metal film is patterned by exposure and etching processes using a gate electrode mask to form patterns of gate scanning lines 1, gate electrodes 2, common electrode leads 11 and light blocking bars 12 in a certain area of the glass substrate.
A schematic cross-sectional view of a portion C-C of the pixel structure after this step is completed is shown in fig. 8, and the gate electrode 2 is formed on the passivation layer 8.
The gate metal material used for the gate metal film may be molybdenum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, copper, or other metals, or a combination structure of the above gate metal material films may also be used.
Step 405: a gate electrode insulating layer 4 is deposited on the substrate completing step 404.
Depositing a layer of a thickness on the glass substrate using a deposition process, such as chemical vapor deposition
To
A gate electrode insulating layer 4. In practical application, a gate electrode insulating layer is depositedAnd 4, forming a via hole pattern on the periphery of the array substrate by using a composition process such as exposure, etching and the like, and exposing the signal lead on the periphery of the array substrate to realize the input of an external signal.
The material of the gate electrode insulating layer is typically silicon nitride, silicon dioxide or aluminum oxide.
Alternatively, in this step, the gate electrode insulating layer 4 may be formed directly on the substrate after the step 404 by using a mask growth process. At this time, the used mask growth process can ensure that the gate electrode insulating layer 4 is not covered above the lead (PAD) area of the lead and the ITO electric shock area, thereby saving the process of exposing the peripheral signal lead by using the composition process such as exposure. How to form the gate electrode insulating layer 4 by using a mask growth process belongs to the well-known technology, and is not described in detail herein.
In step 402 of the pixel structure manufacturing method shown in fig. 4, the semiconductor doping region 15 may be directly etched away by using a patterning process such as dry etching, instead of using the semiconductor doping process, so as to achieve the purpose of disconnecting the ohmic contact layers. The cross-sectional view of the part C-C after etching away the semiconductor doped region 15 is shown in FIG. 6 d. At this time, the detailed operations of other steps are the same as the manufacturing method shown in fig. 4, and are not described in detail here.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (11)
1. A pixel structure of a thin film transistor liquid crystal display comprises a substrate; the liquid crystal display panel is characterized in that a pixel electrode and a transparent conducting layer are formed on the substrate, the pixel electrode and the transparent conducting layer are made of the same material, and the pixel electrode and the transparent conducting layer are not connected with each other;
a drain electrode is formed on the pixel electrode, a data scanning line and a source electrode are formed on the transparent conductive layer, the source electrode is connected with the data scanning line, and the drain electrode is connected with the pixel electrode;
an ohmic contact layer and a semiconductor layer are sequentially formed on the source electrode and the drain electrode, and the ohmic contact layer is not connected with the contact parts of the source electrode and the drain electrode respectively;
a passivation layer is formed on the source electrode, the part of the drain electrode, which is not covered by the ohmic contact layer, the part of the ohmic contact layer, which is not covered by the semiconductor layer, and the semiconductor layer;
a grid scanning line and a grid electrode are formed on the passivation layer;
a gate electrode insulating layer is formed on the gate scan line and the gate electrode.
2. The pixel structure according to claim 1, wherein the ohmic contact layer between the source electrode and the drain electrode comprises a semiconductor doping region which makes a portion of the ohmic contact layer connected to the source electrode and the drain electrode, respectively, unconnected.
3. The pixel structure of claim 2, wherein the substrate structure further comprises:
light blocking strips and common electrode leads are further formed on the passivation layer and below the gate electrode insulating layer, the light blocking strips are parallel to the data scanning lines, and the common electrode leads are parallel to the gate scanning lines.
4. The pixel structure according to claim 3, wherein the gate scan line, the data scan line, the source electrode, the drain electrode, the common electrode lead, or the light blocking strip is a single layer of one of aluminum, chromium, tungsten, tantalum, titanium, molybdenum, and aluminum nickel, or a single layer or a composite layer of any combination of the above metal materials.
5. A method for manufacturing a pixel structure of a thin film transistor liquid crystal display is characterized by comprising the following steps:
A. sequentially depositing a pixel electrode layer and a metal film on a substrate, forming a pixel electrode, a source electrode, a drain electrode and a data scanning line on the substrate through a composition process, connecting the source electrode with the data scanning line, connecting the drain electrode with the pixel electrode, wherein the pixel electrode layer below the data scanning line and the source electrode is a transparent conducting layer, and the pixel electrode and the transparent conducting layer are not connected with each other;
B. depositing an ohmic contact layer film on the substrate which is subjected to the step A, enabling the ohmic contact layer film to be not connected with the parts which are respectively connected with the source electrode and the drain electrode through a certain process, then depositing a semiconductor layer film, and forming an ohmic contact layer and a semiconductor layer on the source electrode and the drain electrode through a composition process;
C. depositing a passivation layer film on the substrate after the step B to form a passivation layer;
D. depositing a metal film on the substrate after the step C is finished, and forming a grid scanning line and a grid electrode through a composition process;
E. and forming a gate electrode insulating layer on the substrate after the step D is completed.
6. The manufacturing method according to claim 5, wherein the step of making the ohmic contact layer film and the source electrode and the drain electrode respectively connected to each other by a certain process is specifically:
firstly, coating a layer of photoresist on a deposited ohmic contact layer film, exposing the ohmic contact layer film corresponding to a semiconductor doping region through an exposure and development process, forming the semiconductor doping region on the exposed ohmic contact layer film by using a semiconductor doping process, and then stripping the photoresist on the ohmic contact layer film.
7. The manufacturing method according to claim 5, wherein the step of making the ohmic contact layer film and the source electrode and the drain electrode respectively connected to each other by a certain process is specifically:
coating a layer of photoresist on the deposited ohmic contact layer film, exposing the ohmic contact layer film corresponding to the semiconductor doping region through an exposure and development process, etching the exposed ohmic contact layer film by using a patterning process, and stripping the photoresist on the ohmic contact layer film.
8. The manufacturing method according to any one of claims 5 to 7, wherein the ohmic contact layer and the semiconductor layer are simultaneously formed in a patterning process using the same mask after the formation of the peninsula doped region in step B.
9. The manufacturing method according to any one of claims 5 to 7, wherein step A is in particular:
sequentially depositing a pixel electrode layer and a metal film on a substrate, coating a layer of photoresist on the metal film, and fully exposing a data scanning line, a source electrode, a drain electrode and a pixel area by using a mask plate;
and carrying out ashing treatment on the pixel area, removing the photoresist on the pixel area, and etching the metal film layer of the pixel area to form a pixel electrode.
10. The manufacturing method according to any one of claims 5 to 7, wherein a common electrode wiring and a light blocking bar are formed at the same time as the gate scan line and the gate electrode are formed by a patterning process in step D.
11. The manufacturing method according to any one of claims 5 to 7, wherein the forming of the gate electrode insulating layer is specifically:
depositing a gate electrode insulating layer, and forming via holes at the periphery of the substrate through a composition process to expose signal leads at the periphery of the substrate; or,
a gate electrode insulating layer is formed using a mask growth process.
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| CN102646713A (en) * | 2011-05-13 | 2012-08-22 | 京东方科技集团股份有限公司 | Pixel structure of thin film transistor liquid crystal display and manufacturing method thereof |
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| CN102646713A (en) * | 2011-05-13 | 2012-08-22 | 京东方科技集团股份有限公司 | Pixel structure of thin film transistor liquid crystal display and manufacturing method thereof |
| CN102646713B (en) * | 2011-05-13 | 2014-11-12 | 京东方科技集团股份有限公司 | Pixel structure of thin film transistor liquid crystal display and manufacturing method thereof |
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