Detailed Description
Fig. 1 is a battery protection circuit employing two-stage discharge overcurrent protection.
As shown in fig. 1, the circuit includes an overcharge detection circuit, an overdischarge detection circuit, a charge overcurrent detection circuit, a discharge overcurrent detection circuit, a short-circuit protection detection circuit, a control circuit, and switches MD, MC. The discharge overcurrent detection circuit and the short-circuit protection detection circuit carry out voltage detection aiming at secondary discharge overcurrent protection, namely, the voltage difference between the voltage of the VM end and the voltage of the G end is detected to be larger than a certain voltage threshold value VEDITo determine whether the discharge has occurredAnd (4) streaming. The voltage difference between the VM terminal and the G terminal is the conduction voltage drop of the switches MD and MC. If the on-resistances of MD and MC are RON_MDAnd RON_MCThen the detected discharge current threshold is:
when the discharge current increases beyond the discharge overcurrent protection threshold VEDIAnd this state continues for more than a certain delay time TEDIAnd when the battery protection circuit is in a discharging overcurrent protection state, the discharging circuit is switched off, discharging is forbidden, and the battery protection circuit enters the discharging overcurrent protection state.
When the discharge current is larger, the short-circuit protection threshold V is exceededSCAnd this state continues for more than a certain delay time TSCWhen the battery protection circuit is in a short-circuit protection state, the battery protection circuit can turn off the discharge path, forbid discharging and enter the short-circuit protection state. The short circuit protection state and the discharge overcurrent protection state are the same state for the control circuit, and the short circuit protection state and the discharge overcurrent protection state are both represented by discharge inhibition. When the two protection states exit, the voltage difference between the voltage of the VM end and the voltage of the G end is detected to be less than VEDIAnd exits the protection state continuously after a certain delay time. The main difference between the two is the short-circuit protection threshold VSCGreater than VEDIAnd T isSCLess than TEDIThat is, the delay time is shortened when the discharge current increases. The short-circuit current threshold is determined by:
this is because the larger the discharge current is, the larger the power consumption generated in the same time becomes for a certain battery voltage, and the larger the amount of heat generated becomes. Many electronic systems are damaged by overheating. Usually, a specific heat value of a specific system is provided, and the temperature rise caused by a certain amount of heat can be calculated. When the temperature rises to a certain value, the system is damaged. A delay time is required to fold back with the discharge current. If the battery voltage is VBCurrent is IBThe heat P generated at a certain time T is:
P=VB.IB.T
fig. 2 is a graph of discharge overcurrent delay time as a function of over-discharge current in the circuit of fig. 1.
When the over-discharge current is at I, as shown in FIG. 2EDI1And ISCIn between, the discharge overcurrent delay time is TEDI1When the over-discharge current exceeds the short-circuit protection current threshold ISCTime, discharge overcurrent delay time becomes TSC. Obviously, ISC、IEDI1The value of (A) varies from large to small, TSC、TEDIThe value of (d) is changed from small to large, i.e., the larger the overdischarge current value, the shorter the discharge overcurrent delay time.
Fig. 3 is a battery protection circuit employing three-stage discharge overcurrent protection.
Since the boundary I can also appear in real systemsEDIAnd ISCIn order to achieve more sufficient protection, the S8261 of the fine work electronics adopts three-level current protection (discharge overcurrent protection 1, discharge overcurrent protection 2 and short-circuit protection), as shown in fig. 3. The circuit comprises an overcharge detection circuit, an overdischarge detection circuit, a charge overcurrent detection circuit, a discharge overcurrent detection circuit 1, a discharge overcurrent detection circuit 2, a short-circuit protection detection circuit, a control circuit and switches MD and MC. The discharge overcurrent protection principle of the circuit is the same as that of the circuit shown in FIG. 1. It is different in that it addsThe discharge overcurrent detection circuit 2. Wherein, the threshold value I of the discharge overcurrent protection 2EDI2Threshold I of specific discharge overcurrent protection 1EDI1Delay time T of high, discharge overcurrent protection 2EDI2Delay time T of specific discharge overcurrent protection 1EDI1Short. Thus realizing the pair IEDIAnd ISCAnd protecting the discharge overcurrent state.
Fig. 4 is a graph of discharge overcurrent delay time as a function of over-discharge current in the circuit shown in fig. 3.
As shown in FIG. 4, when the over-discharge current is at IEDI1And IEDI2In between, the discharge overcurrent delay time is TEDI1. When over-discharge current is in IEDI1And ISCIn between, the discharge overcurrent delay time is TEDI2. When the over-discharge current exceeds the short-circuit protection current threshold ISCTime, discharge overcurrent delay time becomes TSC. Obviously, ISC、IEDI2、IEDI1The value of (A) varies from large to small, TSC、TEDI2、TEDI1The value of (d) is changed from small to large, i.e., the larger the overdischarge current value, the shorter the discharge overcurrent delay time.
Since the boundary I can also appear in real systemsEDI1And IEDI2Between or bounded by IEDI2And ISCAny other overcurrent conditions in between, so these intermediate discharge overcurrent conditions need to be protected. In short, the discharge overcurrent protection time of continuous turn-back is realized, and the turn-back relation is that the discharge overcurrent delay time is inversely proportional to the discharge overcurrent value.
Fig. 5 is a battery protection circuit according to an embodiment of the present invention.
As shown in fig. 5, the circuit includes an overcharge detection circuit, an overdischarge detection circuit, a charge overcurrent detection circuit, a discharge overcurrent detection circuit whose delay time is inversely proportional to the current, a control circuit, and switches MD and MC. In the figure, a discharge overcurrent detection circuit with time delay inversely proportional to current is used for detecting voltage aiming at discharge overcurrent protection. The relationship between the overdischarge current and the discharge overcurrent delay time follows:
wherein T isEDIDelay time for discharge over-current, IEDIFor over-discharge current, Q is a design constant.
Fig. 6 is a graph of discharge delay time versus over-discharge current in the circuit shown in fig. 5.
As shown in fig. 6, the discharge overcurrent delay time TEDIInversely proportional to the over-discharge current IEDIThereby realizing the continuous variation of the discharge overcurrent delay time along with the over-discharge current.
Fig. 7 shows a discharge overcurrent protection circuit according to the present invention in which the discharge delay time is inversely proportional to the discharge current value.
As shown in fig. 7, the circuit diagram includes an operational amplifier, an EDI (discharge overcurrent) comparator, MP1 (P-type field effect transistor), MP2, MP3, an inverter U1, a resistor R1, MN1 (N-type field effect transistor), MN2, a capacitor C1, an oscillator comparator, and a timer.
The positive phase input end of the EDI comparator is VM, and the negative phase input end is a discharge overcurrent voltage threshold value V set by the systemEDIThe output ends of the two-way inverter are respectively connected to the input end of the inverter U1 and the gate of the MP 3;
the inverting input end of the operational amplifier is connected to the VM end, the non-inverting input end of the operational amplifier is connected with the drain electrode of the MP1 and is connected to one end of the resistor R1, and the output end of the operational amplifier is connected to the drain electrode of the MP3 and the grid electrodes of the MP1 and MP 2;
the sources of MP1, MP2 and MP3 are all connected to VCC end, the drain of MP1 is connected to resistor R1, the drain of MP2 is connected to the drains of MN1 and MN2, one end of capacitor C1 and the non-inverting input end of the oscillator comparator respectively;
the inverting input of the oscillator comparator is the reference voltage V set by the systemREF;
The other end of the resistor R1 is grounded;
the source of MN1 is grounded, and the grid is respectively connected to the output end of the oscillator comparator and the input end of the timer;
MN2 has its gate connected to the output of the inverter and its source connected to the other end of capacitor C1 and to ground.
When VM is larger than VEDIAt this time, MP3 is turned off, MN2 is also turned off, and the op-amp and oscillator are both turned on. The operational amplifier adjusts the voltage at its non-inverting input to be equal to the voltage at its inverting input, so that the current flowing through R1 is equal to VM/R1. This current flows out from the drain of MP2 via the mirror of the current mirror circuit constituted by MP1 and MP2, and charges capacitor C1. When the voltage at C1 rises to VREFWhen the voltage of the oscillator comparator is low, MN1 is turned off, and the voltage of C1 is continuously charged and increased by the drain of MP2, and the oscillation is formed. And after the timer counts N periods, the EDI of the protection signal becomes high, and overcurrent protection control is carried out. Here, the timer is not necessary, but its adoption can make the capacitance of C1 reduced, thereby saving chip area.
The oscillator comparator needs to be designed with a certain delay time, which is generally less than 100nS and greater than 10 nS. Specifically, when the oscillator outputs a high level, the gate of MN1 is at a higher voltage, typically the supply voltage. In particular, the discharging current after MN1 turns on is much larger than the current of MP2 (i.e., the charging current of capacitor C1). Generally, the discharge time of the capacitor C1 is less than 5% of the oscillation period, negligible with respect to its charge time. It is also desirable that the voltage at C1 be discharged to zero during this discharge time. The oscillating signal generated by charging and discharging the capacitor C1 is a sawtooth wave. The width-to-length ratio of MN2 in the discharge circuit is generally greater than 5: 1 to meet the design requirement.
When VM is less than VEDIAt this time, MP3 is on, MN2 is also on, and both the op-amp and the oscillator are off.
The currents of the MP1 and the MP2 are in a mirror relationship, and can be equal or M times. In an actual circuit design, the MP1 and MP2 can be designed according to specific requirements of discharge overcurrent delay time and cost, thereby determining the multiple relation of the current flowing between MP1 and MP 2. In one embodiment of the present invention, the ratio of the current flowing through MP1 to the current flowing through MP2 is 1, i.e., equal. In operation, the current through MP1 and MP2 is equal to VM/R1, where VM is the voltage at the VM node. Voltage of VM is equal to IEDI·(RON_MD+RON_MC). MP2 outputs a current whose value is proportional to voltage VM to start the oscillator. Period T of the oscillatorOSCComprises the following steps:
timing delay T over N cyclesDEqual to N.TD。
Wherein,
from the above, it can be seen that the delay time TD and the over-discharge current IEDIIn inverse proportion.
According to the functional principle division, the operational amplifier, MP1, MP2 and resistor R1 in fig. 7 can be regarded as a voltage-controlled current source, and MP3 can be regarded as an enable control circuit. In addition, the capacitor C1, the oscillator comparator, and the MN1 in fig. 7 can be regarded as an oscillation unit, and the inverters U1 and MN2 can be regarded as an enable control circuit. The circuit generalizations described herein should not be considered limiting, but rather illustrative. In other words, the voltage-controlled current source, the oscillation unit and the two respective enable control circuits may be replaced by other devices/circuits having different components but achieving the same function.
Fig. 8 is a structured circuit diagram of the circuit shown in fig. 7.
According to the circuit generalization/structuring described in fig. 7, the circuit shown in fig. 8 preferably includes a discharge overcurrent (EDI) comparator, a voltage-controlled current source, an enable control circuit 1, an oscillation unit, an enable control circuit 2, and a timer.
The input end of the enabling control circuit 1 is connected to the output end of the discharging overcurrent comparator, and the output end of the enabling control circuit is connected to the enabling control end of the voltage-controlled current source and used for starting the voltage-controlled current source according to the judgment result of the discharging overcurrent comparator; the input end of the voltage-controlled current source receives the discharging overcurrent voltage, and the output end of the voltage-controlled current source is the output end of the voltage-controlled current source circuit and is used for generating a current with the value proportional to the discharging overcurrent voltage value. In the embodiment illustrated in fig. 7, the current generated by the voltage controlled current source circuit is inversely proportional to the discharge overcurrent voltage. The reason for this is that the current generated by the voltage-controlled current source is proportional to the discharge overcurrent voltage, and the oscillation period of the oscillator is inversely proportional to the current generated by the voltage-controlled current source.
The input end of the enable control circuit 2 is connected to the output end of the discharging overcurrent comparator, and the output end of the enable control circuit is connected to the enable control end of the oscillation unit, so that the oscillation unit is started according to the judgment result of the discharging overcurrent comparator. It should be noted that the enable control circuit described herein may be any circuit that can implement enable control and may be constructed of different components to achieve this purpose. The input end of the oscillation unit receives the current generated by the voltage-controlled current source circuit, and the output end of the oscillation unit is the output end of the oscillator and is used for generating an oscillation signal with an oscillation period proportional to the current and performing discharge overcurrent protection according to the oscillation signal.
As shown in fig. 8, the EDI comparator is used to determine whether an overcurrent condition occurs, and its two input terminals are VM and V, respectivelyEDI,VEDIA reference voltage set for the system. When the voltage at the VM terminal is higher than VEDIWhen the voltage-controlled current source is in operation, the circuit with the delay time inversely proportional to the overdischarge current starts to work, namely, the enable control circuits 1 and 2 are respectively sent out enable signals, and then the voltage-controlled current source and the oscillating unit are started by the enable control circuits. Otherwise, the circuit in which the delay time is inversely proportional to the overdischarge current is inhibited from operating. In operation, the voltage controlled current source generates a current source. Preferably, the current value of the current source is proportional to VM according to specific circuit designA voltage. The current source outputs to the oscillation unit, and the oscillation period of the oscillation unit is inversely proportional to the current value. The timer is used for timing according to the oscillation signal of the oscillation unit, and the discharge overcurrent delay time is N times of the period of the oscillation signal. From the description of fig. 7, it can be seen that N is also theoretically a design constant related to Q.
Fig. 9 is a structured circuit diagram of the circuit shown in fig. 8.
Similar to the transition from fig. 7 to fig. 8, fig. 8 can be further generalized/structured functionally into the circuit diagram shown in fig. 9. Preferably, the enable control circuit 1 and the voltage-controlled current source shown in fig. 8 may constitute one voltage-controlled current source circuit, and the enable control circuit 2 and the oscillation unit may constitute one oscillator.
As shown in fig. 9, the voltage-controlled current source circuit includes an input terminal for receiving the discharging overcurrent voltage, an enable control terminal for receiving the output of the discharging overcurrent comparator, and an output terminal for outputting to the oscillator, and is configured to generate a current having a current value proportional to the discharging overcurrent voltage value and output to the oscillator; the oscillator comprises an input end for receiving the current generated by the voltage-controlled current source circuit, an enable control end for receiving the output of the discharging overcurrent comparator and an output end, and is used for generating an oscillation signal with an oscillation period proportional to the current and outputting the oscillation signal to the timer, and the timer performs timing according to the oscillation signal so as to perform discharging overcurrent protection.
Fig. 10 is a structured circuit diagram of the circuit shown in fig. 9.
Again, fig. 9 can be further generalized/structured in functional principle into the circuit diagram shown in fig. 10. Preferably, the voltage-controlled current source circuit and the oscillator shown in fig. 9 may constitute one voltage-controlled oscillation circuit.
As shown in fig. 10, the circuit includes a discharge overcurrent comparator and a voltage-controlled oscillation circuit, wherein: the two inputs of the discharging overcurrent comparator are discharging overcurrent voltage and a discharging overcurrent voltage threshold (VEDI), the output end of the discharging overcurrent comparator is connected to the enabling control end of the voltage-controlled oscillation circuit, and the discharging overcurrent comparator is used for judging whether an overcurrent state occurs or not and starting the voltage-controlled oscillation circuit when the overcurrent state occurs; the voltage-controlled oscillating circuit comprises an input end for receiving the discharging overcurrent voltage, an enable control end for receiving the output of the discharging overcurrent comparator and an output end for outputting an oscillating signal, the oscillating signal is used for generating an oscillating signal with an oscillating period proportional to the discharging overcurrent voltage and outputting the oscillating signal to the timer, and the timer performs timing according to the oscillating signal so as to perform discharging overcurrent protection.
It will be obvious that many variations of the invention described herein are possible without departing from the true spirit and scope of the invention. Accordingly, all changes which are obvious to one skilled in the art are intended to be included within the scope of the appended claims. The scope of the invention is only limited by the appended claims.