CN101046789A - Data transmission method, firmware updating method and bus loader - Google Patents
Data transmission method, firmware updating method and bus loader Download PDFInfo
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- CN101046789A CN101046789A CN 200610020564 CN200610020564A CN101046789A CN 101046789 A CN101046789 A CN 101046789A CN 200610020564 CN200610020564 CN 200610020564 CN 200610020564 A CN200610020564 A CN 200610020564A CN 101046789 A CN101046789 A CN 101046789A
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Abstract
The present invention provides a data transmission method, firmware up-grade method and bus down-loader. Said invention relates to communication technology, PC machine parallel interface bus technology, I2C bus technology, microcontroller technology and application program programming technology. Said invention utilizes PC machine parallel interface and application program analog I2C main equipment, and utilizes two ports of I2C bus down-loader and respectively makes them be connected with PC machine parallel interface and ADuC70xxBCPZxxI chip I2C pin to make down-load of firmware.
Description
Technical field
The present invention relates to the communication technology, particularly PC parallel port bussing technique, I
2C bussing technique, microcontroller technology and application programming technology.
Background technology
ADuC70xxBCPZxxI be ADI (ADI) produce based on the accurate simulation of ARM7TDMI microcontroller (MicroConverter), be widely used in optical communication field, and expand to automobile industry, Industry Control, and sensor industry.This chip can change JTAG emulator or USB commentaries on classics I by USB
2The C downloader is realized firmware downloads, not only needs expensive hardware supported, but also needs the user related development experience to be arranged with the operational complicacy dealing with USB interface and brought and unusual.Technical matters to be solved by this invention is to utilize the PC parallel port to realize I
2The C hardware interface utilizes the PC application program to realize I
2The C software interface has characteristics such as low cost, high reliability, high ease for use, high portability, especially supports online download, has made things convenient for the debugging and the upgrading of firmware.
Summary of the invention
Technical matters to be solved by this invention is, a kind of low cost is provided and simple and practical the ADuC70xxBCPZxxI chip realized the data transmission of firmware and the method for firmware downloads, and the bus loader of realizing aforementioned data transmission and firmware downloads method.
The technical scheme that the present invention solve the technical problem employing is, a kind of data transmission method is provided, and utilizes PC parallel port and application program Simulation with I
2The C main equipment utilizes the parallel port to change I
2Two ports of C bus loader connect PC parallel port and ADuC70xxBCPZxxI chip I respectively
2The C pin carries out the download of firmware.
Further, realize PC parallel port and I by application program
2The protocol conversion of C interface, with the ADuC70xxBCPZxxI chip of external unit with I
2The C agreement is carried out communication.
The present invention also provides a kind of employing parallel port to change I
2The C bus data transmission method is realized parallel port commentaries on classics I
2The method of C bus firmware upgrade may further comprise the steps: the ADuC70xxBCPZxxI chip is carried out initialization; Wipe legacy data; Write more new data; Checking data.
The present invention also provides a kind of bus loader, and parallel port the 2nd pin connects the input end of first level converter, the output terminal of described first level converter and I
2C first interface pin links to each other; Parallel port the 3rd pin connects the input end of second level converter, the output terminal of described second level converter, I
2C interface the 3rd pin and parallel port the 12nd pin are connected in a bit.
The invention has the beneficial effects as follows and utilize the PC parallel port to realize I
2The C hardware interface utilizes the PC application program to realize I
2The C software interface because device is few and be homemade entirely, has characteristics such as low cost, high reliability, high ease for use, high portability, especially supports online download, has made things convenient for the debugging and the upgrading of firmware.
The present invention is further illustrated below in conjunction with embodiment and accompanying drawing.
Description of drawings
Fig. 1 is a hardware connection diagram of the present invention.
Fig. 2 is a hardware elementary diagram of the present invention.Wherein, V1: first level converter; V2: second level converter; X1:PC machine parallel port; X2:I
2C interface.
Fig. 3 is a running software synoptic diagram of the present invention.
Embodiment
The present invention utilizes PC parallel port and application program to come Simulation with I
2The C main equipment is realized the I with ADuC70xxBCPZxxI
2The C communication.
System of the present invention connection diagram such as Fig. 1, hardware elementary diagram such as Fig. 2.As shown in Figure 2, adopt the NPN triode to constitute the OC door on the hardware, to meet I
2The connected mode of C standard defined.Fig. 3 is the running software synoptic diagram.
Application program of the present invention is compatible following standard or agreement fully: " Intel HEX File Format ", " I
2C Download Protocol for ADuC70xxBCPZxxI Models " and " THE I
2C-BUSSPECIFICATION ".
Connect the PC parallel port to the downloader parallel port by Fig. 1, connect downloader I
2C interface is to the I of ADuC70xxB-CPZxxI
2The C pin.
After described downloader connects hardware system, by PC application program Simulation with I
2The C sequential is to guarantee the I with ADuC70xxBCPZxxI
2C carries out communication.Application Program Interface such as Fig. 4, order is carried out " Open ", " Start ", " Erase ", " Program ", and " Verify ", " Run " can download to a hex file data in the ADuC70xxBCPZxxI chip and go.Open the hex file of need downloading by the Open key, read in valid data to a data buffer zone and be presented in the form, have miscue if make mistakes; Behind the confirmation of synchronization of shaking hands by realization of Start key and ADuC70xxBCPZxxI, just can carry out erase operation to ADuC70xxBCPZxxI.What erase operation adopted is monoblock flash erase mode, still less more consuming time than inserting the mode of removing page by page like this.Wipe the back and passed through the Program data download in ADuC70xxBCPZxxI.Can carry out verification after having downloaded, will have bomp if make mistakes; If verification succeeds by the Run key, just can be carried out the firmware that just downloads among the ADuC70xxBCPZxxI immediately.
The bus data transmission mode is to utilize PC parallel port and application program Simulation with I
2C main equipment, main equipment are to utilize application program to produce Simulation with I
2The C signal, peripheral ADuC70xxBCPZxxI chipset is a slave unit, receives the data of PC transmission.Utilize the parallel port to change I
2Two ports of C bus loader connect PC parallel port and ADuC70xxBCPZxxI chip I respectively
2The C pin carries out the download of data.PC parallel port the 2nd pin send the SCL signal through the first level converter V1 to I
2C interface the 1st pin, PC parallel port the 3rd pin send the SDA signal through second level converter V2 and the I
2The signal that C interface the 3rd pin is drawn closes the road, with the SDA signal feedback to PC parallel port pin 12.
Further, realize PC parallel port and I by application program
2The protocol conversion of C interface, format transformation is with reference to " I
2C Download Protocol for ADuC70xxBCPZxxI Models ", with the ADuC70xxBCPZxxI chip of external unit with I
2The C agreement is carried out communication.
The present invention also provides a kind of realization parallel port to change I
2The method of C bus firmware upgrade may further comprise the steps: the ADuC70xxBCPZxxI chip is carried out initialization, wipes legacy data, writes the more operation of new data, checking data.
The frame mode of bus loader provided by the invention is as follows: parallel port the 2nd pin connects the input end of the first level converter V1, the output terminal of the described first level converter V1 and I
2C the 1st interface pin links to each other; Parallel port the 3rd pin connects the input end of the second level converter V2, the output terminal of the described second level converter V2 and I
2C interface the 3rd pin is connected in the A point, and the A point links to each other with parallel port the 12nd pin by resistance R 5.
Further, the first level converter V1 comprises a NPN triode Q1 and two resistance R 1, R3, and the base stage of NPN triode Q1 connects the input end of resistance R 1 as the first level converter V1; Power supply is connected in the B point by the collector of resistance R 3 and NPN triode Q1, the B o'clock output terminal as the first level converter V1; The grounded emitter of NPN triode Q1.
Further, the second level converter V2 comprises a NPN triode Q2 and two resistance R 2, R4, and the base stage of NPN triode Q2 connects the input end of resistance R 2 as the second level converter V2; Power supply is connected in the C point by the collector of resistance R 4 and NPN triode Q2, the C o'clock output terminal as the second level converter V2; The grounded emitter of NPN triode Q2.
Further, parallel port the 18th, 19,20,21,22,23,24,25 pin ground connection, the 1st, 4,5,6,7,8,9,10,11,13,14,15,16,17 pins are unsettled; I
2C interface the 2nd pin ground connection, the 4th pin connects power supply.
Below be bus data transmission and the concrete functional description of firmware upgrade.
About being described below of " Open " function.Firmware among the ADuC70xxBCPZxxI is the recordable paper at the Intel HEX form that generates for compiling under keil uVersion3 environment.Intel HEX file is the capable ASCII text file of recording text, in Intel HEX file, each row is a machine code or a static data that the HE-X record is made up of sexadecimal number, and Intel HEX file is often used in program or data transmission are stored in the nonvolatile memories such as ROM or EPROM.In conjunction with the HEX document instance of an A-DuC7020, illustrate how application program of the present invention realizes the analysis of HEX file:
:020000040008F2
:1000000018F09FE518F09FE518F09FE518F09FE5C0
……
:00000001FF
First row shows that the expansion linear address is recorded as 0008h; Second row shows that the skew first address of this line data record is 0000h, and 10h data are respectively 00,18 altogether, F0,9F, E5,18, F0,9F, E5,18, F0,9F, E5,18, F0,9F, E5; C0 is a check code.Last column shows that this document finishes.Because the firmware data of ADuC70xxBCPZxxI can not surpass the 62k byte, so defined the array of a 62k byte in application program, the content of its each unit is by the specified data decision of above-mentioned offset address.
For convenience of description, this paper calls host computer to PC, and the ADuC70xxBCPZxxI chip is called slave computer.
About being described below of " Start " function.In a single day slave computer enters downloading mode, and its P1.0 and P1.1 pin promptly are configured to from I
2The C device pin, and from I
2The C address of devices is 04h.Host computer sends 08h to begin with presentation protocol to slave computer.Slave computer receives ID packet ADuC702x<space that 08h sends later on 24 bytes〉<space〉<space 〉-62 H5T represent response; Wherein " ADuC702x " is product mark, " 62 " respective devices memory size, and " H5T " is hardware and version number, and H represents silicon, and 5 represent version number, and T represents revisions number.
Host computer just can begin data transmission after receiving the ID packet, and data packet format sees Table 1.
Start ID | No.of | Data | 1 CMD | Data 2->5 (Address:h, u,m,l) | Data x (x=6 ->25) | Checksum | |
07h | 0Eh | 5->255 | ‘E’,‘W’, ‘V’or‘R’ | h,u,m,l | XX | No of DataBytes +Data1+Data2->5 +∑Datax (2’s Comp) |
Table 1 data transmission format
" Start ID " comprises 2 byte 07H and 0EH, begins to represent an effective data packets." No.ofData Bytes " expression needs the data number of transmission, and minimum is 5, mostly is 255 most." Data 1 CMD " command format, wherein the E representative is wiped, and W represents to write, and V represents verification, and R represents operation.32 FALSH/EE specific address that " Data2-〉5 (Address:h, u, m, l) " indicates to operate, h represents MSB, and l represents LSB." Data x (x=6-〉55) " be the actual download data, data layout is necessary for the HEX form of Intel expansion." Checksum " be verification and.
About being described below of " Erase " function.Erase command allows to wipe any one page of FALSH, and page address is by Data 2-〉decision of 5 address informations, for example wipe the address from 0x00000000, need wipe 00 page, duty erase command data packet format such as table 2.
Start ID | No.of | Data | 1 CMD | Data 2->5 (Address:h,u,m,l) | Data 6 (pages) | Checksum | |
07h | 0Eh | 6 | ‘E’ (45h) | h,u,m,l | x pages | No of DataBytes +∑Data (2’s Comp) |
Table 2 erase command form
About being described below of " Program " function.Write order relates to data 1+data 2 → 5+datax, slave computer will write FLASH/EE with data after receiving data immediately, if checksum not to or the address go beyond the scope, slave computer will send the BEL signal, after main frame is received the BEL signal, should stop order immediately.Download can only restart.Write order form such as table 3.
Start ID | No.of | Data | 1 CMD | Data 2->5 (Address:h,u,m,l) | Datax (x=1->250) | | |
07h | 0Eh | ||||||
5+No.of Data x (6->255) | ‘W’ (57h) | h,u,m,l | … | No of DataBytes +∑Data Bytes 1-515 |
Table 3 write order form
Application program of the present invention has been divided into 256 pages to the 62k byte data, every page of 248 byte datas when programming.In view of I
2The situation of C communication abnormality might take place (such as chip rosin joint, I
2C cable loose contact, unusual shutdown of host computer etc.), so when downloading, do not write homepage earlier, the content that promptly keeps is 0xffffffff 80014h the address in, treat that other pages all write data after, write homepage again.Even download what accident has taken place and caused downloading interruption so midway, slave computer still can be downloaded once more, otherwise will cause this ADuC70xxBCPZxxI chip rejection.
About being described below of " Verify " function.In order to improve the error correcting capability that detects data, the data that need check have been displaced to from high 5 hangs down 5, and low 3 have been moved to high 3.Slave computer can compare with the content that is written in the FLASH/EE by the correct tagmeme of automatic restore data then, correctly returns 06h, and mistake is returned 07h.The check command form is as shown in table 4.
StartID | No.of | Data | 1 CMD | Data 2->5 (Address:h,u,m,l) | Datax (x=1->250) | | |
07h | 0Eh | ||||||
5+No.of Data x (6->255) | ‘V’ (56h) | h,u,m,l | Complemented data bytes | No of Data Bytes +∑Data Bytes 1-515 |
Table 4 check command form
About being described below of " Run " function.After all data were downloaded and finished, main frame just can send the " RUN " order so that processor begins to carry out the user program code from given address, and slave computer supports the Flash/EE address to begin from (h, u, m, l=80000h or 80001h) at present.Personal code work action command form is as shown in table 5.
Start ID | No.of Data Bytes | Data 1 (Command) | Data 2->5 (Address:h,u,m,l) | Checksum | |
07h | 0Eh | 05h | ‘R’ (52h) | h,u,m,l | A9h |
Table 5 action command form
Claims (6)
1, a kind of data transmission method is characterized in that, utilizes PC parallel port and application program Simulation with I
2The C main equipment utilizes the parallel port to change I
2Two ports of C bus loader connect PC parallel port and ADuC70xxBCPZxxI chip I respectively
2The C pin carries out the download of firmware; Realize PC parallel port and I by application program
2The conversion of C agreement, with the ADuC70xxBCPZxxI chip of external unit with I
2The C agreement is carried out communication.
2, adopt the described employing of claim 1 parallel port to change I
2The C bus data transmission method is realized parallel port commentaries on classics I
2The method of C bus firmware upgrade is characterized in that, may further comprise the steps:
The ADuC70xxBCPZxxI chip is carried out initialization;
Wipe legacy data;
Write more new data;
Checking data.
3, bus loader is characterized in that, parallel port the 2nd pin connects the input end of first level converter (V1), the output terminal and the I of described first level converter (V1)
2C interface the 1st pin links to each other; Parallel port the 3rd pin connects the input end of second level converter (V2), the output terminal and the I of described second level converter (V2)
2C interface the 3rd pin is connected in (A) point, (A) links to each other with parallel port the 12nd pin by resistance (R5).
4, bus loader as claimed in claim 3, it is characterized in that first level converter (V1) comprises NPN triode (Q1), resistance (R1, R3), the base stage of NPN triode (Q1) connects the input end of resistance (R1) as first level converter (V1); Power supply is connected in (B) point by the collector of resistance (R3) and NPN triode (Q1), (B) o'clock as the output terminal of first level converter (V1); The grounded emitter of NPN triode (Q1).
5, bus loader as claimed in claim 3, it is characterized in that second level converter (V2) comprises NPN triode (Q2), resistance (R2, R4), the base stage of NPN triode (Q2) connects the input end of resistance (R2) as second level converter (V2); Power supply is connected in (C) point by the collector of resistance (R4) and NPN triode (Q2), (C) o'clock as the output terminal of second level converter (V2); The grounded emitter of NPN triode (Q2).
6, bus loader as claimed in claim 3 is characterized in that parallel port the 18th, 19,20,21,22,23,24,25 pin ground connection, and the 1st, 4,5,6,7,8,9,10,11,13,14,15,16,17 pins are unsettled; I
2C interface the 2nd pin ground connection, the 4th pin connects power supply.
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CN102033770B (en) * | 2010-12-17 | 2015-01-28 | 中兴通讯股份有限公司 | Touch screen firmware upgrading method and device for mobile terminal |
CN102033770A (en) * | 2010-12-17 | 2011-04-27 | 中兴通讯股份有限公司 | Touch screen firmware upgrading method and device for mobile terminal |
CN102855151B (en) * | 2012-08-21 | 2016-06-08 | 武汉电信器件有限公司 | The optical module firmware not interrupting business is in application upgrade method |
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CN107678770A (en) * | 2017-09-14 | 2018-02-09 | 硅谷数模半导体(北京)有限公司 | Interface chip upgrade method, device, storage medium and processor |
CN107678770B (en) * | 2017-09-14 | 2021-03-09 | 硅谷数模半导体(北京)有限公司 | Interface chip upgrading method and device, storage medium and processor |
CN109684246A (en) * | 2018-12-19 | 2019-04-26 | 东莞博力威电池有限公司 | The method and system carried out data transmission between the equipment of distinct interface agreement |
CN110597537A (en) * | 2019-08-29 | 2019-12-20 | 南宁学院 | Safe updating and upgrading method for nodes of Internet of things |
CN110597537B (en) * | 2019-08-29 | 2022-12-13 | 桂林理工大学南宁分校 | Safe updating and upgrading method for nodes of Internet of things |
CN110908689A (en) * | 2019-11-27 | 2020-03-24 | 杭州莱宸科技有限公司 | Program upgrading interface circuit, embedded device, downloading interface circuit and downloader |
CN110908689B (en) * | 2019-11-27 | 2023-09-15 | 杭州莱宸科技有限公司 | Program upgrade interface circuit, embedded device, download interface circuit, and downloader |
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