CN101034890A - Disorder bit compensation circuit for gradual approaching A/D converter - Google Patents
Disorder bit compensation circuit for gradual approaching A/D converter Download PDFInfo
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- CN101034890A CN101034890A CN 200710020386 CN200710020386A CN101034890A CN 101034890 A CN101034890 A CN 101034890A CN 200710020386 CN200710020386 CN 200710020386 CN 200710020386 A CN200710020386 A CN 200710020386A CN 101034890 A CN101034890 A CN 101034890A
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Abstract
The invention relates to disorder place compensation circuit which is used for successive approximation type analog to digital converter, belongs to the digital-analog composite signal processing technology area, in the circuit the first inout end of the comparator outputs produce circuit and disorder place compensate produce circuit connects the first clock signal, the second input end of the comparator outputs produce circuit and disorder place compensate produce circuit connects the comparator compare result, the output of the comparator outputs produce circuit and disorder place compensate produce circuit separately corresponding connects the two input ends of the analog to digital converter output adjustment circuit, the clock input end of which connects the second clock signal, and lead out the output data signal and overflow signal of the analog to digital converter from the analog to digital converter output adjustment circuit. The set fuction of the circuit enhances transferring speed of the analog to digital converter, in the meantime, adjustes the output signal through increase compensation place and use the output adjustment circuit, eliminates the error by set in advance and produces the overflow signal.
Description
Technical field
The present invention relates to a kind of disorder bit compensation circuit that is used for gradual approaching A/D converter, belong to the digital-to-analogue mixed signal processing technology field.
Background technology
Gradual approaching A/D converter is one of now popular A/D converter with high speed and high precision structure, in the common gradual approaching A/D converter circuit of realizing with switched capacitor network, the time of capacitor charge and discharge is the deciding factor that influences switching rate, has caused the reduction of analog to digital converter switching rate because of the increase of capacitor charge and discharge time constant.
Summary of the invention
Technical problem: the object of the present invention is to provide a kind of disorder bit compensation circuit that is used for gradual approaching A/D converter, solve the problem that analog to digital converter switching rate that the increase owing to the capacitor charge and discharge time constant that exists in the above-mentioned prior art causes reduces, improve the switching rate of gradual approaching A/D converter.
Technical scheme: for realizing purpose of the present invention, disorder bit compensation circuit of the present invention, constitute by comparator output generation circuit, imbalance position compensation generation circuit, analog to digital converter output regulation circuit, wherein: the corresponding respectively valid data signal and first clock control signal that inserts comparator output of data-signal input, clock control signal input of comparator output generation circuit and imbalance position compensation generation circuit; The first input end of the output termination analog to digital converter output regulation circuit of comparator output generation circuit, the compensation of imbalance position produces second input of the output termination analog to digital converter output regulation circuit of circuit, the input end of clock of analog to digital converter output regulation circuit inserts the second clock control signal, draw the outputting data signals of analog to digital converter from the data-signal output of analog to digital converter output regulation circuit, draw spill over from the overflow position output.Comparator output generation circuit and disorder bit compensation circuit, under the control of clock signal, produce the output result and the imbalance position of comparator, utilization is to the function of the set of a certain phase place, add on electric capacity that in advance certain voltage deviation is to accelerate the capacitor charge and discharge process, thereby shorten the impulse electricity time of electric capacity, improve the switching rate of analog to digital converter, and revise because the error that set in advance may cause by increasing the compensation position.The analog to digital converter output regulation circuit is adjusted the output signal of comparator output generation and imbalance position generation circuit, elimination is used to improve the compensation position that is increased of conversion speed and produces spill over by adjusting, and judges whether the input signal of analog to digital converter surpasses input range.
Beneficial effect: disorder bit compensation circuit of the present invention, utilize comparator to produce circuit and a set function that produces circuit of lacking of proper care, shortened the impulse electricity time of electric capacity, improved the switching rate of analog to digital converter; Revise because in the error that set in advance may cause in increase compensation position, spill over is adjusted and produced to the output signal of the output regulation circuit by analog to digital converter, in the switching rate that improves analog to digital converter, increased the signal to noise ratio and the Spurious Free Dynamic Range of analog to digital converter again.
Description of drawings:
Fig. 1 is a disorder bit compensation circuit block diagram of the present invention.
Fig. 2 is that comparator output generation circuit of the present invention and the compensation of imbalance position produce circuit.
Fig. 3 is the output regulation circuit of analog to digital converter of the present invention.
Fig. 4 is that comparator of the present invention produces circuit and the imbalance position compensates the sequential chart that produces each phase place of circuit.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail.
Referring to Fig. 1, Fig. 1 is a theory diagram of the present invention.The disorder bit compensation circuit that is used for gradual approaching A/D converter of the present invention, constitute by comparator output generation circuit 10, imbalance position compensation generation circuit 20 and analog to digital converter output regulation circuit 30, wherein, the data input pin D20 that the data input pin D10 of comparator output generation circuit 10 and the compensation of imbalance position produce circuit 20 inserts comparator compare result signal Din1, and the input end of clock C20 that the input end of clock C10 of comparator output generation circuit 10 and the compensation of imbalance position produce circuit 20 inserts first clock signal clk 1; The output B101 of comparator output generation circuit 10 meets the first input end D301 of analog to digital converter output regulation circuit 30, and the output B201 of imbalance position compensation generation circuit 20 meets the second input D302 of analog to digital converter output regulation circuit 30; The input end of clock C30 of analog to digital converter output regulation circuit 30 inserts second clock signal CLK2, draw the outputting data signals of analog to digital converter from the data-signal output O301 of analog to digital converter output regulation circuit 30, O302 draws spill over from the overflow position output.Comparator output generation circuit 10 and the compensation of imbalance position produce circuit 20, under the control of first clock signal, produce the output result and the imbalance position of comparator, utilization is to the function of the set of one of them phase place, add on electric capacity that in advance certain voltage deviation is to accelerate the capacitor charge and discharge process, shorten the impulse electricity time of electric capacity, improve the switching rate of analog to digital converter, and by increasing a compensation position is revised because the error that set in advance may cause, in the switching rate that improves analog to digital converter, increased the signal to noise ratio and the Spurious Free Dynamic Range of analog to digital converter again.30 pairs of comparator output generation circuits of analog to digital converter output regulation circuit 10 and the compensation of imbalance position produce the output signal of circuit 20 and adjust, elimination is used to improve the compensation position that is increased of conversion speed and produces spill over by adjusting, and judges whether the input signal of analog to digital converter surpasses input range.
Referring to Fig. 2, Fig. 2 is the physical circuit figure that comparator output generation circuit 10 of the present invention and the compensation of imbalance position produce an embodiment of circuit 20.Among the figure, comparator output generation circuit 10 and the compensation of imbalance position produce circuit 20 by 11 unit cascaded forming, ten unit of comparator output generation circuit 10 correspond respectively to 10 valid data signal B0, B1, B2, B3, B04, B5, B6, B7, B8, B9, Unit the 11 is that the compensation of imbalance position produces circuit 20, corresponding to 1 compensation position B04; Each unit all is made up of a Phase Processing NAND gate, a rest-set flip-flop, a phase inverter and a transmission gate, the first input end of the output termination rest-set flip-flop of Phase Processing NAND gate, the input of the output termination phase inverter of rest-set flip-flop, the input of the output termination transmission gate of phase inverter, transmission gate is controlled by complementary clock signal NI and I, and this structure is used for the output result of latched comparator and under the control of first clock signal clk 1 latch signal being exported.Draw the valid data signal of analog to digital converter output from the output of transmission gate.
The 3rd unit 103, the 4th unit 104, the 5th unit 105, the inside of the 6th unit 106 and the rest-set flip-flop of imbalance position, Unit the 11 compensation generation circuit 20 constitutes and is connected identical, the 3rd rest-set flip-flop 1030 is made up of the three or three input nand gate 1031 and the four or three input nand gate 1032 cross-couplings in the 3rd unit 103, wherein, the 3rd input of the three or three input nand gate 1031 and the first input end of the four or three input nand gate 1032 are connected the other side's output respectively, the first input end of the three or three input nand gate 1031 and output are the first input end and the outputs of this trigger, second input of the three or three input nand gate 1031 is second inputs of this trigger, the 3rd input of the four or three input nand gate 1032 is the 3rd inputs of this trigger, and second input of the four or three input nand gate 1032 is set ends of this trigger.
The tenth unit 100, first module 101, second unit 102, the 7th unit 107, the inside of the 8th unit 108 and the rest-set flip-flop of the 9th unit 109 constitutes and is connected identical, the tenth rest-set flip-flop 1000 is made up of the 16 input nand gate 1001 and the 16 liang of input nand gate 1002 cross-couplings in the tenth unit 100, wherein, the 3rd input of the 16 input nand gate 1001 and the first input end of the 16 liang of input nand gate 1002 are connected the other side's output respectively, the first input end of the 16 input nand gate 1001 and output are the first input end and the outputs of this trigger, second input of the 16 input nand gate 1001 is second inputs of this trigger, and second input of the 16 liang of input nand gate 1002 is set ends of the tenth rest-set flip-flop.
Comparator compare result signal Din1 inserts the first input end of the Phase Processing NAND gate of described 11 unit respectively through first phase inverter 0001.
First clock signal clk 1 is at corresponding respectively second input that inserts the Phase Processing NAND gate of described the 9th unit 109, the 8th unit 108, the 7th unit 107, the 6th unit 106, the 5th unit 105, the 104, the 11 unit 20, Unit the 4th, the 3rd unit 103, second unit 102, first module 101, the tenth unit 100 of clock signal I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, the I16 of out of phase; First clock signal clk 1 is at the clock signal " I6; I7; I13; I14; I15; I8 of out of phase, I9, I10, I11, I12 " insert described the 8th unit 108 through separately phase inverter is corresponding respectively; the 7th unit 107; second unit 102; first module 101; the set end of the rest-set flip-flop of the tenth unit 100 and the 6th unit 106; the 5th unit 105, the 4th unit 104, Unit the 11 imbalance position compensation produces circuit 20, the 3rd input of the rest-set flip-flop of the 3rd unit 103; First clock signal clk 1 inserts the set end of the rest-set flip-flop 1030 of described the 3rd unit 103 through its phase inverter at I5 clock signals I5; First clock signal clk 1 inserts the set end of the rest-set flip-flop of second input of rest-set flip-flop of described the 7th unit 107, the 8th unit 108, the 9th unit 109, the tenth unit 100, first module 101, second unit 102 and the 6th unit 106, the 9th unit 109 respectively through second phase inverter 0002 at I1 clock signals I1; First clock signal clk 1 inserts second input of the rest-set flip-flop of the set end of rest-set flip-flop of described the 4th unit 104, the 5th unit 105, the 11 unit 20 and the 6th unit 106 respectively through the 3rd phase inverter 0003 at I3 clock signals I3; First clock signal clk 1 is at I1 and I4 clock signals I1 and corresponding respectively two inputs that insert first NOR gate 0004 of I4, and the output of first NOR gate 0004 connects second input of the rest-set flip-flop of the 4th unit 104, the 5th unit 105, the 11 unit 105 respectively; First clock signal clk 1 is at I1 and I10 clock signals I1 and corresponding respectively two inputs that insert second NOR gate 0005 of I10, second input of the rest-set flip-flop 1030 of output termination the 3rd unit 103 of second NOR gate 0005.
The operation principle of the embodiment of the invention is as follows: referring to Fig. 4, Fig. 4 is for comparator output generation circuit of the present invention and be compensated for as the sequential chart that produces each phase place of circuit, the compare result signal Din1 of the output of comparator is added in the input of first phase inverter 0001, the output of first phase inverter 0001 produces signal, connect the first input end of two input nand gates of the 9th unit 109, second input of this two input nand gate inserts first clock signal clk 1 at I6 clock signals I6, when this clock signal I6 rising edge arrives, the output signal of two input nand gates of the 9th unit 109 promptly is input signal Din1, if this signal is a logic high, then the rest-set flip-flop of the 9th unit 109 is set, and this moment B9 position logic high, if two input nand gates of the 9th unit 109 are output as logic low, the rest-set flip-flop of the 9th unit 109 is reset so, B9 position logic low.
The rest-set flip-flop that produces the 9th unit 109 of logic level B9 is reset when the I1 phase place of first clock signal clk 1, clock signal I1 be added in through the signal of second phase inverter 0002 the 9th unit 109 rest-set flip-flop second input.The rest-set flip-flop that produces the corresponding units of logic level B8, B7, B5, B4, B3, B2, B1, B0 also is reset when the I1 phase place of first clock signal clk 1.The rest-set flip-flop that produces Unit the 6th of logic level B6 is set when the I1 phase place of first clock signal clk 1 and is reset when the reversed phase signal I3N of first clock signal clk 1 in the I3 phase place, reversed phase signal I3N also will produce logic level B5 simultaneously, the rest-set flip-flop of the corresponding units of B4 and compensation position B04 resets, simultaneously, produce logic level B5, the rest-set flip-flop of the corresponding units of B4 and compensation position B04 also is reset when the I4 phase place of first clock signal clk 1, and the 3rd rest-set flip-flop 1030 that produces the 3rd unit 103 of logic level B3 is reset when the I10 phase place of first clock signal clk 1.
Except reset and the signal of set different, produce logic level B8, B7, B6, B5, B4, B3, B2, B1, B0 and to produce the operation principle of 10 rest-set flip-flops of other corresponding 10 unit of corresponding compensation position B04 identical with the operation principle of the rest-set flip-flop of the 9th unit 109 of generation logic level B9, the output of the rest-set flip-flop of all unit is connected on the transmission gate of being controlled by complementary clock signal NI and I, signal NI and I produce when phase place I16, when signal NI and I load on the transmission gate, 10 useful signal B9, B8, B7, B6, B5, B4, B3, B2, B1, B0 add a compensation position B04 totally 11 signals export analog to digital converter output regulation circuit 30 simultaneously to, analog to digital converter output regulation circuit 30 is converted into 10 useful signal O0 with 11 signals, O1, O2, O3, O4, O5, O6, O7, O8 and O9 be corresponding to the output of analog to digital converter, and produce an overflow position OVERFLOW and be used for judging whether to overflow.Table one is that logic level B9, B8, B7, B6, B5, B4, B3, B2, ten valid data of B1, B0 add a compensation position B04, and totally ten one each clock cycle capacitance voltages reset and the set situation.
As shown in Table 1, when the I5 phase place of first clock signal clk 1, can accelerate the switching rate of analog to digital converter for the set of logic level B3.By the precharge to electric capacity, what switching capacity needed when having shortened decision high-order digit amount discharges and recharges the time, and the time of shortening, the weight corresponding with B3 was directly proportional.After a high position produced, logic level B3 was reset, and had guaranteed the output of last correct digital quantity.Compensation position B04 is used for compensating because any error that in advance logic level B3 set may be caused.
| B9 | B8 | B7 | B6 | B5 | B4 | B04 | B3 | B2 | B1 | B0 | |
| I1 I2 I3 I4 | 0 0 0 0 | 0 0 0 0 | 0 0 0 0 | 1 1 0 0 | 0 0 1 0 | 0 0 1 0 | 0 0 1 0 | 0 0 0 0 | 0 0 0 0 | 0 0 0 0 | 0 0 0 0 |
| I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 I16 | 1 S S S S S S S S S S S | 0 1 S S S S S S S S S S | 0 0 1 S S S S S S S S S | 0 0 0 1 S S S S S S S S | 0 0 0 0 1 S S S S S S S | 0 0 0 0 0 1 S S S S S S | 0 0 0 0 0 0 1 S S S S S | 1 1 1 1 1 0 0 1 S S S S | 0 0 0 0 0 0 0 0 1 S S S | 0 0 0 0 0 0 0 0 0 1 S S | 0 0 0 0 0 0 0 0 0 0 1 S |
Each clock cycle capacitance voltage of table 1 resets and the set situation
The pairing weight of the B3 that is set in advance is
B3 is carried out the comparison speed that set can increase comparator in advance, thereby increase the switching rate of whole analog to digital converter, because the time constant that discharges and recharges of switched capacitor network is RC, wherein R is a switch resistance, C is a capacitance, discharge and recharge the time and discharge and recharge time constant and discharge and recharge before and after on the electric capacity variable quantity of voltage all relevant.When needs are determined the high-order digit amount, on electric capacity, add little voltage deviation in advance, then can shorten capacitor charge and discharge needed settling time, thereby accelerate charge and discharge process, allow analog to digital converter under higher switching rate, to work.For example, when the digital quantity of decision highest order correspondence, electric capacity at first will be charged to
After in advance B3 being carried out set, promptly to electric capacity with charge to
When the decision highest order, electric capacity only need be charged to
Definite highest order that just can be correct that is to say, if the input analog signal greater than
Just can determine the high-order digit amount at faster speed.After increasing digital quantity was determined, in the I10 phase place, B3 was reset, and comparator still can be worked under very high speed like this, and has guaranteed precision.Might introduce error but do like this, when the analog signal of importing exists
And when electric capacity can charge fully, for the decision of highest order error will appear.Thereby cause whole analog to digital converter wrong conversion to occur.For addressing the above problem, can increase a compensation position that weight is suitable, the weight of compensation position should be smaller, is in the present invention
After determining highest order, being judged whether by the compensation position should be with self weight
Promptly corresponding to the weight of B3 be added in change on the summing junction of comparator part and, thereby draw correct output result.The generation of compensation position can realize by increasing a clock cycle I11 in the I11 cycle, can determine whether comparator makes mistakes, thereby whether decision compensation position should obtain correct output result being added in summing junction.
Referring to Fig. 3, Fig. 3 is the physical circuit figure of an embodiment of analog to digital converter output regulation circuit 30 of the present invention.Among the figure, analog to digital converter output regulation circuit 30 is formed by 11 homophase latchs, 6 adders, 11 two input NOR gate, 11 transistors and 11 trigger cascades.The first homophase latch 302, the second homophase latch 303, the 3rd homophase latch 304, the 4th homophase latch 305, the 6th homophase latch 307, the 7th homophase latch 308, the 8th homophase latch 309, the 9th homophase latch 310, corresponding respectively 10 valid data signal B0, B1, B2, B3, B04, B5, B6, B7, B8, the B9 of inserting of the tenth homophase latch the 311, the 11 homophase latch 312, the 5th homophase latch 306 inserts 1 compensation position B04.The first homophase latch 302, the second homophase latch 303, the 3rd homophase latch 304, first liang of input of the corresponding respectively connection of the output of the 4th homophase latch 305 NOR gate 313, second liang of input NOR gate 314, the 3rd liang of input NOR gate 315, the first input end of the 4th liang of input NOR gate 316, the 5th homophase latch 306, corresponding two inputs that connect first adder 342 of the output of the 6th homophase latch 307, the 7th homophase latch 308, the 8th homophase latch 309, the 9th homophase latch 310, the tenth homophase latch 311, the corresponding respectively second adder 343 that connects of the output of the 11 homophase latch 312, the 3rd adder 344, the 4th adder 345, slender acanthopanax musical instruments used in a Buddhist or Taoist mass 346, second input of the 6th adder 347 is used to produce final comparative result.
Corresponding respectively second output that connects first adder 342, second adder 343, the 3rd adder 344, the 4th adder 345, slender acanthopanax musical instruments used in a Buddhist or Taoist mass 346 of the first input end of second adder 343, the 3rd adder 344, the 4th adder 345, slender acanthopanax musical instruments used in a Buddhist or Taoist mass 346, the 6th adder 347; The corresponding respectively first input end that connects the 5th liang of input NOR gate 317, the 6th liang of input NOR gate 318, the 7th liang of input NOR gate 319, the 8th liang of input NOR gate 320, the 9th liang of input NOR gate 321, the tenth liang of input NOR gate 322 of first output of first adder 342, second adder 343, the 3rd adder 344, the 4th adder 345, slender acanthopanax musical instruments used in a Buddhist or Taoist mass 346, the 6th adder 347;
The first transistor M1, transistor seconds M2, the 3rd transistor M3, the corresponding respectively first homophase latch 302 that connects of the grid of the 4th transistor M4, the second homophase latch 303, the 3rd homophase latch 304, the output of the 4th homophase latch 305, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7, the 8th transistor M8, the 9th transistor M9, the corresponding respectively first adder 342 that connects of the grid of the tenth transistor M10, second adder 343, the 3rd adder 344, the 4th adder 345, slender acanthopanax musical instruments used in a Buddhist or Taoist mass 346, first output of the 6th adder 347, the drain electrode of the 11 transistor M0 and described other ten transistor drain connect the first input end of the tenth liang of input NOR gate 323, the grid of the 11 transistor M0 and described other ten transistorized source grounds, the source electrode of the 11 transistor M0 connects power supply;
The input of the second output termination the 25 phase inverter 349 of the 6th adder 347, second input of described 11 the two input NOR gate of the output termination of the 25 phase inverter 349, the corresponding respectively data input pin that connects described 11 triggers of the output of described 11 two input NOR gate, the output signal of second clock signal CLK2 behind the 25 phase inverter 324 inserts the input end of clock of described 11 triggers, draw spill over OVERFLOW from the output of the 11 trigger 340, draw 10 bit data signals from the output of described other 10 triggers.
The operation principle of the embodiment of the invention is as follows: analog to digital converter outputs in the next stage circuit and goes through certain format conversion in the difference output from P0 to P15 constantly.Wherein, described 11 triggers are the master-slave mode trigger.When the signal rising edge that clock signal clk 2 produces through the 25 phase inverter 324, described 11 triggers upgrade and latch output; When the signal trailing edge that clock signal clk 2 produces through the 25 phase inverter 324, described 11 triggers receive data.This circuit is when being converted to the 10bit data to the 11bit data, can eliminate the adder circuit that compensates the position and produce overflow position, when input signal is lower than or is higher than the range of signal that analog to digital converter can handle, analog to digital converter will overflow, and produce overflow position misjudgment information.At first, for overflowing of making progress, as shown in Figure 3, by described 11 transistorized have than logic realize, because the input analog signal has surpassed the upper limit of the treatable peak signal of analog to digital converter, then the output signal of comparator output generation circuit 10 all is a logic high, be 1, and be connected on described 10 transistorized grids except that the 11 transistor by described 11 homophase latchs and described 11 adders, these transistor turns when these transistorized grid inputs are 1, the first input end that produces the 23 liang of input NOR gate 323 of overflow position OVERFLOW is 0, overflow position OVERFLOW is output as 1, the output of 10 data-signal outputs simultaneously is 1, and expression is upwards overflowed.Secondly, for downward overflowing, also by described transistorized have than logic realize, because the input analog signal has surpassed the lower limit of the treatable peak signal of analog to digital converter, then the output signal of comparator output generation circuit 10 all is a logic low, be 0, and be connected on described 10 transistorized grids except that the 11 transistor by described 11 homophase latchs and described 11 adders, when these transistorized grid inputs are 0, these transistors end, the first input end that produces the 23 liang of input NOR gate 323 of overflow position OVERFLOW is 1, by particular design to the 6th adder 347, make its second output be output as 1, then overflow position OVERFLOW is output as 1.The output of 10 data-signal outputs simultaneously is 0, and expression is overflowed downwards.
Claims (4)
1, a kind of disorder bit compensation circuit that is used for gradual approaching A/D converter, it is characterized in that, it comprises comparator output generation circuit (10), the compensation of imbalance position produces circuit (20) and analog to digital converter output regulation circuit (30), wherein: the data input pin (D20) that the data input pin (D10) of comparator output generation circuit (10) and the compensation of imbalance position produce circuit (20) inserts comparator compare result signal (Din1), and the input end of clock (C20) that the input end of clock (C10) of comparator output generation circuit (10) and the compensation of imbalance position produce circuit (20) inserts first clock signal (CLK1); The output (B101) of comparator output generation circuit (10) connects the first input end (D301) of analog to digital converter output regulation circuit (30), and the output (B201) of imbalance position compensation generation circuit (20) connects second input (D302) of analog to digital converter output regulation circuit (30); The input end of clock (C30) of analog to digital converter output regulation circuit (30) inserts second clock signal (CLK2), draw the outputting data signals (OUTPUT) of analog to digital converter from the data-signal output (O301) of analog to digital converter output regulation circuit (30), draw spill over (OVERFLOW) from overflow position output (O302).
2, the disorder bit compensation circuit that is used for gradual approaching A/D converter according to claim 1, it is characterized in that, comparator output generation circuit (10) and the compensation of imbalance position produce circuit (20) by 11 unit cascaded forming, ten unit of comparator output generation circuit (10) correspond respectively to 10 valid data signals, Unit the 11 is that the compensation of imbalance position produces circuit (20), corresponding to 1 compensation position; Each unit all is made up of a Phase Processing NAND gate, a rest-set flip-flop, a phase inverter and a transmission gate, the first input end of the output termination rest-set flip-flop of Phase Processing NAND gate, the input of the output termination phase inverter of rest-set flip-flop, the input of the output termination transmission gate of phase inverter, transmission gate is controlled by complementary clock signal NI and I, draws the data-signal of analog to digital converter output from the output of transmission gate.
3, the disorder bit compensation circuit that is used for gradual approaching A/D converter according to claim 1 and 2, it is characterized in that comparator output generation circuit (10) and the compensation of imbalance position produce in the circuit (20), Unit the 3rd (103), Unit the 4th (104), Unit the 5th (105), the inside of the Unit the 6th (106) and the rest-set flip-flop of Unit the 11 imbalance position compensation generation circuit (20) constitutes and is connected identical, the 3rd rest-set flip-flop (1030) is made up of the three or three input nand gate (1031) and the four or three input nand gate (1032) cross-couplings in Unit the 3rd (103), wherein, the 3rd input of the three or three input nand gate (1031) and the first input end of the four or three input nand gate (1032) are connected the other side's output respectively, first input end and output that the first input end of the three or three input nand gate (1031) and output are this trigger, second input of the three or three input nand gate (1031) is second input of this trigger, the 3rd input of the four or three input nand gate (1032) is the 3rd input of this trigger, and second input of the four or three input nand gate (1032) is the set end of this trigger;
Unit the tenth (100), first module (101), Unit second (102), Unit the 7th (107), the inside of the Unit the 8th (108) and the rest-set flip-flop of Unit the 9th (109) constitutes and is connected identical, the tenth rest-set flip-flop (1000) is made up of the 16 input nand gate (1001) and the 16 liang of input nand gate (1002) cross-couplings in Unit the tenth (100), wherein, the 3rd input of the 16 input nand gate (1001) and the first input end of the 16 liang of input nand gate (1002) are connected the other side's output respectively, first input end and output that the first input end of the 16 input nand gate (1001) and output are this trigger, second input of the 16 input nand gate (1001) is second input of this trigger, and second input of the 16 liang of input nand gate (1002) is the set end of the tenth rest-set flip-flop;
Comparator compare result signal Din1 inserts the first input end of the Phase Processing NAND gate of described 11 unit respectively through first phase inverter (0001), and first clock signal (CLK1) is at the clock signal " I6; I7; I8; I9; I10; I11 of out of phase, I12, I13, I14, I15, I16 " the corresponding respectively described Unit the 9th (109) that inserts; Unit the 8th (108); Unit the 7th (107); Unit the 6th (106); Unit the 5th (105); Unit the 4th (104), Unit the 11 imbalance position compensation produces circuit (20), Unit the 3rd (103), Unit second (102), first module (101), second input of the Phase Processing NAND gate of Unit the tenth (100);
First clock signal (CLK1) is at the clock signal " I6; I7; I13; I14; I15; I8 of out of phase, I9, I10, I11, I12 " respectively through the corresponding described Unit the 8th (108) that inserts of separately phase inverter; Unit the 7th (107); Unit second (102); first module (101); the set end of the rest-set flip-flop of Unit the tenth (100) and Unit the 6th (106); Unit the 5th (105), Unit the 4th (104), Unit the 11 imbalance position compensation produces circuit (20), the 3rd input of the rest-set flip-flop of Unit the 3rd (103), first clock signal (CLK1) insert the set end of the rest-set flip-flop (1030) of described Unit the 3rd (103) through its phase inverter at the signal (I5) of I5 phase place;
First clock signal (CLK1) inserts the set end of the rest-set flip-flop of second input of rest-set flip-flop of described Unit the 7th (107), Unit the 8th (108), Unit the 9th (109), Unit the tenth (100), first module (101), Unit second (102) and Unit the 6th (106), Unit the 9th (109) respectively through second phase inverter (0002) in I1 clock signals (I1);
First clock signal (CLK1) inserts second input that described Unit the 4th (104), Unit the 5th (105), Unit the 11 imbalance position compensation produce the rest-set flip-flop of the set end of rest-set flip-flop of circuit (20) and Unit the 6th (106) in I3 clock signals (I3) respectively through the 3rd phase inverter (0003);
First clock signal (CLK1) is at I1 and I4 clock signals (I1) and (I4) corresponding respectively two inputs that insert first NOR gate (0004), and the output of first NOR gate (0004) connects second input that Unit the 4th (104), Unit the 5th (105), Unit the 11 imbalance position compensation produce the rest-set flip-flop of circuit (20) respectively;
First clock signal (CLK1) is at I1 and I10 clock signals (I1) and (I10) corresponding respectively two inputs that insert second NOR gate (0005), second input of the rest-set flip-flop (1030) of output termination Unit the 3rd (103) of second NOR gate (0005)
4, the disorder bit compensation circuit that is used for gradual approaching A/D converter according to claim 1, it is characterized in that, analog to digital converter output regulation circuit (30) is formed by 11 homophase latchs, 6 adders, 11 two input NOR gate, 11 transistors and 11 trigger cascades, corresponding respectively connection comparator output generation circuit (10) of the input of 11 homophase latchs and the compensation of imbalance position produce the output of circuit (20), correspond respectively to 10 valid data signals and 1 compensation position, wherein:
The first homophase latch (302), the second homophase latch (303), the 3rd homophase latch (304), first liang of input of the corresponding respectively connection of the output of the 4th homophase latch (305) NOR gate (313), second liang of input NOR gate (314), the 3rd liang of input NOR gate (315), the first input end of the 4th liang of input NOR gate (316), the 5th homophase latch (306), corresponding two inputs that connect first adder (342) of the output of the 6th homophase latch (307), the 7th homophase latch (308), the 8th homophase latch (309), the 9th homophase latch (310), the tenth homophase latch (311), the corresponding respectively second adder (343) that connects of the output of the 11 homophase latch (312), the 3rd adder (344), the 4th adder (345), slender acanthopanax musical instruments used in a Buddhist or Taoist mass (346), second input of the 6th adder (347);
Corresponding respectively second output that connects first adder (342), second adder (343), the 3rd adder (344), the 4th adder (345), slender acanthopanax musical instruments used in a Buddhist or Taoist mass (346) of the first input end of second adder (343), the 3rd adder (344), the 4th adder (345), slender acanthopanax musical instruments used in a Buddhist or Taoist mass (346), the 6th adder (347);
The 5th liang of input of the corresponding respectively connection of first output of first adder (342), second adder (343), the 3rd adder (344), the 4th adder (345), slender acanthopanax musical instruments used in a Buddhist or Taoist mass (346), the 6th adder (347) NOR gate (317), the 6th liang of input NOR gate (318), the 7th liang of input NOR gate (319), the 8th liang of input NOR gate (320), the 9th liang of first input end of importing NOR gate (321), the tenth liang of input NOR gate (322);
The first transistor (M1), transistor seconds (M2), the 3rd transistor (M3), the corresponding respectively first homophase latch (302) that connects of the grid of the 4th transistor (M4), the second homophase latch (303), the 3rd homophase latch (304), the output of the 4th homophase latch (305), the 5th transistor (M5), the 6th transistor (M6), the 7th transistor (M7), the 8th transistor (M8), the 9th transistor (M9), the corresponding respectively first adder (342) that connects of the grid of the tenth transistor (M10), second adder (343), the 3rd adder (344), the 4th adder (345), slender acanthopanax musical instruments used in a Buddhist or Taoist mass (346), first output of the 6th adder (347), the drain electrode of the 11 transistor (M0) and described other ten transistor drain connect the first input end of the tenth liang of input NOR gate (323), the grid of the 11 transistor (M0) and described other ten transistorized source grounds, the source electrode of the 11 transistor (M0) connects power supply;
The input of second output termination the 25 phase inverter (349) of the 6th adder (347), second input of described 11 the two input NOR gate of the output termination of the 25 phase inverter (349), the corresponding respectively data input pin that connects described 11 triggers of the output of described 11 two input NOR gate, second clock signal (CLK2) inserts the input of the 25 phase inverter (324), the input end of clock of described 11 triggers of output termination of the 25 phase inverter (324), draw spill over (OVERFLOW) from the output of the 11 trigger (340), draw 10 bit data signals from the output of described other 10 triggers.
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