CN100517650C - Making method for memory capacitor - Google Patents
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- CN100517650C CN100517650C CNB200610028769XA CN200610028769A CN100517650C CN 100517650 C CN100517650 C CN 100517650C CN B200610028769X A CNB200610028769X A CN B200610028769XA CN 200610028769 A CN200610028769 A CN 200610028769A CN 100517650 C CN100517650 C CN 100517650C
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- 239000003990 capacitor Substances 0.000 title claims abstract description 78
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000003860 storage Methods 0.000 claims abstract description 43
- 238000004151 rapid thermal annealing Methods 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
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- 238000004140 cleaning Methods 0.000 claims abstract description 17
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- 230000003647 oxidation Effects 0.000 claims description 43
- 238000007254 oxidation reaction Methods 0.000 claims description 43
- 238000004519 manufacturing process Methods 0.000 claims description 36
- 238000000151 deposition Methods 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 13
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910044991 metal oxide Inorganic materials 0.000 claims description 11
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
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- 238000005516 engineering process Methods 0.000 description 2
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Abstract
A method for fabricating a storage capacitor includes that a semiconductor substrate provided with a device layer is deposited with an insulating layer and etched to form a connecting hole; a first polar plate is formed on the insulating layer; the rapid thermal annealing and oxidizing treatment is performed on the first polar plate; a dielectric layer is formed on the first polar plate; a second polar plate is formed on the dielectric layer. The method can increase the consistency when different polar voltages are sequentially exerted on the two sides of the capacitor, and prevent the damage on the capacitor polar plate caused by cleaning in the process of fabricating.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a storage capacitor.
Background
A dram is a memory device widely used in the fields of electronics, communications, and the like. A dynamic memory cell typically includes a storage capacitor and a MOS transistor. The increase in the storage density thereof requires more memory cells to be integrated per unit area and more information to be stored per unit memory cell. The integration of more memory cells per unit area requires a continuous reduction in device size, which depends on the development and progress of the photolithography process, and 193nm exposure technology has been applied to production, and 157nm and immersion exposure technologies have been developed; the amount of information stored in a unit memory cell is determined by the capacity of the storage capacitor, and the storage capacity can be increased by increasing the surface area of the capacitor plate and the dielectric constant of the medium. Chinese patent application No. 98118488 proposes a method of manufacturing a storage capacitor. Fig. 1 is a cross-sectional view of a capacitor formed by the method of increasing the storage capacity by increasing the area of the capacitor plates.
As shown in fig. 1, a Shallow Trench Isolation (STI)110 is formed on a semiconductor substrate 100, and an oxide layer 125 is formed by thermal oxidation, the oxide layer 125 serving as a gate oxide. A polysilicon layer 130 is formed over the oxide layer 125 and the layer 130 is doped to form a gate. A source 120a and a drain 120b are defined on both sides of the gate, and a bit line 145 is formed on the drain 120b and connected to the drain 120 b. A dielectric layer 140 is deposited, a connection hole 150 is formed therein and polysilicon is filled, and a crown-shaped polysilicon electrode 155 as shown in fig. 1 is formed on the dielectric layer 140, wherein the polysilicon electrode 155 is connected to the polysilicon in the connection hole 150. A Hemispherical grained polysilicon (HSG) 156 is formed on the outer surface of the polysilicon electrode 155 and doped. Polysilicon electrode 155 and hemispherical grain polysilicon layer 156 form the lower plate of the capacitor, and hemispherical grains can increase the storage capacity of the capacitor. A high dielectric constant dielectric layer 160 is formed outside the hemispherical grain polysilicon layer 156, and another plate 170 of the capacitor is formed outside the dielectric layer 160, which is made of polysilicon. Other metal materials such as titanium nitride (TiN) are also used in the prior art for the other plate.
For a capacitor with a metal-dielectric-semiconductor structure (MIS), if voltages applied to two plates are positive and negative, respectively, the storage capacity of the capacitor will be different due to the depletion effect of carriers in the semiconductor. Index exhaustion rate (Depletion Ratio) [ (C)high-Clow)/Chigh]X 100% to characterize the difference, where ChighHigh capacitance presented by a capacitor when connected twice with different polarities, ClowThe low capacitance exhibited by the capacitor when two different polarities are connected. Taking an N-type doped semiconductor plate as an example, a high capacitance is obtained when a negative bias is applied thereto, and a low capacitance is obtained when a positive bias is applied thereto. The smaller the Depletion Ratio (hereinafter referred to as D/R), the better the uniformity when voltages of different polarities are applied to both ends of the capacitor in sequence.
FIGS. 2 a-2 b are schematic cross-sectional views of a prior art MIS capacitor and its depletion layer generated during operation. Fig. 2a shows a capacitor device of MIS structure, wherein the lower plate 200 is made of semiconductor material, and is doped with phosphorus to improve the conductivity of the lower plate formed of semiconductor material, the dielectric layer 210 is made of high dielectric constant material, and the upper plate 220 is made of metal material. When the capacitor is operated, as shown in fig. 2b, the lower plate 200 is biased positively and the upper plate 220 is biased negatively, so that electrons in the semiconductor material of the lower plate 200 are attracted to the lower surface of the lower plate 200 by the applied positive bias, and a depletion layer 205 is formed on the upper surface of the lower plate 200, and almost no electrons exist in the depletion layer 205, which corresponds to increasing the thickness of the middle dielectric layer 210, i.e., changing the distance between the two plates of the capacitor. This does not occur when a negative bias is applied to the lower plate 200 and a positive bias is applied to the upper plate 220, which results in a large difference in the storage capacity exhibited by the capacitor when positive and negative positive biases are applied to the plates, respectively.
The use of HSG instead of Flat polysilicon (Flat poly) as the semiconductor plate in MIS, while improving the capacitor's capacitance, is a significant challenge for D/R. In general, the D/R of the MIS capacitor based on the plate Poly (Flat Poly) is only 6-7%. While the same dimension, the D/R of HSG based MIS capacitors under the same doping conditions is as high as 20%.
Disclosure of Invention
The invention provides a method for manufacturing a storage capacitor. The method can improve the consistency when voltages with different polarities are sequentially applied to the two ends of the capacitor and prevent the capacitor plates from being damaged in the cleaning process in the manufacturing process.
The invention provides a manufacturing method of a storage capacitor, which comprises the following steps:
depositing an insulating layer on a semiconductor substrate with a device layer and etching to form a connecting hole;
forming a first electrode plate on the insulating layer;
carrying out rapid thermal annealing oxidation treatment on the first polar plate;
forming a dielectric layer on the first polar plate;
and forming a second polar plate on the dielectric layer.
The device layer includes a metal oxide semiconductor transistor.
The first polar plate is doped polysilicon.
The first electrode plate is electrically connected with the device layer through a connecting hole.
The first polar plate is in the shape of a flat plate, a groove or a combination thereof.
The temperature of the rapid thermal annealing oxidation is 700-1000 ℃.
The time of the rapid thermal annealing oxidation is 5-60 s.
The step of forming the dielectric layer includes:
pre-cleaning the surface of the first polar plate;
performing nitridation or silicon nitride deposition on the first polar plate;
and depositing a dielectric layer on the first polar plate.
The silicon nitride deposition is chemical vapor deposition or atomic layer deposition.
The nitriding is thermally annealed in a nitrogen-containing atmosphere.
The dielectric layer is made of high-dielectric-constant materials such as aluminum oxide, silicon nitride, silicon oxide and the like.
The second polar plate is made of metal or semiconductor material.
Correspondingly, the invention also provides a manufacturing method of the storage capacitor, which comprises the following steps:
depositing an insulating layer on a semiconductor substrate with a device layer and etching to form a connecting hole;
forming a polysilicon layer on the insulating layer;
doping the polysilicon layer;
carrying out rapid thermal annealing oxidation treatment on the polycrystalline silicon layer;
forming a dielectric layer on the polycrystalline silicon layer;
and forming a conductive layer on the dielectric layer.
The temperature of the rapid thermal annealing oxidation is 700-1000 ℃.
The time of the rapid thermal annealing oxidation is 5-60 s.
And the doping temperature of the polycrystalline silicon layer is 600-800 ℃.
The time for doping the polysilicon layer is 30 minutes to 3 hours.
The method further comprises: and pre-cleaning the polysilicon layer before doping.
The method further comprises: and cleaning the surface of the polycrystalline silicon layer subjected to the rapid thermal annealing oxidation treatment.
The forming step of the conductive layer includes:
forming a titanium nitride (TiN) layer on the dielectric layer;
and forming polysilicon on the titanium nitride layer.
The present invention also provides a method for manufacturing a storage capacitor, comprising:
depositing an insulating layer on a semiconductor substrate with a device layer and etching to form a connecting hole;
forming a first polysilicon layer on the insulating layer;
doping the first polysilicon layer;
carrying out rapid thermal annealing oxidation treatment on the first polycrystalline silicon layer;
forming a dielectric layer on the first crystalline silicon layer;
forming a second polysilicon layer on the dielectric layer;
and carrying out rapid thermal annealing treatment on the second polysilicon layer.
The temperature of the rapid thermal annealing oxidation is 700-1000 ℃.
The time of the rapid thermal annealing oxidation is 5-60 s.
Compared with the prior art, the invention has the following advantages: in the invention, after the hemispherical grain polysilicon layer used as the capacitor plate is doped, a Rapid Thermal Oxidation (RTO) step is introduced. After the hemispherical grain polycrystalline silicon layer is doped, the doping ions are mostly concentrated in the surface layer of the hemispherical grain polycrystalline silicon layer, and the high temperature of the rapid thermal annealing oxidation (RTO) can enable the doping ions to diffuse into the hemispherical grain polycrystalline silicon layer under the thermal action, so that the doping ions are uniformly distributed. The Thermal Activation of the rapid Thermal annealing oxidation (RTO) also moves the dopant ions in the free state to the lattice positions of the silicon crystal, thereby increasing the effective doping concentration and conductivity of the hemispherical grain polysilicon layer.
In addition, oxygen is introduced in rapid thermal annealing oxidation (RTO), and the oxygen reacts with the polycrystalline silicon on the surface layer of the hemispherical grain polycrystalline silicon layer at high temperature to form a thin silicon oxide layer on the surface of the hemispherical grain polycrystalline silicon layer, so that the silicon oxide layer can protect the upper surface of the hemispherical grain polycrystalline silicon layer (namely the HSG-dielectric layer interface after dielectric layer deposition) from being damaged by next cleaning, and the doping concentration of the interface can not be reduced.
The depletion rate of the capacitor device formed by introducing a rapid thermal annealing oxidation (RTO) process can be reduced to 5-7%. This is because the effective doping concentration of the HSG plate is increased by the Thermal Activation, and the surface oxide layer formed by oxidation keeps the HSG-dielectric interface at a higher doping concentration after the next cleaning, so that when the N-type (phosphorus) -doped HSG plate is positively biased, the width of the depletion layer formed is greatly reduced compared with that before the application of the present invention, thereby reducing the D/R.
Meanwhile, as the conductivity of the HSG is improved by the RTO, the sheet resistance of the HSG is reduced by 20% after the RTO is introduced under the condition of the same thickness.
Drawings
FIG. 1 is a cross-sectional view of a memory cell formed by a prior art fabrication method;
FIGS. 2 a-2 b are schematic cross-sectional views of a prior art capacitor and its depletion layer generated during operation;
FIG. 3 is a flow chart of a first embodiment of the manufacturing method of the present invention;
FIGS. 4 to 11 are sectional views of the first embodiment of the manufacturing method of the present invention;
FIG. 12 is a flow chart of a second embodiment of the method of the present invention;
FIG. 13 is a flowchart of a third embodiment of the method of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings.
FIG. 3 is a flow chart of a first embodiment of the manufacturing method of the present invention.
As shown in fig. 3, a semiconductor substrate is provided on which device layers, such as metal oxide transistors (MOS), are formed. The metal oxide transistor comprises a source electrode, a drain electrode and a grid electrode, and a conductive channel is formed between the source electrode and the drain electrode. And depositing an insulating layer on the substrate on which the metal oxide transistor is formed and etching a connection hole on the insulating layer (S400).
A capacitor first plate, such as doped polysilicon, is formed on the insulating layer (S410). The first plate is electrically connected with the source electrode of the MOS transistor on the substrate through a connecting hole on the insulating layer, and the thickness and the shape of the first plate can be determined according to the storage capacity and the size of the capacitor device, for example, the shape of the first plate can be a flat plate, a groove or a combination thereof. The polysilicon layer may also be formed with hemispherical grains on its surface to increase the surface area of the capacitor plates.
A rapid thermal annealing oxidation (RTO) process is performed on the polycrystalline silicon (S420). The thermal oxidation can make the impurity ions doped into the polycrystalline silicon layer move to the inside of the polycrystalline silicon layer to form uniform distribution; and a thin oxide layer is formed on the surface of the polysilicon layer, and the oxide layer plays a role of protecting the polysilicon layer, which is helpful for reducing the Depletion rate (Depletion Ratio) of the formed capacitor device.
A dielectric layer is formed on the polysilicon layer (S430). The dielectric layer can be high-dielectric-constant materials such as aluminum oxide, silicon nitride, silicon oxide and the like.
A second plate is formed on the dielectric layer (S440). The second plate may be a metal such as titanium nitride (TiN); but may also be a semiconductor material such as polysilicon.
The following are the detailed steps of the first embodiment of the present invention. Fig. 4 to 11 are cross-sectional views illustrating a first embodiment of the present invention, in which the capacitor has a trench structure.
As shown in fig. 4, a semiconductor substrate 300 is first provided, Shallow Trench Isolation (STI)305 is formed on the substrate 300, and MOS transistors are formed on active regions. The MOS transistor includes a source 310a and a drain 310b, an oxide layer 320 is formed on the substrate, a polysilicon layer 322 is formed on the oxide layer 320 between the source 310a and the drain 310b, a metal silicide layer 324 is formed on the polysilicon layer 322, and the resistivity of the polysilicon layer 322 is reduced by doping. The polysilicon layer 322 and the metal silicide layer 324 form a gate of the MOS transistor, and spacers (spacers) 326 are formed on both sides of the gate to protect the gate and the channel thereunder. The MOS transistors on the active region may have respective sources and drains, or two MOS transistors may share a drain. In this embodiment, the drain 310b is shared.
As shown in fig. 5, an etch stop layer 306, which is made of silicon nitride, is formed on the semiconductor substrate 300 having the MOS transistor formed thereon. A first dielectric layer 330, which may be an insulating material such as TEOS, is formed on the etch stop layer 306.
As shown in fig. 6, a Photoresist (Photoresist) is spin-coated on the first dielectric layer 330, exposed and developed to form a connection hole pattern, a connection hole 332 is formed by etching, and the connection hole 332 is located above the source 310 a; the etch stop layer 306 serves as an end point detection layer for etching the connection hole 332, and protects the upper surface of the underlying source 310a and the outer surface of the sidewall 326 from being damaged during the process of forming the connection hole 332. The etching stop layer 306 and the oxide layer 320 at the bottom of the connection hole 332 are etched to expose the upper surface of the source 310a on the substrate.
As shown in fig. 7, the connection hole 332 is filled with a conductive material 334, such as polysilicon.
As shown in fig. 8, a second dielectric layer 340 is formed on the first dielectric layer 330, and a trench 342 is formed by photolithography etching, wherein the trench 342 is located above the conductive material 334 and exposes the conductive material 334.
As shown in fig. 9, a Hemispherical grained polysilicon (HSG) 344 is formed on the bottom and sidewalls of the trench 342 by chemical vapor deposition at 530 ℃ and a thickness of 300 angstroms, and polysilicon material formed on the upper surface of the second dielectric layer 340 during the deposition process is removed by Chemical Mechanical Polishing (CMP). The formed hemispherical grain polysilicon layer 344 is surface-cleaned for about 10 seconds to remove the oxide layer formed on the outer surface of the hemispherical grain polysilicon layer 344. Then, the hemispherical grain polysilicon layer 344 is doped at a temperature of 600 to 800 ℃, the doped substance is phosphorus, and the duration is about 30 minutes to 3 hours. Doping can alter the conductivity of the hemispherical grain polysilicon layer 344, thereby making it more conductive. The doped hemispherical grain polysilicon layer344 as the first plate of the storage capacitor. In this embodiment, the polysilicon layer 344 is formed in a hemispherical grain shape, so as to increase the surface area thereof, which is helpful for increasing the storage capacity of the capacitor. The hemispherical grain polysilicon layer 344 is doped to improve the conductivity, so that the capacitor plate has better conductivity and the access speed is increased. The difference between the present invention and the prior art is that after the doped hemispherical grain polysilicon layer 344 is formed, Rapid Thermal Oxidation (RTO) treatment is performed on the doped hemispherical grain polysilicon layer, oxygen is introduced during the annealing process, the annealing temperature is 700-1000 ℃, and the annealing time is 5-60 seconds. The annealing process causes dopant ions accumulated in the surface layer of the hemispherical grain polysilicon layer 344 to penetrate into the hemispherical grain polysilicon layer 344, and also forms a thin silicon oxide layer on the surface of the polysilicon layer. And then, cleaning the surface of the hemispherical grain polycrystalline silicon layer again, and then carrying out annealing treatment or silicon nitride deposition for 2 hours in a nitrogen-containing atmosphere, wherein the annealing temperature is 650 ℃. The deposition mode is chemical vapor deposition or atomic layer deposition. This step forms a silicon nitride (Si) layer outside the silicon oxide layer3N4) Silicon oxynitride (SiO)xNy) And the film layer made of the same substance can protect the formed hemispherical grain polysilicon layer 344 from being damaged by ozone generated in the atomic layer deposition process of the Al2O3, and can prevent aluminum in the dielectric layer from diffusing into the hemispherical grain polysilicon layer 344, because oxygen plasma exists when the capacitor dielectric layer is formed in the later-described step.
As shown in fig. 10, a dielectric layer 345 of alumina having a thickness of about 45 angstroms is formed on the outside of the hemispherical grain polysilicon layer 344.
As shown in fig. 11, a titanium nitride (TiN) layer 346 with a thickness of 300 angstroms is formed outside the dielectric layer 345, and the titanium nitride layer 346 is the second plate of the capacitor. A polysilicon layer 348 of thickness 1000 angstroms is formed over the silicon nitride layer 346.
In the present invention, a rapid thermal anneal oxidation (RTO) step is introduced after the hemispherical grain polysilicon layer 344 is doped. Since the doped hemispherical grain polysilicon layer 344 is doped, the doped ions are concentrated in the surface layer of the hemispherical grain polysilicon layer 344, and the high temperature of the rapid thermal annealing oxidation (RTO) can make the doped ions move to the middle and lower surfaces of the hemispherical grain polysilicon layer 344 under the thermal action, so that the doped ions are uniformly distributed. The high temperature of the rapid thermal annealing oxidation (RTO) also causes the dopant ions in the free state to move toward the lattice sites, thereby contributing to an increase in the effective doping concentration and conductivity of the hemispherical grain polysilicon layer. In addition, in the rapid thermal annealing oxidation (RTO), oxygen is introduced, and the oxygen reacts with the polysilicon on the surface layer of the hemispherical grain polysilicon layer 344 at a high temperature to form a thin silicon oxide layer on the surface of the hemispherical grain polysilicon layer 344, and the silicon oxide layer can protect the polysilicon layer on the upper surface of the hemispherical grain polysilicon layer 344 from being damaged by the next cleaning. Without the rapid thermal annealing oxidation (RTO) step, since most of the dopant ions are concentrated on the upper surface of the hemispherical grain polysilicon layer 344, the surface cleaning process in the following step is likely to damage the surface, so that the surface layer with a large amount of dopant ions is cleaned and reacted, thereby reducing the surface doping concentration.
The depletion rate (depletion rate) of the capacitor device formed by introducing a rapid thermal annealing oxidation (RTO) process can be reduced to 5-7%. The effective doping concentration of the HSG plate is improved through a rapid thermal annealing oxidation (RTO) process, and in addition, the HSG-medium interface still keeps higher doping concentration after the HSG-medium interface is cleaned in the next step through a surface oxidation layer formed through oxidation, so that when a positive bias is applied to the HSG plate doped with N-type (phosphorus), the width of a formed depletion layer is greatly reduced compared with that before the application of the invention, and the D/R is reduced. Meanwhile, as the conductivity of the HSG is improved by the RTO, the sheet resistance of the HSG is reduced by 20% after the RTO is introduced under the condition of the same thickness.
FIG. 12 is a flow chart of a second embodiment of the method of the present invention.
As illustrated in fig. 12, a semiconductor substrate is provided on which device layers, such as metal oxide transistors (MOS), are formed. The metal oxide transistor comprises a source electrode, a drain electrode and a grid electrode, and a conductive channel is formed between the source electrode and the drain electrode. And depositing an insulating layer on the substrate on which the metal oxide transistor is formed and etching a connection hole on the insulating layer (S500).
A polysilicon layer is formed on the insulating layer (S510). The polysilicon layer is electrically connected with the source electrode of the MOS transistor on the substrate through a connecting hole on the insulating layer, the shape of the polysilicon layer as the lower plate of the capacitor can be determined according to the storage capacity and the size of the capacitor device, and the shape of the polysilicon layer can be a flat plate, a groove or a combination thereof. The polysilicon layer may also be formed with hemispherical grains on its surface to increase the surface area of the capacitor plates.
And cleaning the surface of the polycrystalline silicon layer and doping the polycrystalline silicon layer (S520), wherein the doping temperature is 600-800 ℃, and the doping time is 30 minutes-3 hours. The doped impurity ion etch may be phosphorous or boron to form excess electrons or holes in the polysilicon layer to increase its conductivity.
Performing a rapid thermal annealing oxidation (RTO) process on the polycrystalline silicon (S530). The temperature of the rapid thermal annealing is 700-1000 ℃, and the time is 5-60 seconds. The thermal oxidation can make the impurity ions doped into the polycrystalline silicon layer move to the inside of the polycrystalline silicon layer to form uniform distribution; and a thin oxide layer is formed on the surface of the polycrystalline silicon layer, and the oxide layer plays a role in protecting the polycrystalline silicon layer, so that the reduction of the doping concentration on the surface of the polycrystalline silicon layer caused by the subsequent cleaning process is avoided, and the reduction of the depletion rate of the formed capacitor device is facilitated. And cleaning the surface of the polycrystalline silicon after the rapid thermal annealing oxidation treatment.
A dielectric layer is formed on the polysilicon layer and a conductive layer is formed on the dielectric layer (S500). The dielectric layer can be high-dielectric constant materials such as aluminum oxide, silicon nitride, silicon oxide and the like; the forming step of the conductive layer includes: forming a titanium nitride (TiN) layer with the thickness of 300 angstroms on the dielectric layer; polysilicon is formed to a thickness of 1000 angstroms over the titanium nitride layer.
Fig. 13 is a flowchart of a third embodiment of the present invention.
As shown in fig. 13, a semiconductor substrate is provided on which device layers, such as metal oxide transistors (MOS), are formed. The metal oxide transistor comprises a source electrode, a drain electrode and a grid electrode, and a conductive channel is formed between the source electrode and the drain electrode. And depositing an insulating layer on the substrate on which the metal oxide transistor is formed and etching a connection hole on the insulating layer (S600).
A first polysilicon layer is formed on the insulating layer (S610). The first polysilicon layer is electrically connected with the source electrode of the MOS transistor on the substrate through a connecting hole on the insulating layer, the shape of the first polysilicon layer as the lower plate of the capacitor can be determined according to the storage capacity and the size of the capacitor device, for example, the shape of the first polysilicon layer can be a flat plate, a groove or the combination of the flat plate and the groove. The first polysilicon layer may also be formed with hemispherical grains on its surface to increase the surface area of the capacitor plate.
And doping the first polysilicon layer (S620), wherein the doping temperature is 600-800 ℃, and the doping time is 30 minutes-3 hours. The doped impurity ion etch may be phosphorous or boron to form excess electrons or holes in the polysilicon layer to increase its conductivity.
A rapid thermal annealing oxidation (RTO) process is performed on the first polycrystalline silicon (S630). The temperature of the rapid thermal annealing is 700-1000 ℃, and the time is 5-60 seconds. The thermal oxidation can make the impurity ions doped into the first polycrystalline silicon layer move towards the interior of the first polycrystalline silicon layer to form uniform distribution; and a thin oxide layer is formed on the surface of the first polysilicon layer, and the oxide layer plays a role in protecting the first polysilicon layer, so that the reduction of the doping concentration on the surface of the polysilicon layer caused by the subsequent cleaning process is avoided, and the reduction of the depletion rate of the formed capacitor device is facilitated.
A dielectric layer is formed on the first polysilicon layer (S640). The dielectric layer can be high-dielectric constant materials such as aluminum oxide, silicon nitride, silicon oxide and the like;
a second polysilicon layer is formed on the dielectric layer (S650).
Performing a rapid thermal process on the second polysilicon layer (S660).
Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto, and variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the present invention.
Claims (22)
1. A method of manufacturing a storage capacitor, comprising:
depositing an insulating layer on a semiconductor substrate with a device layer and etching to form a connecting hole;
forming a first electrode plate on the insulating layer;
carrying out rapid thermal annealing oxidation treatment on the first polar plate;
forming a dielectric layer on the first polar plate;
forming a second polar plate on the dielectric layer;
wherein,
the first polar plate is doped polysilicon.
2. A method of manufacturing a storage capacitor as claimed in claim 1, characterized in that: the device layer includes a metal oxide semiconductor transistor.
3. A method of manufacturing a storage capacitor as claimed in claim 1, characterized in that: the first electrode plate is electrically connected with the device layer through a connecting hole.
4. A method of manufacturing a storage capacitor as claimed in claim 1, characterized in that: the first polar plate is in the shape of a flat plate, a groove or a combination thereof.
5. A method of manufacturing a storage capacitor as claimed in claim 1, characterized in that: the temperature of the rapid thermal annealing oxidation is 700-1000 ℃.
6. A method of manufacturing a storage capacitor as claimed in claim 1, characterized in that: the time of the rapid thermal annealing oxidation is 5-60 s.
7. A method of manufacturing a storage capacitor as claimed in claim 1, characterized in that: the step of forming the dielectric layer includes:
pre-cleaning the surface of the first polar plate;
performing nitridation or silicon nitride deposition on the first polar plate;
and depositing a dielectric layer on the first polar plate.
8. A method of manufacturing a storage capacitor as claimed in claim 7, characterized in that: the silicon nitride deposition is chemical vapor deposition or atomic layer deposition.
9. A method of manufacturing a storage capacitor as claimed in claim 7, characterized in that: the nitriding is thermally annealed in a nitrogen-containing atmosphere.
10. A method of manufacturing a storage capacitor as claimed in claim 7, characterized in that: the dielectric layer is made of high-dielectric-constant materials such as aluminum oxide, silicon nitride, silicon oxide and the like.
11. A method of manufacturing a storage capacitor as claimed in claim 1, characterized in that: the second polar plate is made of metal or semiconductor material.
12. A method of manufacturing a storage capacitor, comprising:
depositing an insulating layer on a semiconductor substrate with a device layer and etching to form a connecting hole;
forming a polysilicon layer on the insulating layer;
doping the polysilicon layer;
carrying out rapid thermal annealing oxidation treatment on the polycrystalline silicon layer;
forming a dielectric layer on the polycrystalline silicon layer;
and forming a conductive layer on the dielectric layer.
13. A method of manufacturing a storage capacitor as claimed in claim 12, characterized in that: the temperature of the rapid thermal annealing oxidation is 700-1000 ℃.
14. A method of manufacturing a storage capacitor as claimed in claim 12, characterized in that: the time of the rapid thermal annealing oxidation is 5-60 s.
15. A method of manufacturing a storage capacitor as claimed in claim 12, characterized in that: and the doping temperature of the polycrystalline silicon layer is 600-800 ℃.
16. A method of manufacturing a storage capacitor as claimed in claim 12, characterized in that: the time for doping the polysilicon layer is 30 minutes to 3 hours.
17. A method of manufacturing a storage capacitor as claimed in claim 12, characterized in that the method further comprises: and pre-cleaning the polysilicon layer before doping.
18. A method of manufacturing a storage capacitor as claimed in claim 12, characterized in that the method further comprises: and cleaning the surface of the polycrystalline silicon layer subjected to the rapid thermal annealing oxidation treatment.
19. The method of manufacturing a storage capacitor as claimed in claim 12, wherein the step of forming the conductive layer comprises:
forming a titanium nitride (TiN) layer on the dielectric layer;
and forming polysilicon on the titanium nitride layer.
20. A method of manufacturing a storage capacitor, comprising:
depositing an insulating layer on a semiconductor substrate with a device layer and etching to form a connecting hole;
forming a first polysilicon layer on the insulating layer;
doping the first polysilicon layer;
carrying out rapid thermal annealing oxidation treatment on the first polycrystalline silicon layer;
forming a dielectric layer on the first crystalline silicon layer;
forming a second polysilicon layer on the dielectric layer;
and carrying out rapid thermal annealing treatment on the second polysilicon layer.
21. A method of manufacturing a storage capacitor as claimed in claim 20, characterized in that: the temperature of the rapid thermal annealing oxidation is 700-1000 ℃.
22. A method of manufacturing a storage capacitor as claimed in claim 20, characterized in that: the time of the rapid thermal annealing oxidation is 5-60 s.
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| CNB200610028769XA CN100517650C (en) | 2006-07-10 | 2006-07-10 | Making method for memory capacitor |
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| CNB200610028769XA CN100517650C (en) | 2006-07-10 | 2006-07-10 | Making method for memory capacitor |
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| CN107893203B (en) * | 2017-11-30 | 2019-06-14 | 宁波博恩电气有限公司 | Capacitor aluminium sheet homogenizing annealing method |
| CN107916381B (en) * | 2017-11-30 | 2019-06-14 | 宁波博恩电气有限公司 | Aluminium foil used in capacitor annealing device |
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