CN100463179C - Active component and switch circuit device - Google Patents
Active component and switch circuit device Download PDFInfo
- Publication number
- CN100463179C CN100463179C CNB2006100714524A CN200610071452A CN100463179C CN 100463179 C CN100463179 C CN 100463179C CN B2006100714524 A CNB2006100714524 A CN B2006100714524A CN 200610071452 A CN200610071452 A CN 200610071452A CN 100463179 C CN100463179 C CN 100463179C
- Authority
- CN
- China
- Prior art keywords
- layer
- unit
- emitter
- transistor
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Bipolar Transistors (AREA)
- Electronic Switches (AREA)
Abstract
A unit HBT and a unit FET are arranged to be adjacent to each other through an isolation region and a base electrode of the unit HBT is connected to a source electrode of the unit FET to form a unit element, and a plurality of unit elements are connected to form an active element. This makes it possible to implement the active element in which a current is not likely to concentrate on the unit element and no destruction is generated by the second breakdown. Moreover, although a buried gate electrode structure is used to ensure a withstand pressure in the unit FET, a buried portion is structured not to be diffused to an InGaP layer, and thereby it is possible to prevent Pt from being abnormally diffused. Furthermore, a selection etching can be used for a formation of an emitter mesa, that of a base mesa, that of a ledge in the unit HBT, and a gate recess etching in the unit FET, and a good reproducibility can be obtained.
Description
Technical field
The present invention relates to a kind of active element and switch circuit devices, particularly relate to a kind of active element and switch circuit devices of temperature compensating type with heterogenous junction type bipolar transistor.
Background technology
Heterogenous junction type bipolar transistor (Heterojunction Bipolar Transistor: hereinafter referred to as HBT) is compared emission effciency height and current amplification degree h with common homogeneity junction bipolar transistor
FEGreatly, thus base stage concentration can be improved significantly, and can carry out transistor work equably in whole base stage.Consequently, metal-semiconductor field effect transistor), GaAs JFET (Junction FET: junction field effect transistor), HEMT (High Electron Mobility Transistor: High Electron Mobility Transistor) compare with GaAs MESFET (Metal Semicondutor Field Effect Transistor:, so its current density is high and be communicated with that resistance is low to have a good efficiency, gain property, distorted characteristic.
With in the communication equipment, efficient and small-sized HF switch element is indispensable at moving bodys such as mobile phones.Therefore, the known structure that two-way HBT is constituted switching circuit as switch element that has as shown in figure 26.
Figure 26 is that expression is with the example of HBT as the switching circuit of switch element use.Figure 26 (A) is that circuit diagram, Figure 26 (B) are for representing the profile of HBT structure.
As Figure 26 (A), this circuit has the 2nd HBT321 that a HBT320 that emitter is connected with antenna ANT and collector electrode are connected with antenna ANT, the collector electrode of a HBT320 with send signal and be connected with lateral circuit Tx.In addition, the emitter of the 2nd HBT321 is connected with received signal lateral circuit Rx, HBT320, and each base stage of 321 is connected with control terminal CtrlRx with received signal with control terminal CtrlTx with the transmission signal respectively via resistance 322.
Shown in Figure 26 (B), on semiconductive GaAs substrate 310, form the secondary collector layer 311 of n type GaAs, one-tenth mesa shape such as stacked n type AlGaAs collector layer 312, p type GaAs base layer 313, n type AlGaAs emitter layer 314, n type GaAs emitter contact layer 315 on secondary collector layer 311 and constituting.
Clip config set electrode 316 on the position of collector layer 312 on the surface of secondary collector layer 311.Clip configuration base stage 317 on the position of emission layer 314 on the surface of collector electrode 313.At the top of emitter contact layer 315 configuration emitter 318.Least unit HBT shown in the figure as unit element 320 ' (321 '), by being connected in parallel, they is constituted the HBT320 (the 2nd HBT321) (as referring to Patent Document 1) as active element
Patent documentation 1: the spy opens the 2000-260782 communique
The emitter 318 of HBT, base stage 317, collector electrode 316 form the broach shape.Structure shown in Figure 26 (B) as a unit element, is connected in parallel a plurality of unit elements and constitutes the active element of switch element etc.
Because electric current has positive temperature coefficient between the base-emitter of HBT, so collector current also has positive temperature coefficient.Therefore, improve current density if manage to make base current to increase, then in the unit element of a plurality of HBT that are connected in parallel, electric current is concentrated and second breakdown takes place and is damaged easily to a unit element.
At present, for fear of such problem that can not fully current density be improved that exists in the problem aspect the reliability.
In addition, take following measure usually in order to address this problem.That is, emission steady resistance and base stage steady resistance are inserted the broach shape unit element 320 of HBT320 '.But, if insertion emission steady resistance and base stage steady resistance have then produced the problem of high frequency characteristics branch deterioration again.
Summary of the invention
The present invention constitutes for addressing the above problem, a first aspect of the present invention provides a kind of active element, have: compound semiconductor substrate, its stacked a plurality of semiconductor layers form, and form heterojunction between at least one group of (band gap is different) semiconductor layer in a plurality of semiconductor layers; The first transistor, it is arranged on the described substrate, first, second, third semiconductor layer of described semiconductor layer is formed collector layer, base layer, emitter layer respectively, and have collector electrode, base stage, emitter; Transistor seconds, it is arranged on the described substrate, and has grid, source electrode, drain electrode; Unit element, its unit element for described the first transistor and transistor seconds are formed in abutting connection with configuration via separated region, and the described base stage of described the first transistor and the described source electrode of described transistor seconds be connected.A plurality of described unit elements are connected in parallel, and the drain electrode of the described transistor seconds of described constituent parts element is connected with power supply terminal, the voltage signal of the described grid by being input to described transistor seconds changes the electric current between the collector electrode-emitter of described the first transistor of described constituent parts element.
A second aspect of the present invention is to provide a kind of circuit arrangement, and it has: compound semiconductor substrate, and its stacked a plurality of semiconductor layers form, and form heterojunction between at least one group of (band gap is different) semiconductor layer in a plurality of semiconductor layers; The first transistor, it is arranged on the described substrate, first, second, third semiconductor layer of described semiconductor layer is formed collector layer, base layer, emitter layer respectively, and have collector electrode, base stage, emitter; Transistor seconds, it is arranged on the described substrate, and has grid, source electrode, drain electrode; Unit element, its unit element for described the first transistor and transistor seconds are formed in abutting connection with configuration via separated region, and the described base stage of described the first transistor and the described source electrode of described transistor seconds be connected; A plurality of switch elements that described unit element is connected in parallel; The one RF port, it is with the collector electrode of described a plurality of switch elements or emitter is shared is connected; A plurality of the 2nd RF ports, it is connected respectively with the emitter or the collector electrode of described a plurality of switch elements; Power supply terminal, it is connected with the drain electrode of described a plurality of switch elements respectively.Grid to described transistor seconds applies control signal respectively, by the described the first transistor of being supplied with by the conducting of described transistor seconds of current drives, and forms signal path between the described first and second RF ports.
Description of drawings
Fig. 1 (A), (B) are the circuit diagrams of the explanation first embodiment of the present invention;
Fig. 2 is the plane graph of the explanation first embodiment of the present invention;
Fig. 3 is (A) profile, (B) profile, (C) stereogram, (D) stereogram of the explanation first embodiment of the present invention;
Fig. 4 (A)～(C) is the profile of the explanation first embodiment of the present invention;
Fig. 5 is (A) circuit diagram, (B) circuit block diagram of the explanation first embodiment of the present invention;
Fig. 6 (A), (B) are the profiles of explanation second embodiment of the invention;
Fig. 7 (A), (B) are the profiles of explanation second embodiment of the invention;
Fig. 8 is (A) circuit synoptic diagram, (B) circuit diagram of explanation third embodiment of the invention;
Fig. 9 is the plane graph of explanation third embodiment of the invention;
Figure 10 is (A) profile, (B) profile, (C) stereogram, (D) stereogram of the explanation third embodiment of the present invention;
Figure 11 (A), (B) are the performance plots of explanation third embodiment of the invention;
Figure 12 (A)～(C) is the profile of explanation third embodiment of the invention;
Figure 13 (A), (B) are the profiles of explanation fourth embodiment of the invention;
Figure 14 (A), (B) are the profiles of explanation fourth embodiment of the invention;
Figure 15 (A), (B) are the circuit skeleton diagrams of explanation fifth embodiment of the invention;
Figure 16 is (A) plane graph, (B) profile of the explanation fifth embodiment of the present invention;
Figure 17 is the profile of the explanation fifth embodiment of the present invention;
Figure 18 is the circuit skeleton diagram of explanation sixth embodiment of the invention;
Figure 19 is the circuit skeleton diagram of explanation seventh embodiment of the invention;
Figure 20 is (A) profile, (B) profile, (C) stereogram, (D) stereogram of the explanation first embodiment of the present invention;
Figure 21 (A), (B) are the profiles of the explanation eighth embodiment of the present invention;
Figure 22 (A), (B) are the profiles of the explanation eighth embodiment of the present invention;
Figure 23 (A)～(C) is the profile of the explanation ninth embodiment of the present invention;
Figure 24 is (A) profile, (B) stereogram, (C) stereogram of the explanation tenth embodiment of the present invention;
Figure 25 (A), (B) are the profiles of the explanation ninth embodiment of the present invention;
Figure 26 is (A) circuit diagram, (B) profile of explanation prior art.
Description of reference numerals
1 GaAS substrate
2 secondary collector layers
3 first semiconductor layers (collector layer)
4 second semiconductor layers (p+ type GaAs layer)
The 4a base layer
5 the 3rd semiconductor layers (n type InGaP layer)
The 5a emitter layer
6 n+ type GaAs layers
6a emitter contact layer
7,13 collector electrodes
8 base stages
9,15 emitters
4b p+ type resilient coating
5b raceway groove lower layer
5b ' channel layer
6bs, 6bd, 6bse, 6bde, 6bsd, 6bdd collector layer
10,16 drain electrodes
11 source electrodes
12 grids
The 12b buried portion
17 connect distribution
18,18a the 4th semiconductor layer (n type AlGaAs layer or n type GaAs layer)
18b raceway groove upper layer
19,19a the 5th semiconductor layer (n type InGaP layer)
20 separated regions
23 conductive area
30 resolution elements
31 non-alloy ohm layers
33,33a, 33b steady resistance layer
41 inverter circuits (イ Application バ- loop)
51 nitride films
100 unit elements
101 HBT of unit
102 FET of unit
115,135,115e, 115d, 135e, 135d source electrode
116,136,116e, 116d, 136e, 136d drain electrode
120 gate wirings
127 first grids
The 127b buried portion
128 second grids
130 collector electrode distributions
150 emitter distributions
160 drain electrode distributions
170 peripheral conductive area
200 active elements
The 200a grouped component
210 power amplification circuit devices
R1, R2 resistance
R11, R12, R13 resistance
R21, R22, R23 resistance
R31, R32, R33 resistance
411 resistance
412 E type FET
413 D type FET
414 E type FET
The L bead
The EM emitter mesa
BM base stage table top
The CP tie point
SW, SW1, SW2 switch element
SW1-1, SW1-2, SW1-3 switch element
SW2-1, SW2-2, SW2-3 switch element
SW3-1, SW3-2, SW3-3 switch element
S, S1, S2 group of switching elements
IN shared input
OUT1 first input end
OUT2 second input terminal
OUT3 the 3rd input terminal
The Ct1 control terminal
Ct11 first control terminal
Ct12 second control terminal
Ct13 the 3rd control terminal
BP bias point (バ ィ ア ス Port イ Application ト)
Embodiment
Below, utilize Fig. 1～Figure 25 to describe embodiments of the invention in detail.
At first, with reference to Fig. 1～Fig. 5, the active element of the expression first embodiment of the present invention.Fig. 1 (A) is the circuit diagram of active element, and Fig. 1 (B) is the circuit diagram of the unit element of formation active element.
As Fig. 1 (A), active element 200 is the structure of a plurality of unit elements 100 (dotted line) that are connected in parallel.Unit element 100 has the first transistor 101 and transistor seconds 102.
The first transistor 101 forms at least one heterojunction for stacked semiconductor layer as collector layer, base layer, emitter layer on compound semiconductor substrate, and has the HBT of the collector electrode that is connected with each semiconductor layer respectively, base stage, emitter.HBT has mesa structure, in the present embodiment, by the first transistor that mesa structure constituted of least unit hereinafter referred to as the HBT101 of unit.
One group of HBT101 of unit and the FET102 of unit are via separated region disposed adjacent described later, and it is a unit element 100 (dotted line) that the source electrode of the base stage of the HBT101 of unit and the FET102 of unit connects and composes.
A plurality of unit elements 100 is connected in parallel and constitutes active element 200.Specifically, a unit element 100 is with the drain electrode of emitter, collector electrode and the FET102 of unit of the HBT101 of unit, emitter, collector electrode, drain electrode, the grid of the shared connection other unit element 100 of grid difference.
The drain electrode of the FET102 of unit of constituent parts element 100 is connected with power supply terminal VDD.And, change by the electric current between the collector electrode-emitter of the HBT101 of the voltage signal unit of making on the grid of the FET102 of the unit of being applied to.
With reference to Fig. 1 (B), the HBT101 of unit of unit element 100 and the FET102 of unit be disposed adjacent (aftermentioned) via separated region, and the base stage of the HBT101 of unit is connected with the source electrode of the FET102 of unit.Unit element 100 is connected in parallel, on the base stage of a unit element 100 and source electrode and the not shared base stage and source electrode that is connected to other unit element 100.
Fig. 2 is the plane graph of expression active element 200.
Like this, the HBT101 of unit in plane graph for example pattern form the broach shape.And the FET102 of unit is connected with constituent parts HBT101.That is, the unit element 100 of present embodiment forms the broach shape, and each broach is connected in parallel respectively constitutes active element 200.
Stacked a plurality of semiconductor layers on compound semiconductor substrate form HBT101 of unit and the FET102 of unit.
The HBT101 of unit carries out mesa etch with desirable pattern with each semiconductor layer as described later, and each semiconductor layer that constitutes emitter layer, base layer is formed mesa shaped.
By ohmic metal layer (AuGe/Ni/Au), emitter 9, the collector electrode 7 of the ground floor that setting and emitter layer, secondary collector layer are connected respectively form the base stage 8 that is connected with base layer by ohmic metal layer (Pt/Ti/Pt/Au).Emitter 9 and collector electrode 7 are set to the broach shape.With emitter 9 is that the center disposes base stage 8 around it shown in hacures.And, the collector electrode 7 of two clamping base stages 8 of configuration on the secondary collector layer in the outside of base stage 8.
On the emitter 9 of ground floor, collector electrode 7 by emitter 15, the collector electrode 13 of the second layer being set with their overlapping distribution metal levels (Ti/Pt/Au).The emitter 15 of the second layer is the broach shape identical with ground floor.The collector electrode 13 of the second layer is connected with collector electrode distribution 130.Base stage 8 is for only forming one deck structure by ohmic metal layer.In addition, on the emitter 15 of the second layer, emitter distribution 150 is set by Gold plated Layer.
The FET102 of unit is arranged on same substrate and the semiconductor layer with the HBT101 of unit as described later.With desirable pattern semiconductor layer is carried out mesa etch, each semiconductor layer that constitutes contact layer, channel layer is formed mesa shaped.
By ohmic metal layer (AuGe/Ni/Au), drain electrode 10, the source electrode 11 of the ground floor that contacts respectively with each contact layer is set.On the channel layer surface between drain electrode 10 and the source electrode 11, (Pt/Mo) is provided with grid 12 by gate metal layer.Grid 12 extends on the direction vertical with the bearing of trend of each electrode of the HBT101 of unit of broach shape and is provided with between the source electrode 11 of island, drain electrode 10.
The working region of the FET102 of unit of configuration drain electrode 10, source electrode 11, grid 12 is formed on by on the conductive area 23 of separated region 20 with the semiconductor layer separation.Separated region 20 is that the ion by B+ etc. injects the insulating regions that forms, so separated region 20 zone in addition promptly becomes conductive area 23 by double dot dash line institute area surrounded in the present embodiment.Conductive area 23 is for example for comprising the zone of n type impurity.
The drain electrode 16 of the second layer is set by distribution metal level (Ti/Pt/Au) on the drain electrode 10 of ground floor.In addition, on the drain electrode 16 of the second layer, form drain electrode distribution 160 by Gold plated Layer.
The connection distribution 17 of distribution metal level is set on the source electrode 11 of ground floor.Connection distribution 17 is connected the source electrode 11 of the FET102 of unit with the base stage 8 of the HBT101 of unit.
FET102 of unit and the HBT101 of unit are arranged on same substrate and with on the semi-conductor layer, and the semiconductor layer of a part forms mesa shaped and by apart.Injecting the separated region 20 that forms in the zone that is not carried out mesa etch by ion separates.That is, HBT101 of unit and the FET102 of unit be disposed adjacent via being arranged on separated region 20 on same substrate and the semiconductor layer, and the base stage 8 of the HBT101 of unit and the source electrode of the FET102 of unit 11 connect by connecting distribution 17.In addition, in the present embodiment, the base layer of the HBT101 of unit and collector layer form continuously with the semiconductor layer that is equivalent to the FET102 of unit respectively.
In the present embodiment, shown in dotted line, the HBT101 of unit of the mesa structure of the least unit that constitutes by emitter 9,15, base stage 8, collector electrode 7,13 be connected by one group of source electrode 11, grid 12, drain electrode 10,16 FET102 of unit that constitute, constitute a unit element 100.
At this, the base stage 8 of the HBT101 of unit connects by being connected distribution 17 in a unit element 100 with the source electrode 11 of the FET102 of unit.A plurality of unit elements 100 are being configured in the line map of broach shape, are not directly connecting between the base stage 8 of the HBT101 of unit and between the source electrode 11 of the FET102 of unit.
The drain electrode 16 of the FET102 of unit is by drain electrode distribution 160 distributions of Gold plated Layer, and distribution 160 and power supply terminal V drain
DDConnect.And the gate wirings 120 of the FET102 of unit is connected with the terminal of input voltage signal.
Fig. 3 is the figure of instruction book bit unit 100, and Fig. 3 (A) is the profile of the HBT101 of unit of the a-a line profile of Fig. 2, b-b line that Fig. 3 (B) is Fig. 2.In addition, to be the section shown in the c-c line of Fig. 3 (A) cut off into the stereogram of described two HBT101 of unit when regional with described unit element to Fig. 3 (C).Fig. 3 (D) is the stereogram of FET102.In addition, in Fig. 3 (B), (C), (D), omit connection electrode 17.In Fig. 3 (C), (D), omit second and in addition with the electrode on upper strata.
In addition, in all embodiment of the application, the circuit diagram of unit element 100 and active element 200 (Fig. 1 (A)) is identical with plane graph (Fig. 2).But as shown in Figure 3, each semiconductor layer of component unit element 100 (active element 200) is suitably selected according to the purposes of active element 200.Therefore, first embodiment (Fig. 3) expression is configured for the unit element 100 of the active element 200 of amplifier (amplifier), and this example is described.
As Fig. 3 (A), on the GaAs of half insulation substrate 1, stacked a plurality of semiconductor layer, i.e. n+ type GaAs layer 2, n-type GaAs layer 3, p+ type GaAs layer 4, n type InGaP layer 5, n type AlGaAs layer 18, n type InGaP layer 19 and n+ type GaAs layer 6.In addition, n type AlGaAs layer 18 also can be n type GaAs layer, in the present embodiment n type AlGaAs layer 18 is described.
Part by semiconductor layer is removed in etching forms mesa shaped.In addition, the separated region 20 that arrives substrate 1 is set.Separated region is that the ion by B+ etc. injects the insulating regions 20 that forms.
As Fig. 3 (B), (C), the secondary collector layer 2 of the HBT101 of unit forms on substrate 1 by epitaxial growth method, is that doped silicon (Si) becomes 3E18cm
-3～6E18cm
-3The n+ type GaAs layer of higher impurity concentration.Its thickness is thousands of
Collector electrode 3 is formed on a part of zone of secondary collector layer 2, and is to be doping to 1E16cm by silicon doping
-3About～10E16cm
-3About the n-type GaAs layer of impurity concentration.Its thickness is thousands of
Base layer 4a is formed on the collector layer 3, is to be doping to 1E18cm by carbon (C)
-3～50E18cm
-3About the p+ type GaAs layer of impurity concentration.Its thickness is hundreds of
Emitter layer 5a forms mesa shaped (emitter mesa EM) on a part of zone of base layer 4a, be to be doping to 1E17cm by silicon doping
-3About～5E17cm
-3About the n type InGaP layer of impurity concentration.Its thickness is that hundreds of～thousand are hundreds of
Doped silicon is to become 1E17cm on emitter layer 5a
-3About～5E17cm
-3About impurity concentration, stacked have hundreds of～thousand the number
The n type AlGaAs layer 18a of thickness.The AlGaAs layer and the GaAs layer of emitter layer 5a and the upper and lower carry out lattice match.In addition, doped silicon becomes 1E17cm on n type AlGaAs layer 18a
-3About～60E17cm
-3About impurity concentration, stacked have hundreds of～thousand the number
The n type InGaP layer 19a of thickness.
At this, the part of the emitter layer 5a of the n type InGaP layer 5 formation HBT101 of unit and the channel layer of the FET102 of unit, and near the side of emitter 5a, form bead L.The back is described in detail, is that hundreds of～thousand are hundreds of by the thickness attenuation that makes n type InGaP layer 5
And exhaust fully by surface depletion layer in bead L part, can prevent to flow through recombination current between the emitter-base stage on base layer 4a surface.N type AlGaAs layer 18 is with the part of the channel layer of n type InGaP layer 5 FET102 of the unit of formation.That is, form the grid of the FET102 of unit on the surface of n type AlGaAs layer 18, the thickness of the pinch-off voltage Vp that the thickness setting of n type AlGaAs layer 18 can obtain stipulating for the FET102 of unit.N type InGaP layer 19 is for the grid that forms the FET102 of unit makes in the operation that n type AlGaAs layer 18 surface expose, the etch stopper of etching n+ type GaAs layer 6.
There are two kinds of following situations in the impurity concentration of n type InGaP layer 19.First kind of situation is that doped silicon is to become 1E17cm
-3About～5E17cm
-3About impurity concentration, between emitter-base stage, apply reverse bias, then depletion layer enlarges to emitter layer 5a and n type AlGaAs layer 18 from the heterojunction between emitter-base stage.Fully guarantee the extended distance of this depletion layer between emitter-base stage in conjunction with the withstand voltage needs that will obtain stipulating.But the gross thickness of emitter layer 5a and n type AlGaAs layer 18 is not enough as the distance that this depletion layer is extended.
In this case, n type AlGaAs layer 19 also becomes a part that is used to obtain the regulation zone withstand voltage, that depletion layer extends between collector-base.That is, under first kind of situation, making the impurity concentration of n type AlGaAs layer 19 is 1E17cm
-3About～5E17cm
-3About, by collector layer 5a, n type AlGaAs layer 18, and n type InGaP layer enlarge depletion layer for 19 3 layers and guarantee that the regulation between collector-base is withstand voltage.
Second kind of situation be on n type InGaP layer 19 doped silicon to become 20E17cm
-3About～60E17cm
-3About impurity concentration.As mentioned above, when between emitter-base stage, applying reverse bias, enlarge, thereby guarantee regulation withstand voltage between emitter-base stage at emitter layer 5a and n type AlGaAs layer 18 depletion layer.Only the gross thickness with emitter layer 5a and n type AlGaAs layer 18 is just enough as the distance that depletion layer expansion is extended under second kind of situation.At this moment, be 20E17cm by the impurity concentration that makes n type AlGaAs layer 19
-3About～60E17cm
-3About high concentration, reduce the emitter dead resistance component of the HBT101 of unit and source electrode (drain electrode) the dead resistance component of the FET102 of unit.
On the other hand, under first kind of situation, be 20E17cm if make the impurity concentration of n type InGaP layer 19
-3～60E17cm
-3About high concentration, when then applying reverse bias between emitter-base stage, depletion layer arrives n type InGaP layer 19 with the withstand voltage following reverse bias voltage of the regulation between emitter-base stage.So even apply than its high reversed migration voltage, depletion layer also extends in n type InGaP layer 19 hardly, so the withstand voltage following reverse bias voltage with regulation disconnects between emitter-base stage.
In addition, under second kind of situation, the impurity concentration of n type InGaP layer 19 is 20E17cm
-3About～60E17cm
-3About high concentration (n+), at this moment, first kind of situation and second kind of situation general name note are made n type InGaP layer 19.
N type AlGaAs layer 18 and n type InGaP layer 19 are by mesa etch, and apart becomes n type AlGaAs layer 18a, 18b and n type InGaP layer 19a, 19b respectively.
The position configuration of clamping collector layer 3 is by the collector electrode 7 of the ground floor of ohmic metal layer (AuGe/Ni/Au) formation on the surface of secondary collector layer 2.The base stage 8 that is constituted with the pattern arrangement ohmic metal layer (Pt/Ti/Pt/Au) that surrounds emitter layer 5a on the surface of base layer 4a.Dispose the emitter 9 of the ground floor that is constituted by ohmic metal layer (AuGe/Ni/Au) on the top of emitter contact layer 6a.Cover by nitride film 51 on the collector electrode 7 of ground floor, emitter 9 and the base stage 8.The collector electrode 7 of ground floor, emitter 9 be via the contact hole that is arranged on the nitride film 51, contacts with emitter 15 with collector electrode 13 by the set second layer of distribution metal level (Ti/Pt/Au) respectively.
At this, as Fig. 3 (A), (B), emitter layer 5a becomes to side-prominent bead (canopy) L of the base stage 8 that is positioned at both sides.Any semiconductor layer is not set above L, and surface depletion layer extends from bead L surface.In addition, the thickness of bead L is the thickness of emitter layer 5a, is set to be less than or equal to the thickness that surface depletion layer extends than unfertile land.Therefore, bead L is by surface depletion layer exhausting fully.Thus, the surface current that can prevent the base layer 4a below bead L is crossed the recombination current between emitter-base stage.
Other the explanation of embodiment for example described later exists the structure as HBT directly to contact and stacked situation with n+ type GaAs layer 6 by thick emitter layer 5a than the thickness of bead L.At this moment, need also that exhausting, photoetch by emitter 5a form bead L fully as mentioned above with bead L.
But this method is difficult to carry out the control of wet etching, and existence can not reproducibility forms the problem of the bead L of specific thickness well.That is, if the thickness of bead L is blocked up, then the surface depletion layer that extends to bead L from bead L surface does not arrive base layer 4a.At this moment, because bead L surface exhausting fully not, cross recombination current between emitter-base stage, reduce the current amplification degree of HBT at the surface current of base layer 4a.In addition, the etching of n type InGaP layer 5 that is used to form bead L is excessive, and itself has also disappeared bead L.In addition, improve the precision of wet etching, need to reduce rate of etch, produce the elongated problem of etching period.
Therefore, in the present embodiment, the FET102 of unit adds n type AlGaAs layer 18a on emitter layer (n type InGaP layer) 5a, with the thickness of the channel layer of the pinch-off voltage Vp that obtains accessing regulation.Promptly as described later, the thickness of the channel layer of the FET102 of unit is the gross thickness of n type InGaP layer 5 and n type AlGaAs layer 18.The AlGaAs layer is selected than big with the wet etching of InGaP layer.Therefore, emitter layer 5a is arranged on the bead L with only specific thickness, forms bead L by selective etch n type AlGaAs layer 18a and n type InGaP layer 5a.Thus, bead L well and in short time can be formed with the thickness reproducibility of regulation.
In addition as mentioned above, when applying reverse bias between emitter-base stage, exist among the n type InGaP layer 19a also depletion layer is enlarged design, the EB junction of the HBT101 of the unit of making closes can guarantee the withstand voltage situation stipulated.As the distance that the depletion layer that makes emitter side extends, under the not enough situation of the gross thickness of emitter layer 5a and n type AlGaAs layer 18a, making the impurity concentration of the n type InGaP layer 19a that is formed on the n type AlGaAs layer 18a is 1E17cm
-3About～5E17cm
-3About.Thus, depletion layer also may extend into n type AlGaAs layer 19a.
Fig. 3 (D) is the stereogram of the unit FET102 of the section shown in the c-c line of Fig. 3 (A) when unit element is separated.The n type InGaP layer 5 of the FET102 of unit and n type AlGaAs layer 18 work as channel layer.Therefore, with n type InGaP layer 5 as raceway groove lower layer 5b, with n type AlGaAs layer 18 as raceway groove upper layer 18b.In addition, with the n+ type GaAs layer 6 of the superiors as contact layer 6bs, 6bd.Contact layer 6bd, 6bs become drain region and the source region of FET respectively, form drain electrode 10, the source electrode 11 of ground floor on contact layer 6bd, 6bs respectively by ohmic metal layer.
The n type InGaP layer 19b of contact layer 6bd, 6bs and its lower floor also forms mesa shaped, and the n type AlGaAs layer 18b of the lower floor of n type InGaP layer 19b exposes between them.On the n type AlGaAs layer 18b that exposes, grid 12 is set.
The FET102 of unit decision from the bottom of grid 12 to the degree of depth of the bottom of raceway groove bottom (n type InGaP) the layer 5b of a part that constitutes channel layer, to obtain the pinch-off voltage Vp of raceway groove.That is, determine to form the position (degree of depth) of grid 12 in view of the above.Therefore, to the degree of depth of desirable semiconductor layer recess etch, on the surface of exposing, form grid 12 according to pinch-off voltage Vp to regulation.At this moment, in recess etch, there is deviation, then causes the deviation of pinch-off voltage Vp, the characteristic degradation of the FET102 of unit.
Therefore in the present embodiment, stacked channels bottom (n type InGaP) layer 5a, raceway groove top (n type AlGaAs) layer 18b, n type InGaP layer 19b and n+ type GaAs layer 6.And in the recess etch operation that forms grid, at first by the selective etch of n+ type GaAs layer 6 and n type InGaP layer 19b, etching n+ type GaAs layer 6 separates 6bd, the 6bs of contact layer.Then, by the selective etch of n type InGaP layer 19b and n type AlGaAs layer 18b, etching n type InGaP layer 19b exposes the surface of the n type AlGaAs layer 18b that forms grid.By the corresponding thickness of pinch-off voltage Vp that n type AlGaAs layer 18b is set at and stipulates, can form the recess etch of the good grid of reproducibility 12.
Like this, in the FET102 of unit, n type AlGaAs layer 18b and n type InGaP layer 19b are set, in addition, also help guaranteeing the withstand voltage of grid in exposing the depression in the surface etching that forms grid 12, can carry out selective etch.
In the present embodiment, the grid 12 of the FET102 of unit is arranged on the n type AlGaAs layer 18b.And the part of orlop metal that employing will constitute the gate metal layer (metallized multilayer film) of grid 12 is imbedded the buried gate structure of n type AlGaAs layer 18b.
The amplification profile of representing the buried gate structure at this Fig. 4.Adopt under the situation of buried gate structure, grid 12 is by adopt a plurality of metallized multilayer films (for example Pt/Mo) of metal Pt to constitute at orlop.And after on the semiconductor layer, the orlop metal is that the part of Pt is diffused into semiconductor layer with the metallized multilayer film evaporation, forms buried portion 12b.Because buried portion 12b is a diffusion zone, formed forniciform shape so ought to form laterally with the curvature of stipulating from semiconductor layer surface, help to improve withstand voltage raising.
Fig. 4 (A) and Fig. 4 (B) are the situations that expression Pt is diffused into the InGaP layer.For example in Fig. 4 (A), stacked non-doping InGaP layer 402 on non-doped with Al GaAs layer 401, and form grid 12 on the surface of InGaP layer 402.Thus, the layer that exposes of the both sides of grid 12 becomes InGaP layer 402.It is stable on chemical property that InGaP layer 402 is difficult to oxidation, and has the advantage that the passivation layer of the working region of the both sides that can be used as grid 12 uses.Buried portion 12b ' works as the part of grid 12, therefore determines the position (diffusion depth) of the bottom of buried portion 12b ' according to pinch-off voltage Vp.
But, the Pt of actual observation grid 12 be diffused into InGaP layer 402 surface and, shown in Fig. 4 (A), can distinguish that Pt becomes the shape of point to horizontal unusual diffusion and end (X point) on InGaP layer 402 surface.That is, the shape that is used to improve withstand voltage buried portion 12b ' does not in fact become with the crooked laterally shape of the curvature of regulation, can not obtain improving withstand voltage favourable shape.
In addition, in Fig. 4 (B), represent non-doped with Al GaAs layer 401,403 and non-doping InGaP layer 402 is alternately laminated, form the structure of grid 12 on the surface of AlGaAs layer 403.Thus,, arrive InGaP layer 402, then unusual diffusion laterally takes place on its surface if connect the Pt of AlGaAs layer 403 diffusion even do not form under the situation of grid 12 on InGaP layer 402 surface.
In addition, semiconductor layer is all represented with non-doped layer in Fig. 4 (A), (B), but the InGaP layer (or AlGaAs layer) of the abnormality of Pt diffusion when comprising the layer (doping InGaP layer, doped with Al GaAs layer) of impurity too.
Like this, because in the unusual diffusion of the surperficial Pt of InGaP layer 402, so under any circumstance, take place at X point all that electric field is concentrated can not guarantee original high withstand voltage of buried gate.That is, the withstand voltage and situation of buried gate not of this moment rests on the same level.
Fig. 4 (C) is the grid 12 and the buried portion 12b of present embodiment.Like this, in the present embodiment, raceway groove upper layer (n type AlGaAs) layer 18b is arranged on raceway groove lower layer (n type InGaP) the layer 5b, forms grid 12 on its surface.And, make the bottom of buried portion 12b be positioned at n type AlGaAs layer 18b.Thus, can prevent the abnormality diffusion of Pt on the surface of n type InGaP layer 5b, the shape of buried portion 12b becomes with the curvature of the regulation shape towards outside curve, can seek withstand voltage raising.
In addition, as the pinch-off voltage Vp of its target by from the bottom (bottom of buried portion 12b) of grid 12 to the distance of raceway groove lower layer 5b bottom, and the impurity concentration of raceway groove lower layer 5b and raceway groove upper layer 18b determines.At this, if the evaporation thickness of the undermost Pt of gate metal layer is less than or equal to
The then degree of depth of buried portion 12b and evaporation thickness (degree of depth of buried portion 12b=Pt evaporation thickness * 2.4) in direct ratio.That is, the degree of depth of buried portion 12b can be controlled well according to Pt evaporation thickness reproducibility.In addition, because impurity concentration is the impurity concentration when forming epitaxial loayer by the MOCVD device, so can carry out very accurate control.
On the other hand, the channel layer from the bottom of buried portion 12b to raceway groove lower layer 5b surface is made of raceway groove top (n type AlGaAs layer) 18b.In the present embodiment, at first the impurity concentration of raceway groove bottom (n type InGaP) layer 5b and raceway groove top (n type AlGaAs) layer 18b is set the withstand voltage and connection resistance that the FET102 of the unit of making obtains stipulating.Then, the bead L of the HBT101 of unit is set at the thickness of proper function, so that the thickness of raceway groove bottom (n type InGaP) layer 5b is identical with the thickness of the bead L of the HBT101 of unit.At last, the thickness setting of raceway groove top (n type AlGaAs) layer 18b is obtained the thickness of regulation pinch-off voltage Vp for the FET102 of unit.The upper strata stacked n type InGaP layer 19b of (n type AlGaAs) layer 18b on raceway groove top.And,, n type AlGaAs layer 18b exposed by the selective etch of n type InGaP layer 19b and n type AlGaAs layer 18b.Preparing enough thick n type AlGaAs layer 18b, etching into the degree of depth of regulation by wet etching, making in the existing method that the surface of formation grid exposes, etched reproducibility is poor, and pinch-off voltage Vp is deviation significantly.But, the surface of the n type AlGaAs layer 18b that forms grid is exposed according to the present embodiment reproducibility.
The lower floor of (n type AlGaAs layer) 18b configuration raceway groove lower layer 5b on raceway groove top is at the configuration p+ of lower floor of raceway groove lower layer 5b type resilient coating 4b.P+ type resilient coating 4b is a p+ type GaAs layer, can prevent the current-carrying that leaks to substrate side from raceway groove by this layer.
In addition be the layer that does not especially influence as work because the lower floor of p+ type GaAs layer 4 below is FET, therefore, design optimum the getting final product of characteristic of the HBT101 of unit.
Referring again to Fig. 3.As Fig. 3 (A) unit element 100 is the structure that makes face S1 ' with the face S1 butt of the FET102 of unit shown in Fig. 3 (D) of the HBT101 of unit shown in Fig. 3 (B), (C).Bearing surface is the face of the c-c line of Fig. 3 (A).And, connection distribution 17 is set on the source electrode distribution 11 of the FET102 of unit by distribution metal level (Ti/Pt/Au).Connect the table top of distribution 17, again on the base stage 8 by the HBT101 of the unit of extending on the insulating regions 20 along the FET102 of unit.
At this, mesa shape and distribution direction are described.
Use under the situation of wet etching in the mesa etch of GaAs, crystal face influences mesa shape.As the relation of crystal orientation and mesa shape, with (01 thick stick (バ-), 1 thick stick) (below's, note do (01-1-)) direction parallel direction on mesa shape under the situation on trace etch step surface be positive mesa shape (trapezoidal shape).In addition, the mesa shape on trace etch step surface is contrary mesa shape (catenary configuration) on the direction vertical with the direction of (01-1-).
That is, for example the distribution metal level promote to reduce under the situation of table top step, produces the problem that classification covers (step coverage) in the difference because of the bearing of trend of mesa shape or distribution metal level.
Metal level with the direction parallel direction of (01-1-) on extend and promote under the situation that reduces the table top step owing to be positive mesa shape, do not produce the problem of classification covering.But distribution is extending on the direction vertical with (01-1-) direction under the situation that promotes reduction table top step, owing to be contrary mesa shape, produces the problem that classification covers.
In the present embodiment, the mesa etch of emitter contact layer 6a, n type InGaP19a, n type AlGaAs layer 18a and emitter 5a by forming the HBT101 of unit also forms table top in the zone of the FET of unit 102 simultaneously.That is, in Fig. 2, emitter mesa EM is the table top that forms simultaneously.
In addition, by the base layer 4a of the formation HBT of unit 101 and the mesa etch of collector layer 3, also form table top in the zone of the FET of unit 102 simultaneously.That is, in Fig. 2, base stage table top BM is the table top that forms simultaneously.
Therefore, the connection distribution 17 that the source electrode 11 of the FET of unit 102 is connected with the base stage 8 of the HBT of unit 101 promotes and reduces emitter mesa EM, and then gate wirings 120 promotes and reduces base stage table top BM.
At this, in the present embodiment, connection distribution 17, gate wirings 120 have the direction that promotes the reduction table top, and make it to go up extension in the direction parallel with (01-1-) direction (direction of arrow of figure).
Like this, n+ type GaAs layer 6, n type InGaP layer 19, n type AlGaAs layer 18 and n type InGaP layer 5 are mesa shaped, by apart.On the other hand, the lower floor from 4 beginning of p+ type GaAs layer is separated by separated region (insulating regions) 20.That is, the base layer 4a of the HBT of unit 101, collector layer 3, secondary collector layer 2 separate, but structurally are continuous with resilient coating 4b, n-type GaAs layer 3, n+ type GaAs layer 2 electricity of the FET of unit 102.HBT of unit 101 and the FET102 of unit are via separated region 20 disposed adjacent.
In the present embodiment, by each unit element 100, FET of unit 102 and 101 adjacent connections of the HBT of unit.And, the HBT of unit 101 is identical with the stepped construction of the semiconductor layer of the FET of unit 102, and the base layer 4a of the HBT of unit 101, collector layer 3, secondary collector layer 2 are continuous with p+ type GaAs layer 4b, n-type GaAs layer 3, the n+ type GaAs layer 2 of the FET102 of unit respectively.Therefore, can be with the FET of the heat unit of passing to 102 that work produced by the HBT of unit 101.Because the drain current of the FET102 of unit has negative temperature coefficient, so the base current of the HBT of unit 101 also has negative temperature coefficient.Therefore, the collector current of the HBT of the heating unit of making 101 of the HBT of unit 101 reduces.
When constituting active element 200 being connected in parallel a plurality of unit elements 100, there is the operating current of 100 of the unit elements uneven situation that becomes.Existing HBT 320 (or 321) with the HBT of least unit shown in Figure 26 as unit element 320 ' with its a plurality of formation active elements that are connected in parallel.In this case, compare with HEMT usually and can obtain very high current density potentially, and obtain low-down connection resistance R on.But HBT 320 exists the positive feedback effect of passing through temperature with the problem of current concentration to a unit element by second breakdown destruction.Therefore, in fact can not improve current density fully.In addition, in order to address this problem, must take following measure usually.That is, emitter ballast resistance and base stage steady resistance are inserted the unit element 320 of the broach shape of HBT 320 ' in.But, then produced the problem that high frequency characteristics worsens again if insert emitter ballast resistance and base stage steady resistance.
The emitter-to-base voltage V of HBT 320
BEWhen the characteristic of-base current has positive coefficient with respect to temperature, owing to the uneven reason in any design, exist unit element 320 ' with respect to other unit element 320 ', emitter-to-base voltage V
BEThe situation that-bias voltage is applied slightly bigly.Consequently, base current, collector current flow in a large number, and temperature rises, and a large amount of base currents, collector current are flowed be common second breakdown process.
But in fact the unit element 100 of present embodiment does not begin the process of second breakdown.Provide unit element 100 the HBT of unit 101 base current be the FET of unit 102, but the FET of unit 102 is different with the HBT of unit 101, has negative temperature coefficient with respect to temperature.In addition, so because the heat of the HBT of unit 101 of HBT101 of unit and the FET of unit 102 approaching heatings passes to the FET102 of unit of adjacency, the source current of the FET of unit 102 reduces.Because source electrode is connected with base stage, so the source current of the FET102 of unit becomes the base current of the HBT of unit 101.That is, reduce the source current of the FET of unit 102, and reduce the base current of the HBT of unit 101 by the heating of the HBT of unit 101.Thus, reduce the collector current of the HBT of unit 101, the opposite HBT of unit 101 becomes the cooling direction.That is, its result can prevent the generation of second breakdown.
That is, in the present embodiment,, compare with existing active element and can significantly improve current density and work by connecting the active element 200 that obtains temperature compensating type with the FET of unit 102 of the HBT of unit 101 adjacency.That is, owing to do not increase all high frequency characteristics degradation factors that make emitter ballast resistance and base stage steady resistance etc. and the generation that can prevent second breakdown, can improve current density significantly so compare with existing active element.
Fig. 5 is the power amplification circuit device 210 that the active element 200 of the described amplifier purposes of Fig. 3 is used in expression.Fig. 5 (A) is a circuit diagram, and Fig. 5 (B) is a circuit block diagram.
The main application of HBT in the market is the power amplifier (high output amplifier) of mobile phone.In the power amplifier of mobile phone, especially after the third generation, how to guarantee in limited wave scale that the mass communication circuit becomes the key of technical maximum.Adopted the high density communication mode of CDMA etc.Be accompanied by the densification of communication mode, seek to have the power amplifier equipment of higher linearity.Also use HEMT in the power amplifier of mobile phone, the usage rate of comparing the high and linear high HBT of current density after the third generation with HEMT has increased.Because HEMT is a unipolarity equipment, and HBT is a bipolar device, so can improve current density with overwhelming.
According to present embodiment, can not provide emitter ballast resistance and base stage steady resistance are inserted in the constituent parts element of the active element 200 that constitutes amplifier element, and avoid the power amplification circuit device 210 of second breakdown.
As Fig. 5 (A), constitute power amplification circuit device 210 by the active element 200 that unit element 100 is connected in parallel.Power amplification circuit device 210 for will as the active element 200 of amplifier element and bias voltage with and the integrated structure of passive component used etc. of coupling.
In the amplifier element 200 that constitutes power amplification circuit device 210, input signal enters from the grid of the FET102 of unit of formation constituent parts element 100, and output signal is from the collector electrode output of the HBT of unit 101.The drain electrode of the FET102 of unit is via the resolution element (sensing element) 30 and power supply terminal V that prevent that high-frequency signal from leaking
DDConnect.Power supply terminal V
DDTo the FET102 of unit supplying electric current.In addition, emitter is connected with GND.The unit element 100 of present embodiment constitutes for connect the FET102 of unit on the HBT101 of unit.That is, be connected with the FET102 of unit as amplifier element in previous stage as the HBT101 of unit of amplifier element.
Promptly as Fig. 5 (B), if the amplifier element 200 by the unit element 100 of the present embodiment that is connected in parallel constitutes power amplifier circuit 210, then work as the two-stage amplifier element, this two-stage amplifier element is by connect the HBT102 of unit as partial amplifier element on the back one-level as the FET of the amplifier element of the first order.
That is, owing to current amplification degree h to HBT
FEAdd the mutual inductance gm of FET, so the amplification performance of an amplifier element 200 becomes mutual inductance gm and current amplification degree h
FEAccumulated value.That is, the gm of an amplifier element 200 becomes the gm of FET and the h of HBT
FEAccumulated value.Only the amplification performance of the amplifier element that constitutes with HBT with only with current amplification degree h
FECompare during formation, can improve gain significantly as amplifier element.
Fig. 6, Fig. 7 be as second embodiment, and expression constitutes other the example of unit element 100 of the active element 200 of amplifier purposes.Under the situation of the active element 200 that is used for amplifier, the structure of the epitaxial loayer of constituent parts element 100 is generally the structure shown in Fig. 3 (B), (C), but also can be the structure of Figure 6 and Figure 7.Second embodiment is the structure of adding other semiconductor layer on the unit element 100 identical with first embodiment.
Fig. 6 is for being provided with the situation of steady resistance layer on the unit element 100 identical with first embodiment.Fig. 6 (A) is the profile of unit element 100 of the a-a line that is equivalent to Fig. 2, and Fig. 6 (B) is the profile of the HBT of unit 101 of the b-b line that is equivalent to Fig. 2.
As mentioned above, according to present embodiment, the generation that the steady resistance layer also can prevent second breakdown is not set.But, also there is the situation that can not prevent fully that second breakdown from taking place according to the design of the FET of unit 102 and the HBT of unit 101 of component unit element 100.In addition, flow in the HBT101 of the unit situation of a large amount of electric currents also is difficult to avoid the generation of second breakdown.Under these circumstances, can be by in the epitaxial structure of the HBT of unit 101, adding steady resistance layer repeated using second breakdown measure.
That is, at the n-type GaAs layer 33 of emitter layer 5a side configuration as the steady resistance layer.Become the steady resistance layer owing to have the n-type GaAs layer 33 of regulation resistance value, so can prevent to concentrate to a unit element 100 generation of the second breakdown that causes owing to electric current.
Because present embodiment constitutes active elements 200 with temperature compensating type unit element 100, thus be provided with under the situation of steady resistance, also can be to obtain identical effect with steady resistance that existing HBT 320 compares low-resistance value.Therefore, can be with owing to degree that high frequency characteristics that steady resistance causes worsens being set than reducing at present.
At this moment, shown in Fig. 6 (A), also dispose n-type GaAs layer 33 on the FET102 of unit, but the electric current of the FET102 of the unit of inflow seldom, n-type GaAs layer 33 is set can not brings influence.
Fig. 7 is in the unit HBT 101 identical with first embodiment, and non-alloy ohm layer 31 is set, the situation that emitter is contacted with non-alloy ohm layer 31.Fig. 7 (A) is the situation that non-alloy ohm layer 31 is set in the HBT of unit 101 of Fig. 3, and Fig. 7 (B) further is provided with the situation of non-alloy ohm layer 31 in the structure of the steady resistance layer that Fig. 7 is set.In addition, Fig. 7 is the profile of the HBT of unit 101 that is equivalent to the b-b line of Fig. 2.For reducing the contact resistance of emitter contact layer 6a, non-alloy ohm layer 31 is set on collector electrode contact layer 6a.Non-alloy ohm layer 31 is a n+ type InGaAs layer.At this moment, emitter contact layer 6a is a n+ type InGaAs layer, and other semiconductor layer is also identical with Fig. 3 (B).At this moment, though not shown, also in the FET of unit 102, non-alloy ohm layer 31 is arranged on contact layer 6bs, the 6bd simultaneously.
Below, with reference to Fig. 8～Figure 12 the third embodiment of the present invention is described.The 3rd embodiment constitutes the situation of switch circuit devices 220 for the active element of being used by switch element 200.
At first, the circuit diagram of representing the switch circuit devices of the 3rd embodiment with reference to Fig. 8.Fig. 8 (A) is the circuit synoptic diagram, and Fig. 8 (B) is actual circuit diagram.
Switch circuit devices for example is SPDT (Single Pole Double Throw: switch MMIC single-pole double throw).
SPDT switch MMIC has the first switch element SW1 and second switch element SW2.The first switch element SW1 is the active element 200 of unit element of being connected in parallel, and second switch element SW2 also is the active element of the unit element that is connected in parallel.
Unit element is identical with first embodiment, is made of HBT of unit and the FET of unit.At this, it among Fig. 8 (A) the general structure of expression switch circuit devices 220, represent with HBT 1, HBT 2 HBT of unit of each active element that constitutes the first switch element SW1 and second switch element SW2 is blanket, the FET of unit of each active element is summed up represent with FET 1, FET 2.
Metal-semiconductor field effect transistor), and for the driving transistors of base current is provided to HBT 1, HBT2 respectively in addition, FET 1, FET 2 are MESFET (Metal Semiconductor Field EffectTransistor:.
The HBT 1 of first and second switch element SW1, SW2 and the collector electrode of HBT 2 are shared to be connected on the RF port.The one RF port for example is the sub-IN of shared input that is connected with antenna etc.
In addition, the emitter of the HBT 1 of first and second switch element SW1, SW2 and HBT 2 is connected with the 2nd RF port respectively.The 2nd RF port for example is and sends the first lead-out terminal OUT 1 that signal is connected with lateral circuit etc. and the second lead-out terminal OUT 2 that is connected with received signal circuit etc.
The base stage of HBT 1 and HBT 2 respectively via FET 1 and FET2 with for example be connected with control terminal and received signal the first control terminal Ct11 and the second control terminal Ct12 with control terminal as sending signal.
The drain electrode of FET 1 and FET2 respectively with power supply terminal V
DDConnect, source electrode is connected with the base stage of HBT 1 and HBT 2 respectively.Grid is connected with the first control terminal Ct11 and the second control terminal Ct12 via controlling resistance R1 and R2 respectively.Configuration controlling resistance R1 and its purpose of R2 are to prevent that high-frequency signal from leaking the DC potential that constitutes the control terminal Ct11, the Ct12 that exchange ground connection via grid.The resistance value of controlling resistance R1 and R2 is about 5K Ω～10K Ω about.
Illustrate that the control signal that is applied on the first control terminal Ct11 and the second control terminal Ct12 is the situation of complementary signal.In this case, when the signal of the first control terminal Ct11 was H level (for example 3V), the signal of the second control terminal Ct12 became L level (for example 0V).And, apply the FET conducting of H level side, by the current drives HBT1 that provides by FET or any among the HBT2.And, between a RF port and the 2nd RF port, form a signal path.
For example, if on the first control terminal Ct11, apply the H level, then conducting between source electrode-drain electrode of FET1.Thus, will be by power supply terminal V
DDThe base current I that provides
BAs base bias, HBT 1 work.At this moment, owing to apply the L level to the second control terminal Ct12, so not conducting of FET2, HBT2 does not work.Thus, between the sub-IN-first lead-out terminal OUT1 of shared input, form a signal path, for example export from the first lead-out terminal OUT1 from the high frequency analog signals that will be input to the sub-IN of shared input.On the other hand, if apply the H level, then between the sub-IN-second lead-out terminal OUT2 of shared input, form a signal path to the second control terminal Ct12.
Bias point BP is connected with emitter and the collector electrode of HBT 1 and HBT 2 respectively.Bias point (bias point) BP applies equal bias (for example GND current potential) to emitter and the collector electrode of HBT 1 and HBT 2.
Between the emitter and bias point BP of HBT 1 and HBT 2, and be connected the resolution element 30 of high-frequency signal between the collector electrode of HBT 1 and HBT 2 and the bias point BP respectively.Resolution element 30 for example is the resistance of resistance value 5K Ω～10K Ω, can prevent to leak with respect to bias (GND current potential) high-frequency signal.
Further, based on same reason, applying the power supply terminal V of drain bias
DDAnd between the FET1, and power supply terminal V
DDWith the resolution element 30 that also is connected high-frequency signal between the FET2.
Below, this circuit working is described.
Connection voltage (the emitter-to-base voltage V of HBT 1, HBT 2
BE) for example be 2.0V.And FET1, FET2 are depletion type (テ リ プ レ ッ シ ョ Application), and pinch-off voltage Vp is 0.4V.
That is, connect side control terminal (for example first control terminal Ct11) current potential than the current potential of the emitter of HBT1 and collector electrode exceed more than or equal to 1.6V (=2.0V-0.4V) time, FET1 and HBT1 just connect.
At this, the emitter of HBT 1, HBT 2 and the current potential of collector electrode are GND current potential (0V).Owing to apply 3V to the first control terminal Ct11 that connects side, thus the potential difference of the current potential of the emitter of the first control terminal Ct11 and HBT1 and collector electrode be 3V (=3V-0V).This value is more abundant than the current potential (1.6V) that FET1 and HBT1 connect.That is, even the pressure drop of the resolution element 30 (resistance) that consideration is connected with bias point BP also can fully be connected FET1 and HBT1 by the current potential that applies from the first control terminal Ct11, the emitter of HBT1-inter-collector conducting.
On the other hand, connect side with respect to the emitter of HBT2 and the current potential 0V (GND) of collector electrode, the second control terminal Ct12 is 0V.Because when the current potential of the second control terminal Ct12 exceeded more than or equal to 1.6V than the current potential of the emitter of HBT2 and collector electrode, FET2 and HBT2 connected, the disconnection side can be born the power of 1.6V amplitude.
1.6V amplitude corresponding with the power of 20.1dBm, can be in WLAN and Bluetooth fully use.
Like this, for example when the current potential with the emitter of HBT1 and collector electrode was the aggregate value of the current potential of the first control terminal Ct11 of the benchmark pinch-off voltage that surpasses the connection voltage of HBT1 and FET1, the first switch element SW1 began to connect (the second control terminal Ct12 side is also identical).In a second embodiment, making the emitter of HBT1, HBT2 and the current potential of collector electrode is GND.Not shown, by being set, bias circuit that resistance cuts apart etc. can freely set emitter and the collector potential of HBT1, HBT2.Therefore, the aggregate value of the connection voltage of HBT1, HBT2 and the pinch-off voltage of FET1, FET2 is not limited to described example when being any value, all can obtain the characteristic identical with second embodiment by adjusting bias circuit.That is, FET1 and FET2 can be in enhancement mode or the depletion type any.
Fig. 8 (B) is the HBT1 shown in the presentation graphs (A) and being connected and the circuit diagram that is connected of HBT2 and the reality of FET2 of the reality of FET1.The pattern that constitutes the reality of the HBT1 of first and second switch element SW1, SW2 and HBT2 is that collector electrode, base stage, emitter comb are configured to dentation, and FET1, FET2 also are configured to dentation with source electrode, drain electrode, grid comb.And the base stage of HBT1 is connected with the source electrode of FET1, and being connected of the source electrode of the base stage of HBT2 and FET2, and is in fact all corresponding with each broach.
Among Fig. 8 (B), with HBT1 and FET1, HBT2 and FET2 are unit element 100 expressions by each broach.Like this, the switch circuit devices 220 of the 3rd embodiment connects the first transistor (HBT of unit) 101 and transistor seconds (FET of unit) 102 as unit element 100, is made of the first switch element SW1 and the second switch element SW2 of a plurality of unit elements 100 that are connected in parallel.The FET102 of unit is for providing the driving transistors of base current to the HBT101 of unit.
The circuit diagram of unit element 100, the HBT101 of unit and the FET102 of unit, identical with first embodiment, the detailed description of its repeating part of Therefore, omited.
One group HBT101 of unit and the FET102 of unit are via the separated region disposed adjacent, and the source electrode of the base stage of the HBT101 of unit and the FET102 of unit connects and composes a unit element 100 (dotted line).
The unit element 100 that is connected in parallel constitutes the first switch element SW1 and second switch element SW2.Unit element 100 is connected in parallel, but on the base stage and source electrode of the not shared respectively unit element 100 that is connected to other of the base stage of a unit element 100 and source electrode.
Specifically, unit element 100 with the emitter of the HBT101 of unit, collector electrode, and the shared respectively emitter that is connected to other the HBT101 of unit of drain electrode, the grid of the FET102 of unit, collector electrode, and the drain electrode of the FET102 of unit, grid on.
The drain electrode of the FET102 of unit of constituent parts element 100 and power supply terminal V
DDConnect.And, to the collector emitter voltage V of the HBT101 of unit
CEBias voltage is 0V, applies complementary signal to first and second control terminal Ct11, Ct12.Thus, the base current that applies regulation to any HBT101 of unit of the first switch element SW1 or second switch element SW2 makes conducting between collector electrode-emitter.Perhaps, making base current is 0 to interdict between collector electrode-emitter.Thus, form signal path in any between the sub-IN-first lead-out terminal OUT1 of shared input or between the sub-IN-second lead-out terminal OUT2 of shared input.
Its form represented in Fig. 8 (A) summary.HBT1 is made of the HBT101 of unit of the first switch element SW1, and FET1 is made of the FET102 of unit of the first switch element SW1.Equally, the HBT2 shown in Fig. 8 (A) is made of the HBT101 of unit of second switch element SW2, and FET2 is made of the FET102 of unit of second switch element SW2.
The work of above switch circuit devices as the 3rd embodiment, the control signal that expression applies to the first control terminal Ct11 and the second control terminal Ct12 are the situation of any conducting of the first switch element SW1 of complementary signal and second switch element SW2.
But having the control signal that applies to the first control terminal Ct11 and the second control terminal Ct12 all is the situation of L level, and when the both was the L level, SW1 and SW2 interdicted.
Fig. 9 represents the example with Fig. 8 (B) circuit pattern of integrated switch MMIC on compound semiconductor substrate.
On the substrate that is configured in stacked a plurality of semiconductor layer on the Semi-insulating GaAs substrate, carry out first and second switch element SW1, the SW2 of switch.Constitute the sub-IN of shared input, the first lead-out terminal OUT1, the second lead-out terminal OUT2, the first control terminal Ct11, the second control terminal Ct12, power supply terminal V
DD, each pad I, O1 of earth terminal GND, O2, C1, C2, V, G be arranged on the periphery of substrate.
The first switch element SW1 side and second switch element SW2 and each pad are with respect to the center balanced configuration of chip.Therefore, below the first switch element SW1 side is described, second switch element SW2 is also identical.
The first switch element SW1 is connected in parallel a plurality of unit elements 100 and constitutes, and constituent parts element 100 is made of HBT101 of unit and the FET102 of unit.HBT101 of unit and the FET102 of unit form the mesa shaped of regulation with a plurality of semiconductor layer etchings on the Semi-insulating GaAs substrate, in addition, form the element of the switch MMIC that constitutes resistance etc. by the conductive area that is made of semiconductor layer.In addition, as described later, the conductive area of present embodiment is an extrinsic region, is separated from other zone by the separated region 20 that arrives substrate.
The emitter 9 of the ground floor of the HBT101 of unit, base stage 8, collector electrode 7 form the broach shape by ohmic metal layer.The emitter 15 of the second layer and collector electrode 13 form by the distribution metal level, and emitter 15 forms the broach shape equally with the emitter 9 of ground floor.The collector electrode 13 of the second layer is connected with the collector electrode 13 of the HBT101 of other unit by collector electrode distribution 130, is connected on the sub-pad I of shared input.On the emitter 15 of the second layer, form the emitter distribution 150 of Gold plated Layer, be connected, be connected on the first lead-out terminal pad O1 with other the emitter 15 of HBT101.Also overlapping Gold plated Layer on collector electrode distribution 130.
Because the HBT101 of unit introduces base current, so emitter 9,15 and collector electrode 7,13 are connected with the GND pad G that constitutes bias point BP.Emitter 15 is by the emitter distribution 150 and first shared connection of lead-out terminal pad O1.Therefore, by connecting lead-out terminal pad O1 and GND pad G, collector electrode 9,15 can be connected with bias point BP.In addition, collector electrode 13 is by the 130 shared connections of collector electrode distribution.Therefore, connect collector electrode distribution 130 and GND pad G, collector electrode 7,13 is connected with bias point BP by resistance via resolution element 30.Bias point BP (GND pad G) is configured between the first lead-out terminal pad O1 and the second lead-out terminal pad O2, the opposition side of the sub-pad I of shared input as shown in Figure 9.By this configuration, do not need to guarantee new space especially and can supply with bias to the emitter of the HBT101 of unit and collector electrode.
The drain electrode 10 of the ground floor of the FET102 of unit, source electrode 11 form island by ohmic metal layer.The drain electrode 16 of the second layer forms island by the distribution metal level.On the drain electrode 16 of the second layer, form the drain electrode wiring layer 160 of Gold plated Layer, be connected, be connected on the power supply terminal pad V with other the drain electrode of the FET102 of unit.
HBT101 of unit and the HBT102 of unit are via separated region 20 disposed adjacent, and the base stage 8 of the HBT101 of unit, the source electrode of the FET102 of unit 11 connect by the connection distribution 17 that the distribution metal level forms, and constitute a unit element 100.
On source electrode 11 and the conductive area (extrinsic region) 23 between 10 of draining, the grid 12 that is made of gate metal layer is set.Grid 12 is connected with the grid of other the FET102 of unit by the gate wirings 120 that is made of the distribution metal level, is connected with the first control terminal pad C1 via controlling resistance R1.
Between the first lead-out terminal pad O1 and earth terminal pad G, connect and compose the resistance of resolution element 30.In addition, between power supply terminal pad V-connection distribution 160, reach the resistance that also connects and composes resolution element 30 between the sub-pad I-of the shared input earth terminal pad G.Resolution element prevents spilling of high-frequency signal.
The resistance of controlling resistance R1 and resolution element 30 is the conductive area 23 of being separated by separated region 20.
In addition, for improving insulation, peripheral conductive area (extrinsic region 170) is set respectively at the periphery of each pad and the periphery of gate wirings 120.
The amplification view of unit element 100 is identical with Fig. 2.With reference to Fig. 2, the FET102 of unit is connected with the HBT101 of unit of broach shape pattern respectively, the first switch element SW1 and second switch element SW2 that the unit element 100 of the broach shape that is connected in parallel constitutes as active element 200.
The first switch element SW1 is the structure of unit element 100 of being connected in parallel.That is, the collector electrode 13,7 by collector electrode distribution 130 constituent parts HBT101 is connected to each other, and in addition, the emitter 15,9 by emitter distribution 150 constituent parts HBT101 is connected to each other.In addition, collector electrode 7,13 is shared by adjacent unit element 100.The grid 12 of constituent parts FET102 by the gate wirings 120 of the FET102 of unit be connected to each other, the gate wirings 120 of the FET102 of unit is connected with the first control terminal Ct11.The drain electrode 10,16 of constituent parts FET102 is connected to each other by drain electrode distribution 160, is connected to power supply terminal V
DD
In addition, each grid 12 of the FET102 of unit extends outside the working region, is connected with the gate wirings 120 of distribution metal level.Gate wirings 120 is connected with control terminal carrying out distribution between the grid 12.Around gate wirings, also dispose separated region 20.In addition, second switch element SW2 is also identical.
Other structure is identical with the unit element 100 of Fig. 2, its explanation of Therefore, omited.
Figure 10 is the figure of the unit element 100 of explanation the 3rd embodiment, and Figure 10 (A) is the profile of the a-a line of Fig. 2.Figure 10 (B) is the profile of the b-b line of Fig. 2, and Figure 10 (C) is the stereogram of the HBT101 of unit, and Figure 10 (D) is the stereogram of the FET102 of unit.In addition, in Figure 10 (C), omission second or its electrode with the upper strata.
As mentioned above, each semiconductor layer of component unit element 100 (active element 200) is suitably selected according to the purposes of active element 200.Under the situation of the active element 200 that is used for switch circuit devices, the collector layer 3 of the HBT101 of unit becomes n type InGaP layer.Other structure is identical with the unit element 100 of embodiment 1, its explanation of Therefore, omited.
In the 3rd embodiment, the InGaP layer-selective etching of n type AlGaAs layer (or n type GaAs layer) 18 and emitter layer 5a can form the bead L with the good thickness of reproducibility.The InGaP layer of emitter layer 5a can carry out selective etch with the p+ type GaAs layer of base layer 4a.
In addition, by n type InGaP19 is set, can selective etch will the FET102 of the unit of formation the surface of grid n type AlGaAs layer 18 expose.In addition, the grid 12 of FET102 is formed on the n type AlGaAs layer 18b, and buried portion 12b is positioned at n type AlGaAs layer 18b.Thus, the abnormality of the Pt that can prevent diffusion at the InGaP laminar surface, that guarantees to stipulate is withstand voltage.
In addition, in the present embodiment, the FET102 of unit of each unit element 100 is connected with the HBT101 of unit is approaching.And the HBT101 of unit is identical with the stepped construction of the semiconductor layer of the FET102 of unit, the base layer 4a of the HBT101 of unit, collector layer 3, secondary collector layer 2 respectively with the FET102 of unit suitable semiconductor layer continuous.Therefore, can the FET102 of the unit of passing to by the heat that work produced of the HBT101 of unit.Because the drain current of the FET102 of unit has negative temperature coefficient, so the base current of the HBT101 of unit also has negative temperature coefficient.Therefore, the collector current that the heating of the HBT101 of unit can the HBT101 of the unit of making reduces.
By taking such structure, owing to can not increasing the generation that the factor that makes all high frequency characteristics deteriorations such as emitter ballast resistance and base stage steady resistance prevents second breakdown, so with compare the current density that can improve HBT significantly at present.Consequently, the connection resistance R on of first and second switch element SW1, SW2 is reduced significantly, thereby make the insertion loss of switch MMIC become very little.
As Figure 10, under the situation of the unit element 100 that is used for switch circuit devices 220, the HBT101 of unit forms the InGaP/GaAs heterojunction at emitter layer 5a and base layer 4a.In addition, on this basis, on collector layer 3 and base stage 4a, also form the InGaP/GaAs heterojunction.And, with emitter 5a during as the work of the transistor of the positive direction of emitter work when being called the work of forward transistor (below) with emitter 5a during when being called transistor work (below) as the reciprocal transistor work of collector electrode work, it is roughly the same characteristic that each parameter of project organization makes transistor characteristic, making collector electrode-emission voltage across poles is 0V, and collector electrode-emission electrode current is with near the bias voltage work the 0A.In the present embodiment, as above be that benchmark adopts emitter and the polar-symmetric HBT of current collection (hereinafter referred to as symmetric form HBT) with the base stage.
Because being used in the HEMT of switch MMIC usually is mono-polar devices, and HBT is a bipolar devices,, make connection resistance R on become very little so can improve current density significantly.In addition, can be as HBT101 by using symmetric form HBT, to make between collector electrode-emitter current sinking be 0A so can save energy ground and work.Its reason is, it is 0V that HMET makes drain electrode-voltage between source electrodes bias voltage, identical therewith, and symmetric form HBT can make that voltage bias is 0V between collector electrode-emitter.
Performance plot explanation symmetric form HBT with reference to Figure 11.The base current I of the regulation of figure expression symmetric form HBT
BIn collector emitter voltage V
CEWith collector current I
CThe V-I curve.
Base current I in certain regulation
BIn will represent collector emitter voltage V
CEWith collector current I
CFor the transistor of (+) value just is called the forward transistor, the transistor of negative (-) value of expression is called reverse transistor.
As Figure 11 (A), symmetric form HBT is for making forward transistor connection resistance R the on (=Δ V in when work shown in thick line
CE/ Δ I
C) connection resistance R on ' (=Δ V during with reverse transistor work
CE'/Δ I
C') equate and the HBT of formation basically.For realizing this structure, make emitter layer 5a be identical substantially structure with collector layer 3.For example, when on emitter layer 5a, using the InGaP layer, on collector layer 3, also use the InGaP layer.And, when on emitter layer 5a and collector layer 3, using the InGaP layer, respectively with GaAs layer or AlGaAs layer (base layer 4a, secondary collector layer 2 and n type AlGaAs layer 18a) lattice match.When using the AlGaAs layer on emitter layer 5a and the collector layer 3, make the molar ratio of Al identical.
And, the impurity concentration of the impurity concentration of emitter layer 5a and collector layer 3 is set at about equally value.Thus, to compare base stage-collector electrode withstand voltage low with common HBT, in switch circuit devices base stage-inter-collector withstand voltage be that 7～8V is just enough.
Symmetric form HBT, by making the bias voltage work of collector electrode-emission voltage across poles with 0V, can make the current sinking between collector electrode-emitter basically is 0A.
The characteristic of the asymmetric HBT of Figure 11 (B) expression.In asymmetric HBT, the transistorized upward up voltage of forward is not 0V, has the bucking voltage V about 100～hundreds of mV
OFFAt this moment, make collector emitter voltage V
CEWhen bias voltage is 0V, between collector electrode-emitter, produce some current sinkings.In addition, because the structure difference of emitter collector electrode, shown in thick line, the connection resistance R on ' when the connection resistance R on the during work of forward transistor works with reverse transistor is very different.
At this, thick line is represented the load line of work, and half of work is reverse transistorized work.That is, make collector emitter voltage V
CEWhen bias voltage was 0V, the load line of work was crooked near bias point, and it is very poor that distortion level becomes.In addition and since reverse transistorized electric current compare with the transistorized electric current of forward very little, so the power that can make it to pass through is very little.In addition, the connection resistance R on ' when working owing to reverse transistor is very big, inserts loss and becomes very big.
On the other hand, to make emitter and collector be roughly the same structure (identical compound semiconductor and roughly the same impurity concentration) to symmetric form HBT.Therefore, shown in Figure 11 (A), the bucking voltage of symmetric form HBT roughly can be 0V.Therefore, make collector emitter voltage V
CEWhen bias voltage was 0V, the current sinking between collector electrode-emitter can be 0A.Because the load line of work is not in the bias point bending, so distortion level is good.In addition, because reverse transistorized electric current is identical with the transistorized electric current of forward, make the power that can pass through become big.In addition, the connection resistance R on when the connection resistance R on ' when oppositely transistor is worked works with the forward transistor is the same little, so can reduce to insert loss.
Figure 12 represents the profile of pad and distribution.Figure 12 (A) and Figure 12 (B) are the d-d line profile of Fig. 9, and Figure 12 (C) is the e-e line profile of Fig. 9.
Constitute pad P and the gate wirings 120 of the sub-pad I of shared input, the first lead-out terminal pad O1, the first control terminal pad C1 (second switch element SW2 side is also identical), power supply terminal pad V, earth terminal pad G, as shown in the figure, be arranged on secondary collector layer (the n+ type GaAs) layer.Pad P and gate wirings 120 are arranged on the secondary collector layer 2 (Figure 12 (B)) via nitride film 51 or are set directly on the secondary collector layer 2, form schottky junctions (Figure 12 (A), (C)) with secondary collector layer 2 surfaces
Therefore, the quarantine measures as pad P and gate wirings 120 peripheries dispose peripheral conductive area 170 around pad P and gate wirings 120.Periphery conductive area 170 is aforesaid conductive area 23, and is separated with other zone by insulating regions 20.
Figure 13 and Figure 14 be as the 4th embodiment, and expression is configured for other the execution mode of unit element 100 of the active element 200 of switch element.When being used for switch element, the structure of the epitaxial loayer of constituent parts element 100 is structure shown in Figure 10 substantially, also can be structure shown below.
Figure 13 (A) is the profile of unit element 100 that is equivalent to the a-a line section of Fig. 2.Figure 13 (B) is the profile of HBT101 of the b-b line section of Fig. 2.
As mentioned above, according to present embodiment, even the generation that the steady resistance layer also can prevent second breakdown is not set.But also there is the situation that can not fully prevent second breakdown according to FET102 of unit that constitutes constituent parts element 100 and the design of the HBT101 of unit.In addition, when in the HBT101 of unit, flowing electric current very big, also be difficult to fully avoid the generation of second breakdown.Under these circumstances, can repeat to take the second breakdown measure by in the epitaxial structure of the HBT101 of unit, adding the steady resistance layer.
That is, dispose n-type GaAs layer 33b as the steady resistance layer in emitter layer 5a side.In addition, under the situation of switch circuit devices 220, owing to emitter and the collector electrode of the HBT101 of unit are worked symmetrically with respect to base stage, so also dispose n-type GaAs layer 33a as the steady resistance layer in collector layer 3 sides.Because n- type GaAs layer 33a, 33b with regulation resistance value become the steady resistance layer, can prevent to concentrate the generation of the second breakdown that electric currents cause to a unit element 100.
At this moment, as Figure 13 (A), also dispose n-type GaAs layer 33 in the FET102 of unit, but the electric current that flows in the FET102 of unit seldom, the influence that produces by n-type GaAs layer 33 is set is few.
Figure 14 is in the 3rd embodiment, and it is the situation of non-alloy ohm layer that additional non-alloy ohm layer makes the contact layer of emitter 9.Figure 14 (A) is for being provided with the situation of non-alloy ohm layer in the HBT101 of Figure 10, Figure 14 (B) further is provided with the situation of non-alloy ohm layer in the structure that the steady resistance layer is set of Figure 13.In addition, the profile of Figure 14 representation unit HBT101 (the b-b line section that is equivalent to Fig. 2).In order to reduce the contact resistance of emitter contact layer 6a, non-alloy ohm layer 31 is arranged on the emitter contact layer 6a.Non-alloy ohm layer 31 is a n+ type InGaAS layer.At this moment, emitter contact layer 6a is a n+ type GaAS layer, and other semiconductor layer is also identical with Figure 10 (B).At this moment, in the FET102 of unit, non-alloy ohm layer 31 is arranged on contact layer 6bs, the 6bd simultaneously, and is not shown.
In the present embodiment, described symmetric form HBT is used for unit element 101 and constitutes switch circuit devices.Thus, the current sinking that can obtain between collector electrode-emitter is the switch circuit devices of 0A.In addition, because the connection resistance R on ' of the connection resistance R on the during work of the forward transistor of symmetric form HBT during with reverse transistor work about equally, so can obtain collector emitter voltage V in the amplitude of high-frequency signal
CEBe positive part and collector emitter voltage V
CEBe the linear good switching circuit of the switching part of negative part.
In the switching circuit of GaAsMESFET and HEMT, the bias voltage between drain electrode-source electrode is that the current sinking between 0V event drain electrode-source electrode is 0A, collector emitter voltage V in the amplitude of high-frequency signal
CEBe positive part and collector emitter voltage V
CEFor the switching part of negative part linear good.That is, the switch circuit devices 220 at embodiment has the advantage identical with the switch circuit devices of GaAsMESFET and HEMT.In addition, compare with the FET of mono-polar devices, the connection resistance of the HBT of bipolar devices is much lower.The switch element of present embodiment is made of the unit element 100 that connects HBT101 of unit and the FET102 of unit, so can obtain the characteristic of HBT in connecting resistance.That is, the high frequency characteristics of switch circuit devices 220 improves significantly, chip size can be dwindled significantly.
Below, with reference to Figure 15～Figure 17, the 5th embodiment describes to the present invention ground.
The 5th embodiment is by logical circuit is set in the 3rd embodiment ground switch circuit devices 220, can be by the switch circuit devices of a control terminal job.
Figure 15 is a circuit diagram.In addition, in Figure 15, the expression with Fig. 8 (A) in identical electric current skeleton diagram, first and second switch element SW1, SW2 are actually the structure shown in Fig. 8 (B).
Figure 15 (A) connects the inverter circuit 41 of the resistive load situation as logical circuit.That is, resistive load 411 is connected in series at tie point CP with GaAsMESFET412 (pinch-off voltage Vp=0.25V: reinforced), tie point CP is connected via controlling resistance R2 with the grid of for example FET2 of second switch element SW2.In addition, the grid of MESFET412 is connected with a control terminal Ct1.
Figure 15 (B) is for connecting the inverter circuit 41 of enhancement mode/depletion type DCFL (Direct Coupled FET Logic directly the be coupled FET logic) situation as logical circuit.Be that the source electrode of depletion type MESFET413 (pinch-off voltage Vp=-0.4V) and the drain electrode of grid and reinforced MESFET414 (pinch-off voltage Vp=0.25V) are connected in series by tie point CP, tie point CP for example is connected via controlling resistance R2 with the grid of FET2.In addition, the grid of reinforced MESFET414 is connected with a control terminal Ct1.The structure of other of Figure 15 is all identical with the 3rd embodiment, therefore omits its explanation.
By connecting inverter circuit 41, the grid that is applied to the FET2 of the control signal first switch element SW1 on the control terminal Ct1 is applied like this, the complementary signal of control signal is applied to the grid of the FET1 of second switch element SW2.That is, form one with SPDT switch MMIC control terminal.
Logical circuit 41 also can by resistance/or MESFET form.That is, can with in that the switch MMIC of logical circuit is housed is all integrated on 1 chip of GaAS substrate.
Figure 16 represents the inverter circuit of the enhancement mode/depletion type DCFL shown in Figure 15 (B).Figure 16 (A) is plane pattern figure, and figure (16) is the f-f line profile of Figure 16 (A).
D type FET413 is identical with the FET102 of unit shown in Figure 10 (A), (D).That is, at the source electrode 135d of the second layer that constitutes by the distribution metal level and the configuration first grid 127 between the 136d that drains.The below of source electrode 135d and one pole 136d disposes the source electrode 115d and the drain electrode 116d of the ground floor that is made of ohmic metal layer, and the working region is separated by the separated region shown in the double dot dash line 20.Source electrode 115d and drain electrode 116d are connected with contact layer 6bsd, 6bdd respectively.
On the other hand, the channel layer of E type FET414 only is made of raceway groove lower layer (n type InGaP layer) 5b.The source electrode 135e of the second layer that alternate configurations is made of the distribution metal level in E type FET414 and drain electrode 136e, raceway groove lower layer betwixt (n type InGaP layer) 5b surface configuration second grid 128.The gate metal layer of second grid 128 for example is Ti/Pt/Au, with first grid 127 different mining buried gate structure.
Dispose the source electrode 115e and the drain electrode 116e of the ground floor that is made of ohmic metal layer below source electrode 135e and drain electrode 136e, source electrode 115e and drain electrode 116e are connected with contact layer 6bse, 6bde respectively.
The drain electrode 136e of the second layer of the end of E type FET414 (the drain electrode 116e of ground floor is also identical) is shared with the source electrode 135d (the source electrode 115d of ground floor is also identical) of the second layer of D type FET413.Equally, the drain electrode contact layer 6bde of the end of E type FET414 is connected with the source electrode contact layer 6bsd of D type FET413.
Like this, D type FET413 makes the semiconductor layer that forms first and second grid 127,128 different with E type FET414.Thus, according to (buried portion 127b bottom) reaches from the bottom of second grid the setting of the distance of raceway groove lower layer 5b to the setting of the distance of raceway groove lower layer 5b bottom and obtain the pinch-off voltage Vp that stipulates respectively from the bottom of first grid 127.
When constituting logical circuit, the second grid 128 that makes E type FET414 be not the buried gate structure and only first grid 127 are buried gate structures.As mentioned above, because the buried portion 127b of first grid 127 is positioned at n type AlGaAs layer 18b, so can prevent the abnormality diffusion of the Pt of InGaP laminar surface.On the other hand since do not need at E type FET414 big withstand voltage, even for the buried gate structure also can fully guarantee to stipulate withstand voltage.
In addition, first grid 127 and second grid 128 are respectively formed at surface and raceway groove lower layer (n type InGaP layer) the 5b surface of raceway groove upper layer (n type AlGaAs layer) 18b.At this moment, can be by selective etch at n type InGaP layer 19b and raceway groove upper layer (n type AlGaAs layer) 18b, the recess etch that reproducibility makes the surface of formation first grid 127 expose well.Can be by selective etch at raceway groove upper layer (n type AlGaAs layer) 18b and raceway groove lower layer (n type InGaP layer) 5b, the recess etch that reproducibility makes the surface of formation second grid 128 expose well.
Like this, by at raceway groove lower layer (n type InGaP layer) 5b and n+ type GaAs layer 6 configurations n type InGaP layer 19b and raceway groove upper layer (n type AlGaAs layer) 18b, D type FET413 forms the recess etch that expose on the surface of first grid 127 and second grid 128 with selective etch respectively with E type FET414.
In addition, under the situation of the logical circuit shown in Figure 15 (A), also need E type FET412.On the other hand, the FET102 of unit that constitutes the first switch element SW1 (second switch element SW2 is also identical) is D type FET.That is, under the situation of Figure 15 (A), the D type FET of the E type FET412 of logical circuit and the FET102 of unit need be formed on same substrate and with on the semi-conductor layer.At this moment, D type FET and E type FET are not adjacency on pattern, and the FET102 of unit (D type FET) is identical with Figure 16 (B) respectively with the profile of the E type FET412 of logical circuit.That is the recess etch of, can be respectively exposing with the surface of the second grid 128 of the E type FET412 of the first grid 127 of the FET102 of the selective etch unit of formation (D type FET) and logical circuit.
Figure 17 is in comprising the switch circuit devices of logical circuit, as Figure 13 (B), during configuration steady resistance layer and the profile of Figure 16 (B) corresponding D type FET413 and E type FET414.
The HBT101 of unit is symmetric form HBT too, on integrated D type FET413 and the E type FET414 steady resistance layer 33a, 33b is set too at same substrate and on semi-conductor layer.
Because the operating current of logical circuit is seldom, so the time steady resistance layer 33a, 33b can not influence the work of logical circuit.In addition, under the situation of configuration these steady resistance layers 33a, 33b, can form the recess etch that expose on the surface of first grid 127 and second grid 128 by selective etch.In addition, Figure 15 (A) is identical with Figure 17, the E type FET412 of its logical circuit and the FET102 of unit (D type FET) and adjacency not.That is, can carry out the recess etch of first grid 127 and second grid 128 by selective etch.
Figure 18 is the circuit skeleton diagram of the embodiment of presentation graphs 6.
The 6th embodiment is SP3T (Single Pole Three Throw: one pole three is thrown) switch MMIC.Identical with the 3rd embodiment, Figure 18 represents the circuit skeleton diagram corresponding with Fig. 8 (A), and each switch element SW is actually the structure shown in Fig. 8 (B).
SP3T is by the first group of switching elements S1, second switch element group S2, the 3rd group of switching elements S3 of plural serial stage connection switch element SW form respectively.The shared RF port that is connected to of the collector electrode of the collector electrode of the end of the collector electrode of the end of the first group of switching elements S1, second switch element group S2 and the end of the 3rd group of switching elements S3.The one RF port for example is the sub-IN of shared input.
The first group of switching elements S1 is the structure that switch element SW1-1, SW1-2, SW1-3 are connected in series.Switch element SW1-1, SW1-2, SW1-3 are identical with Fig. 8 (B) respectively, are connected in parallel and constitute by the unit element more than 100 of the base stage that connects the HBT101 of unit and the source electrode of the FET102 of unit is individual.The profile of unit element 100 and stereogram are identical with Figure 10.Represent with HBT1-1, HBT1-2, HBT1-3 respectively the HBT101 of unit of each active element 200 that constitutes switch element SW1-1, SW1-2, SW1-3 is blanket, the FET of unit of each active element 200 is summed up represent with FET1-1, FET1-2, FET1-3.
FET1-1, FET1-2, FET1-3 are MESFET, and its source electrode is connected with the base stage of HBT1-1, HBT1-2, HBT1-3 respectively.And each grid of each FET1-1, FET1-2, FET1-3 is connected with the first control terminal Ct11 via controlling resistance R11, R12, R13 respectively.
Second switch element group S2 is the structure that switch element SW1-1, SW1-2, SW1-3 are connected in series.Formation switch element SW1-1, HBT2-1, the HBT2-2 of SW1-2, SW1-3, the base stage of HBT2-3 are connected respectively with the source electrode of FET2-1, FET2-2, FET2-3, and each grid is connected with the second control terminal Ct12 via controlling resistance R21, R22, R23.Other structure is identical with the first switch element SW1.
The 3rd group of switching elements S3 is the structure that switch element SW3-1, SW3-2, SW3-3 are connected in series.Formation switch element SW3-1, HBT3-1, the HBT3-2 of SW3-2, SW3-3, the base stage of HBT3-3 are connected respectively with the source electrode of FET3-1, FET3-2, FET3-3, and each grid is connected with the 3rd control terminal Ct13 via controlling resistance R31, R32, R33.
In addition, each emitter of the other end of the first group of switching elements S1, second switch element group S2, the 3rd group of switching elements S3 respectively with the 2nd RF port promptly the first lead-out terminal OUT1, the second lead-out terminal OUT2, and the 3rd lead-out terminal OUT3 be connected.
The control signal that applies to first, second, third control terminal Ct11, Ct12, Ct13 is H level or L level, applies the base stage supplying electric current of the FET connection of H level signal to the HBT of correspondence.Thus, supply with the switch element of base current to HBT and connect the formation signal path, make the lead-out terminal that is sent to the switch element correspondence of connection to the high frequency analog signals of the sub-IN input of shared input.The resistance purpose is set is to prevent that high-frequency signal from leaking control terminal Ct11, the Ct12 that constitutes interchange ground connection, the DC potential of Ct13 via grid.In addition, the drain electrode of the resolution element between the collector electrode of each HBT and emitter and the GND 30 and each FET and V
DDBetween resolution element 30 all use sensing element.Its explanation of the identical Therefore, omited of other structure with the 3rd embodiment.
Because connection voltage (emitter-to-base voltage) V of the HBT of the switch circuit devices of Figure 18
BEFor example be 2.0V, the pinch-off voltage Vp of FET is-0.4V, so FET and HBT begin to connect simultaneously when the current potential of control terminal exceeds more than or equal to 1.6V than the current potential of the emitter of HBT and collector electrode.Therefore, applying 3V to control terminal and be in the switch element of on-state, because resolution element 30 is a sensing element, so the pressure drop that the base current that flows in sensing element brings is 0V, HBT and FET fully connect, conducting between the emitter-base stage of the switch element of connection side.On the other hand, owing to apply 0V so disconnect the power that side can be born the amplitude of 1.6V to control terminal.At this moment, because SP3T is a tertiary structure,, can in the CDMA mobile phone, fully use so the amplitude of 1.6V is corresponding with the power of 29.6dBm.In addition, both are connected with GND with the emitter of each HBT, collector electrode, are used to introduce the base current of each HBT.In addition, the CDMA mobile phone with high power purposes such as switch circuit devices in, the base current that drives HBT is big, thus can use not can owing to the sensing element of the mobile generation pressure drop of base current as resolution element 30.
Represent during Figure 19 that the 7th executes the circuit diagram of example.The 7th embodiment is SP3T (Single Pole ThreeThrow) switch MMIC.
SP3T is by the first group of switching elements S1, second switch element group S2, the 3rd group of switching elements S3 of plural serial stage connection switch element SW form respectively.The collector electrode of the collector electrode of the end of the collector electrode of the end of the first group of switching elements S1, second switch element group S2 and the end of the 3rd group of switching elements S3 is connected with shared input terminal IN.
The first group of switching elements S1 is the structure that switch element SW1-1, SW1-2, SW1-3 are connected in series.Switch element SW1-1, SW1-2, SW1-3 with a plurality of be connected FET102 and be connected as chain-dotted line with unit element 100 that HBT101 is formed by connecting and constitute grouped component 200a, a plurality of grouped component 200a that further are connected in parallel constitute active element 200 shown in dotted line.
The FET102 of unit is the driving transistors that is used for providing to the HBT101 of unit base current.In addition, the profile of unit element 100 and stereogram are identical with Figure 10.
The source electrode of the FET102 of unit is connected with the base stage of the HBT101 of unit, drain electrode and power supply terminal V
DDConnect.And a unit element 100 is distinguished shared the connection with drain electrode, the grid of emitter, collector electrode and the FET102 of unit of the HBT101 of unit with drain electrode, the grid of emitter, collector electrode and the FET102 of unit of other the HBT101 of unit.
So in the present embodiment, a plurality of unit elements 100 that are connected in parallel constitute grouped component 200a, by a plurality of grouped component 200a formations each switch element as active element 200 that is connected in parallel.
In Figure 19, a grouped component 200a connects three unit elements 100.That is, with the shared emitter E of the shared connection of the emitter of three HBT101 of unit, with the common collector C of the shared connection of the collector electrode of the HBT101 of unit as grouped component 200a as grouped component 200a.In addition, with the shared connection of drain electrode of three the FET102 of unit common drain D as grouped component 200a.The also shared connection of the grid of the FET102 of unit.
And between the shared emitter E with each grouped component 200a, between the common collector C, shared connection between the grid of the FET102 of unit constitutes the switch element SW1-1 as the first order of active element 200 respectively.The switch element SW1-3 of partial switch element SW1-2, the third level is also identical.
Second switch element group S2 is identical with the first group of switching elements S1 in addition is connected in series switch element SW2-1, SW2-2, SW2-3.The 3rd group of switching elements S3 ground first group of switching elements S1 is identical to be connected in series switch element SW3-1, SW3-2, SW3-3.
The collector electrode of the end of the first group of switching elements S1, second switch element group S2, the 3rd group of switching elements S3, the collector electrode of the HBT101 of unit of switch element that promptly constitutes the first order is with the one the RF port is shared is connected.The one RF port for example is the sub-IN of shared input.
In addition, each emitter of the other end of the first group of switching elements S1, second switch element group S2, the 3rd group of switching elements S3, promptly constitute the third level switch element the HBT101 of unit emitter respectively with as the first lead-out terminal OUT1, the second lead-out terminal OUT2 of the 2nd RF port, the 3rd lead-out terminal OUT3 is shared is connected.
The base stage of the HBT101 of unit is connected with the source electrode of the FET102 of unit, and the grid of the FET102 of unit at different levels is connected with the first control terminal Ct11, the second control terminal Ct12 and the 3rd control terminal Ct13 via the resolution element 30 of high-frequency signal.
Other is the L level to any of the control signal that applies to first, second, third control terminal Ct11, Ct12, Ct13 for the H level, or be the L level all, the FET102 of the unit connection that applies the signal of H level provides electric current to the base stage of the HBT101 of unit of correspondence.Thus, provide the group of switching elements of base current to connect to the HBT101 of unit and form a signal path, the high frequency analog signals to the sub-IN input of shared input is transmitted to any lead-out terminal.
When first, second, third control terminal Ct11, Ct12, Ct13 were the L level, the first group of switching elements S1, second switch element group S2, the 3rd group of switching elements S3 were cut off.
The structure of the first group of switching elements S1, second switch element group S2, the 3rd group of switching elements S3 is identical, therefore, below the first group of switching elements S1 is described.
Bias point BP is connected respectively with switch element SW1-1, the SW1-2 at different levels of the first group of switching elements S1, emitter and the collector electrode of SW1-3.Bias point BP for example is connected respectively with each grouped component 200a.That is, the bias point BP of shared emitter E connection to a grouped component 200a connects a bias point BP to a common collector C.And, apply equal DC bias (for example GND current potential) respectively to each bias point BP.
In addition, between the shared emitter E and bias point BP of a grouped component 200a, and be connected the resolution element 30 of a high-frequency signal between the common collector C of a grouped component 200a and the bias point BP respectively.
When having the HBT101 of unit to constitute switch element, usually because current amplification degree h
FELess than 1000 is so need very big electric current.Therefore, for example be connected with each switch element is shared respectively at emitter and collector electrode all HBT101 of unit, concentrate via in resolution element 30 and the structure that bias point BP is connected by each switch element, the pressure drop change of the base current that flows in resolution element (resistance) 30 greatly.Consequently, can not apply sufficient bias voltage, can not work fully by the HBT101 of the unit of making to the HBT101 of unit.
Suppose current amplification degree h
FEVery big, for example be more than or equal to 1000 o'clock, as present embodiment, the total amount electrorheological of necessity of the switch circuit devices of multistage connection is big.Its reason is all to provide base current to the HBT101 of unit at different levels of the port of connecting.And necessary base current is not the level several times under the situation of one-level but becomes the greatly quadratic power of progression.
Reason is, for example under three grades situation, because three of switch element SW1-1, SW1-2, SW1-3 are connected in series, if do not make constituent parts HBT101 be of a size of three times, then total connection resistance of the first group of switching elements S1 of a series of connections just can not with the situation of one-level under equate.
Promptly under three grades situation, it is three grades that constituent parts HBT is of a size of under the situation of one-level three times and switch element SW, so when total base current is one-level nine times (3 * 3=9).
Compare when therefore, the needed total amount base current of switch circuit devices of three step switch element SW1-1, SW1-2, three grades of connections of SW1-3 driving is with one-level and increase about one digit number.Like this, because base current becomes very big, two problems have been produced.
First problem as mentioned above, it is big that the pressure drop of the base current that flows in resolution element 30 becomes, and HBT101 can not be worked fully.Second problem is can not the HBT101 of the unit of driving in the base band LSI of mobile phone.
Therefore, in the present embodiment, solve first problem with following measure.That is, a plurality of unit elements 100 that are connected in parallel with the broach shape constitute grouped component 200a, and shared emitter E and the common collector C of grouped component 200a is connected with bias point BP via resolution element 30 by each grouped component 200a.Apply DC bias voltage (for example GND current potential) to bias point BP.
The resistance value of resolution element 30 is generally 5～10K Ω.When base current flows through resolution element 30, produce and the directly proportional pressure drop of base current size at the two ends of resistance.With a plurality of current potential HBT101 groupings that are connected in parallel, be connected with bias point BP via a resolution element 30 respectively by group as grouped component 200a.The degree that its pressure drop can not influenced the work of the HBT101 of unit reduces.
That is owing to base current is disperseed by grouping, so with resolution element 30 that each grouped component 200a of 5～10K Ω is connected in mobile base current diminish, pressure drop also diminishes.In addition, because resolution element 30 is not sensing element but resistance, so integrability is a chip.
Because the FET102 of unit provides base current to the HBT101 of unit, so power supply terminal V
DDProvided the drain current of the FET102 of unit become the base current of the HBT101 of unit.And, at FET102 of unit and power supply terminal V
DDBetween the base current that flows also identical.
Promptly in the FET102 of unit, as common drain D, each common drain D is via resolution element 30 and power supply terminal V with the shared connection of the drain electrode of each grouped component 200a
DDConnect.Connect these resolution element 30 by each grouped component 200a.
If it is big that the pressure drop of the base current that flows in connecting the resistance 30 of the FET102 of unit becomes, then the drain potential of the FET102 of unit descends, and can not guarantee voltage between source electrode-drain electrode of current potential FET102.Thus, the electric current that flows in the voltage between source electrode-drain electrode of the FET102 of unit diminishes, and consequently, it is not enough that the base current of the HBT101 of unit becomes.
Therefore, also with the FET102 of unit grouping, owing to the pressure drop between the source electrode-drain electrode of resistance 30 diminishes, so the HBT101 of unit works fully.
Because resolution element 30 is not sensing element but resistance, so can make all structure divisions of switch circuit devices integrated to a chip.In addition, both are connected with the GND current potential with the emitter of constituent parts HBT101, collector electrode, apply the DC bias to emitter, collector electrode, and can be used for introducing the base current of each current potential HBT.
Take following measure for solving second problem.That is, adopt to make constituent parts FET102 corresponding with constituent parts HBT101 respectively, and with the temperature compensating type unit element 100 of HBT101 of unit and the FET102 of unit disposed adjacent.That is, unit element 100 is by the base current of the HBT101 of the FET102 unit of providing of unit, and provides from power supply terminal V in the FET102 of unit
DDElectric current.Thus, can sufficient base current be provided and make HBT101 work to the HBT101 of unit.
Example to the circuit working of Figure 19 describes.
(apply the H level to the first control terminal Ct11, apply the situation of L level signal to the second control terminal Ct12 and the 3rd control terminal Ct13)
The connection voltage VBE of the HBT101 of the unit of making is 2.0V, and the pinch-off voltage Vp of the FET102 of unit is-0.4V.In this case, the current potential of the emitter of the current potential of the first control terminal Ct11 and the HBT101 of unit and collector electrode is compared to exceed more than or equal to 1.6V (2.0V-0.4V) FET102 of time unit and the HBT101 of unit and is begun to connect.At this, the emitter of the HBT101 of the unit of making and the current potential of collector electrode are GND current potential (0V).
Owing to apply 3V to the first control terminal Ct11, so the current potential of the first control terminal Ct11 becomes 3V (3V-0V) than the enough height of 1.6V.In addition, the pressure drop of the base current that flows in as the electric current of resolution element 30 is very little as mentioned above, so FET102 of unit and the HBT101 of unit fully connect, connects emitter-inter-collector conducting of the HBT101 of unit of side.
On the other hand, disconnect side with respect to the emitter of the HBT101 of unit and the current potential 0V (GND) of collector electrode, the current potential of the second control terminal Ct12 and the 3rd control terminal Ct13 is 0V.The current potential of the second control terminal Ct12 and the 3rd control terminal Ct13 is compared with the current potential of the emitter of the HBT101 of unit and collector electrode when exceeding more than or equal to 1.6V, and FET102 of unit and the HBT101 of unit connect, so disconnect the power that side can be born the amplitude of 1.6V.At this moment, SP3T is a tertiary structure, is that the power of 29.6dBm is corresponding with the amplitude of 1.6V, can fully use in the CDMA mobile phone.
(all applying the situation of L level signal to the first control terminal Ct11, the second control terminal Ct12 and the 3rd control terminal Ct13)
Apply under the situation of L level signal to the first control terminal Ct11, the second control terminal Ct12 and the 3rd control terminal Ct13, all apply 0V to the first control terminal Ct11, the second control terminal Ct12 and the 3rd control terminal Ct13, whole switch element SW same as described above can both bear the amplitude of 1.6V.In addition, at this, with the sub-IN of the shared input of RF port, the first lead-out terminal OUT1, the second lead-out terminal OUT2 and the 3rd lead-out terminal OUT3 are as the GND current potential.
Regard the RF port as current potential for GND, then MESFET as switch element because the MESFET of its circuit arrangement is a depletion type, so even apply the raceway groove that 0V can not cut off MESFET to the grid that is connected with control terminal, applying 0V can not cut off.Therefore, can not be GND current potential and need be set at positive potential with MESFET with the RF ports-settings as the circuit arrangement of switch element.In addition, outside high-frequency signal line is that the GND current potential is different with the current potential of RF port, so the high-frequency signal and the RF port of outside directly can not be linked.That is,, need between them, add connection electric capacity because the high-frequency signal of outside is separated with RF port DC.
But in the present embodiment, there are HBT of unit and the FET of unit to constitute switch element, by being that the GND current potential applies 0V to control terminal and disconnects with the RF ports-settings.Therefore, electric capacity is installed also can be reduced erection space with FET is compared not need to add as the switch circuit devices of switch element.
In addition, disconnect the power that side can be born the amplitude of 1.6V, owing to be three grades of connections, so the power of the amplitude of 1.6V and 29.6dBm is suitable.That is, be widely used in the CDMA mobile phone.
The the 6th and the 7th embodiment is three grades SP3T, can be a level arbitrarily but be not limited to three grades.In addition, circuit is not limited to SP3T, can be SP4T, SP5T ... the number of SPnT and lead-out terminal can be any.In addition, (Double Pole Double Throw: DPDT) etc., input terminal also can be number arbitrarily to DPDT, in addition, also can logical circuit be set as the 5th embodiment.
, as the 8th～the tenth embodiment the situation that n type AlGaAs layer 18a and n type InGaP layer 19a are not set in the unit element 100 is described with reference to Figure 20～25.
The 8th embodiment and the 9th embodiment are the situation of unit element 100 that is configured for the active element 200 of amplifier.The tenth embodiment is the situation of unit element 100 that is configured for the active element 200 of switch element.
With reference to Figure 20～Figure 22, expression is as other form of the unit element that is used for amplifier 100 of the 8th embodiment.The 8th embodiment is not for being provided with the situation of n type AlGaAs layer 18a and n type InGaP layer 19a in the unit element 100 in first embodiment.At this moment, the mesa etch EM of bead L emitter layer 5a forms.
Figure 20 (A) is the a-a line profile of Fig. 2, and Figure 20 (B) is the profile of the HBT101 of unit of the b-b line of Fig. 2.In addition, Figure 20 (C) cuts off stereogram into described two HBT101 of unit when regional by the section shown in the c-c line of Figure 20 (A) with unit element 100, and Figure 20 (D) is the stereogram of the FET102 of unit.In addition, (C) omit connection electrode 17 in (D) at Figure 20 (B).In Figure 20 (C), (D), omit the electrode more than two-layer or two-layer.
As Figure 20 (A), stacked a plurality of semiconductor layers on semi-insulating substrate GaAs substrate 1, i.e. n+ type GaAs layer 2, n-type GaAs layer 3, p+ type GaAs layer 4, n type InGaP layer 5, n+ type GaAs layer 6.The part of semiconductor layer is removed by etching, form mesa shaped.In addition, the separated region 20 that arrives substrate 1 is set.Separated region 20 injects the insulating regions that forms for the ion by B+ etc. as mentioned above.
As Figure 20 (B), (C), the secondary collector layer 2 of the HBT101 of unit is formed on the substrate 1 by epitaxial growth method, is that doped silicon (Si) becomes 3E18cm
-3～6E18cm
-3About the n+ type GaAs layer of higher impurity concentration.Its thickness is thousands of
Collector electrode 3 is formed on a part of zone of secondary collector layer 2, is to be doped to 1E16cm by silicon doping
-3About～10E16cm
-3About the n-type GaAs layer of impurity concentration.Its thickness is thousands of
Base layer 4a is formed on the collector layer 3, is to be doped to 1E18cm by carbon
-3About～50E18cm
-3About the p+ type GaAs layer of impurity concentration.Its thickness is hundreds of
Emitter layer 5a is formed on a part of zone of base layer 4a, and it is to be doped to 1E17cm by silicon doping
-3～5E17cm
-3About the n type InGaP layer of impurity concentration.Its thickness is
The GaAs layer of emitter layer 5a and the upper and lower carries out lattice match.In addition, emitter contact layer 6a is formed on the emitter layer 5a, is to be doped to 3E18cm by silicon doping
-3About～6E18cm
-3About the n+ type GaAs layer of impurity concentration, its thickness is thousands of
The HBT101 of unit of present embodiment forms the InGaP/GaAs heterojunction at emitter layer 5a and base layer 4a.In addition, the semiconductor layer that constitutes emitter layer 5a also can not be an InGaP layer and form GaAs, and at this moment, also the GaAs layer with upper strata and lower floor carries out lattice match.(with reference to Figure 20 (C)) is provided with separatory insulating regions 20 near the face S1 ' below the base layer 4a.In addition, shown in Figure 20 (B), the bottom of emission layer 5a is provided with bead (canopy) L to the side-prominent shape of the base stage 8 that is positioned at both sides.
That is, emitter layer 5a carries out photoetch up to making bead L arrive the thickness of the regulation of exhausting fully near the side.Thus, bead L uses the part of emitter layer 5a, and thereunder part forms.That is, n+ type GaAs layer 6 is carried out mesa etch, proceed to etch in the way of n type InGaP layer 5 by the photoetch program.By new photoetch program remaining n type InGaP layer 5 is carried out mesa etch after removing resist, remove resist.Thus, emitter contact layer 6a and emitter layer 5a form mesa shaped (emitter mesa EM), simultaneously, use the part of emitter 5a thereunder to form bead L.Exhausting of bead L prevents the base layer 4a Surface runoff of recombination current below bead L between emitter-base stage.Can not control the thickness of bead L with selective etch simply as first～the 7th embodiment, the THICKNESS CONTROL of bead L is got final product at ± one hundred～hundreds of A, can be by the thickness of the slow etching solution control bead L of rate of change.
The collector electrode 7 of the ground floor that constitutes by ohmic metal layer (AuGe/Ni/Au) in the position configuration of the surperficial clamping collector electrode 3 of secondary collector layer 2.On the surface of base layer 4a, the base stage 8 that constitutes by ohmic metal layer (Pt/Ti/Pt/Au) with the pattern arrangement of surrounding emitter layer 5a.At the emitter 9 of the top of emitter contact layer 6a configuration by the ground floor of ohmic metal layer (AuGe/Ni/Au) formation.
Figure 20 (D) is the stereogram of the FET102 of unit when by the section shown in the c-c line of Figure 20 (A) unit element 100 being cut off.The FET102 of unit makes n type InGaP layer 5 be channel layer 5b '.In addition, with the n+ type GaAs layer 6 of the superiors as contact layer 6bs, 6bd.Contact layer 6bd, 6bs become drain region and the source region of the FET102 of unit respectively.Contact layer 6bd, 6bs also form mesa shaped, on the channel layer 5b ' that exposes between them grid 12 are set.Under the situation of the buried gate of the undermost Pt of InGaP layer buried gate metal, if the well-crystallized of InGaP laminar surface, then Pt can be in the laterally unusual diffusion of InGaP course.On contact layer 6bd, 6bs, form drain electrode 10, the source electrode 11 of ground floor respectively by ohmic metal layer.
At this, the channel layer 5b ' of the FET102 of unit is all the InGaP layer mutually with the emitter layer 5a of the HBT101 of unit.Thus, can seek high withstand voltageization of the FET102 of unit and the stabilisation on channel layer 5b ' surface.
In addition, at the configuration P+ of lower floor of channel layer 5b ' type GaAs layer 4b.Can prevent from the charge carrier of channel layer by this layer to the substrate side leakage.
In addition, do not influence work is special because the lower floor of p+ type GaAs layer 4b is the FET102 of unit, therefore, the characteristic of the HBT101 of the unit of being designed to is optimum to get final product.
Referring again to Figure 20 (A), unit element 100 is the structure that makes face S1 ' with the face S1 butt of the FET102 of unit shown in Figure 20 (D) of the HBT101 of unit shown in Figure 20 (C).Bearing surface is the face of the c-c line of Figure 20 (A).And, connection distribution 17 is set on the source electrode 11 of the FET102 of unit by distribution metal level (Ti/Pt/Au).Connect the table top of distribution 17, again on the base stage 8 by the HBT101 of the unit of extending on the insulating regions 20 along the FET102 of unit.
Below, with reference to Figure 21～22, other form of the unit element 100 of the 8th embodiment is described.In addition, profile is equivalent to the b-b line section of Fig. 2, is used to illustrate the roughly situation of epitaxial loayer, Therefore, omited connection electrode 17.
Figure 21 (A) is for to be provided with non-alloy ohm layer, with the situation of emitter contact layer 6a as non-alloy ohm layer in the 8th embodiment.
In order to reduce the contact resistance of emitter contact layer 6a, non-alloy ohm layer 31 is set on emitter contact layer 6a sometimes.Non-alloy ohm layer is a n+ type GaAs layer.In this case, emitter contact layer 6a is made as n type GaAs layer, other structure is identical with Figure 20 (B).
Figure 21 (B) is for being provided with the situation of gradient layer.
Exist in emitter 5a and adopt Al
0.3Ga
0.7The As layer, and the GaAs layer of base layer 4a between form the situation of heterojunction.There is the frequency band peak value in this heterojunction in the bottom of conduction band, and this frequency band peak value becomes one of reason of bucking voltage generation.In order to eliminate this frequency band peak value so can dispose and be used for the gradient layer 32 that gently moves to the AlGaAs layer from GaAs, thereby bucking voltage is diminished.
Figure 22 (A) is for being provided with the situation of steady resistance layer in the 8th embodiment.Exist because the design of the FET102 of unit of component unit element 100 and the HBT101 of unit and can not fully prevent the situation that second breakdown takes place.In addition, when in the HBT101 of unit, flowing electric current very big, also be difficult to prevent fully the generation of second breakdown.Can repeat to take the second breakdown measure by in the epitaxial structure of the HBT of unit, adding the steady resistance layer in this case.
That is, dispose n-type GaAs layer 33 as the steady resistance layer in emitter layer 5a side.Become the steady resistance layer owing to have the n-type GaAs layer 33 of regulation resistance value, so can prevent because electric current is concentrated the generation of the second breakdown that causes to a unit element 100.
Figure 22 (B) is for engaging situation about staggering with heterojunction from the Pn between emitter-base stage in the 8th embodiment, emitter layer 5a becomes n type AlGaAs layer.
In common HBT structure, Pn is in conjunction with consistent with heterojunction between the emitter-base stage between the n type AlGaAs layer of emitter layer 5a and the p+ type GaAs layer of base layer 4a.There is the frequency band peak value in this bottom that is combined in the conduction band, and this frequency band peak value becomes the reason that bucking voltage produces.For the generation of the bucking voltage that prevents to cause, can the heterojunction position be departed from from the Pn binding site between emitter-base stage by interpolation n type GaAs layer 34 between the n type AlGaAs of the p+ of base layer 4a type GaAs layer and emitter layer 5a layer by the frequency band peak value.Can make bucking voltage significantly diminish because the heterojunction position combines inconsistent the event with Pn between emitter-base stage this moment.
The principle of HBT is to inject to emitter side for the hole that does not make base stage, disposes as emitter layer 5a likening to the big AlGaAs layer of the GaAs layer band gap of base layer 4a.Under the situation of this structure, the n type AlGaAs layer 5a of the n type GaAs layer of interpolation 34 and position emitter layer thereon is combined into heterojunction.
Figure 23 is the 9th embodiment, at the unit element that is used for amplifier 100 shown in the 8th embodiment, the situation of alternative etched other semiconductor layers is set on the emitter layer 5a of the HBT101 of unit.Promptly, in the 9th embodiment, emitter layer 5a in the unit element 100 of first～the 7th embodiment, n type AlGaAs layer 18a and n type InGaP layer 19a are changed into other semiconductor layer, make the thickness of emitter layer 5a identical, use selective etch to form bead L with the thickness of bead L.In addition, profile is equivalent to the b-b line section of Fig. 2, is used to illustrate the roughly situation of epitaxial loayer, Therefore, omited connection electrode 17.
For example, in Figure 23 (A), on emitter layer (n type InGaP layer) 5a, add n type GaAs layer 35, by the selective etch formation bead L of GaAs/InGaP.The grid of the FET102 of unit is arranged on the n type GaAs layer 35.At this moment, can not use selective etch but can be by making the thickness attenuation of n+ type GaAs layer 6a, or rate of etch measure slowly etc. is controlled.
In Figure 23 (B), on emitter layer (n type InGaP layer) 5a, add n type AlGaAs layer 36, by the selective etch formation bead L of AlGaAs/InGaP.The grid of the FET102 of unit is arranged on the n type AlGaAs layer 36.At this moment, can not use selective etch but can be by making the thickness attenuation of n+ type GaAs layer 6a, or slack-off etc. the measure of rate of etch is controlled.
In Figure 23 (C), on emitter layer (n type AlGaAs type layer) 5a, add n type InGaP layer 37, by the selective etch formation bead L of InGaP/AlGaAs.When exposing on the surface that makes base layer 4a, can not use selective etch for forming base stage.But can determine whether base layer 4a exposes by direct detection etched surfaces.Therefore, may command makes the etching that expose on the surface of base layer 4a.That is, when undercut emitter layer 5a is also residual, because the impurity concentration of emitter layer 5a is low, so even the direct detection contact resistance is very high, resistance value is also very high.On the other hand, because the impurity concentration of base layer 4a is very high, so that its resistance value of direct detection then detects resistance is low, resistance value is step-down also.
In Figure 23, use selective etch to form bead L.Therefore, identical with logical circuit when integrated with the 5th embodiment, can the surface of the grid that forms E type FET be exposed by selective etch.
In Figure 23, other semiconductor layer is identical with Figure 20 (B).
With reference to Figure 24 and Figure 25, represent to be used for other form of the unit element 100 of switch element as the tenth embodiment.Figure 24 (A) is the a-a line profile of Fig. 2, and Figure 24 (B) is the stereogram of the HBT101 of unit, and Figure 24 (C) is the stereogram of the FET102 of unit.In addition, in Figure 24, omit to connect second beyond the distribution 17 and with the electrode on upper strata.
As Figure 24 (A), on semi-insulated GaAs substrate 1, stacked a plurality of semiconductor layers, promptly, stacked n+ type GaAs layer 2, n type InGaP layer 3, p+ type GaAs layer 4, n type InGaP layer 5, n+ type GaAs layer 6.The part of semiconductor layer is removed by etching, form mesa shaped.In addition, the separated region 20 that arrives substrate 1 is set.Separated region injects the insulating regions 20 that forms for the ion by B+ etc. as mentioned above.
Figure 24 (B) is divided into the stereogram of described two HBT101 of unit when regional by the section shown in the c-c line of Figure 24 (A) with unit element, in addition, omits connection electrode 17 at this.The secondary collector layer 2 of the HBT101 of unit is formed on the substrate 1 by epitaxial growth method, is that doped silicon (Si) is 3E18cm
-3～6E18cm
-3The n+ type GaAs layer of higher impurity concentration.Its thickness is thousands of
Collector layer 3 is formed on a part of zone of secondary collector layer 2, is to be doped to 1E17cm by silicon doping
-3About～5E17cm
-3About the n type InGaP layer of impurity concentration.Its thickness is 1000
～5000
Base layer 4a is formed on the collector layer 12, is to be doped to 1E18cm by carbon (C)
-3About～50E18cm
-3About the p+ type GaAs layer of impurity concentration.Its thickness is hundreds of A～2000A.Emitter layer 5a forms mesa shaped (emitter mesa EM) on a part of zone of base layer 4a, be by a silicon doping silicon 1E17cm that mixes
-3～5E17cm
-3About the n type InGaP layer of impurity concentration.Its thickness is
The AlGaAs layer and the GaAs layer of emitter layer 5a and the upper and lower carry out lattice match.In addition, emitter contact layer 6a is formed on the emitter layer 5a, is to be doped to 3E18cm by silicon doping
-3About～6E18cm
-3About the n+ type GaAs layer of impurity concentration, its thickness is thousands of
The HBT101 of unit of present embodiment forms the InGaP/GaAs heterojunction at emitter layer 5a and base layer 4a, in addition also forms the InGaP/GaAs heterojunction in collector layer 3 and base layer 4a.That is, the HBT101 of unit is symmetric form HBT.
In addition, the semiconductor layer that constitutes emitter layer 5a and collector layer 3 also can be for the InGaP layer be not the AlGaAs layer, also carries out lattice match with the GaAs layer of base layer 4a in this case.Near the face S1 ' below the base layer 4a, be provided with and separate with insulating regions 20.
The collector electrode 7 of the ground floor that constitutes by ohmic metal layer (AuGe/Ni/Au) in the position configuration of the surperficial clamping collector layer 3 of secondary collector layer 2.On the surface of base layer 4a, the base stage 8 that constitutes by ohmic metal layer (Pt/Ti/Pt/Au) with the pattern arrangement of surrounding emitter layer 5a.At the emitter 9 of the top of emitter contact layer 6a configuration by the ground floor of ohmic metal layer (AuGe/Ni/Au) formation.
Figure 24 (C) is the stereogram of the FET102 of unit when by the section shown in the c-c line of Figure 24 (A) unit element 100 being cut off.The FET102 of unit with n type InGaP layer 5 as channel layer 5b '.In addition, with the n+ type GaAs layer 6 of the superiors as contact layer 6bs, 6bd.Contact layer 6bd, 6bs become drain region and the source region of the FET102 of unit respectively.Contact layer 6bd, 6bs also form mesa shaped, on the channel layer 5b ' that exposes between them grid 12 are set.On contact layer 6bd, 6bs, form drain electrode 10, the source electrode 11 of ground floor respectively by ohmic metal layer.
In addition, at the configuration P+ of lower floor of channel layer 5b ' type resilient coating 4b.P+ type resilient coating 4b is a p+ type GaAs layer, can prevent from the charge carrier of channel layer to the substrate side leakage by this layer.
In addition, do not influence work is special because the lower floor of p+ type GaAs layer 4 is the FET102 of unit, therefore, the characteristic of the HBT101 of the unit of being designed to is optimum to get final product.
Figure 25 is other the profile of form of the unit element 100 of explanation the tenth embodiment, the profile of a representation unit HBT101 (the b-b line that is equivalent to Fig. 2).
Figure 25 (A) has the structure of gradient layer for eliminating the frequency band peak value.
For example in emitter 5a and collector layer 3, adopt Al
0.3Ga
0.7The As layer, and, between base-emitter, base stage-inter-collector configuration gradient layer 32.That is, between base-emitter, dispose from GaAs to Al
0.3Ga
0.7The Al of the n type that As slowly changes
xGa
1-xAs (X=0 → 0.3) layer for example for example disposes from Al at base stage-inter-collector
0.3Ga
0.7As is to the Al of the slow n type that changes of GaAs
xGa
1-xAs (X=0.3 → 0) layer.Thus, bucking voltage is further diminished.
Figure 25 (B) is for being provided with the situation of steady resistance layer.Exist because the design of the FET102 of unit of component unit element 100 and the HBT101 of unit and can not fully prevent the situation that second breakdown takes place.In addition, when in the HBT101 of unit, flowing electric current very big, also be difficult to prevent fully the generation of second breakdown.Can repeat to take the second breakdown measure by in the epitaxial structure of the HBT101 of unit, adding the steady resistance layer in this case.
That is,, dispose n-type GaAs layer 33 as the steady resistance layer in emitter layer 5a side and collector layer 3 sides owing to adopt symmetric form HBT.Become the steady resistance layer owing to have the n-type GaAs layer 33 of regulation resistance value, can prevent to concentrate to a unit element generation of the second breakdown that causes thus owing to electric current.
In addition, in the 3rd, the 4th, the 5th, the 6th, the 7th, the tenth embodiment, the 5th HBT101 that is used for switch element is symmetric form HBT, so emitter and the collector electrode of the HBT101 of unit can be replaced.
In addition, by the bias circuit that resistance is cut apart etc. is set in the 3rd, the 4th, the 5th, the 6th, the 7th, the tenth embodiment, then the current potential of the emitter of the HBT101 of unit and collector electrode is not limited to the GND current potential and can freely sets.
According to present embodiment, with HBT and FET via the separated region disposed adjacent, with a plurality of be connected MESFET with the base stage of HBT and the unit element of source electrodes connect and compose switch element, and obtain switch circuit devices.That is, the MESFET of unit element is connected with the base stage of the HBT of each broach shape, and HBT and MESFET are via the separated region disposed adjacent.And switch element is with drain electrode and the power supply terminal V of MESFET
DDConnect,, make that electric current changes between collector electrode-emitter of HBT by voltage signal to the grid input of MESFET.Because the distance of HBT and MESFET is approaching, so transmit to MESFET by the heat of the work generation of HBT.But because the MESFET drain electrode has negative temperature coefficient, so the base current of the HBT of present embodiment also has negative temperature coefficient.That is, in the present embodiment, the heating of HBT can make the collector current of HBT reduce.
Therefore, unstable even the operating current of each unit element becomes in the switch element that a plurality of such unit elements are connected in parallel, because electric current is not concentrated so can not produce the destruction that is produced by second breakdown to a unit element.That is, compare with the pick-up current of existing HBT and can increase substantially current density and work.
In addition, in the FET of unit,, do not make buried portion can prevent that to the structure of InGaP layer diffusion the abnormality of Pt from spreading by making it to become for guaranteeing withstand voltage employing buried gate structure.In addition, the emitter mesa of the HBT of unit, base stage table top form and the gate etch of L shaped one-tenth of bead and the FET of unit in can use selective etch, reproducibility is good.
Claims (29)
1. active element is characterized in that having: compound semiconductor substrate, and its stacked a plurality of semiconductor layers form, and form heterojunction between at least one group of (band gap is different) semiconductor layer in a plurality of semiconductor layers; The first transistor, it is arranged on the described substrate, first, second, third semiconductor layer of described semiconductor layer is formed collector layer, base layer, emitter layer respectively, and have collector electrode, base stage, emitter; Transistor seconds, it is arranged on the described substrate, and has grid, source electrode, drain electrode; Unit element, its unit element for described the first transistor and transistor seconds are formed in abutting connection with configuration via separated region, and the described base stage of described the first transistor and the described source electrode of described transistor seconds be connected,
A plurality of described unit elements are connected in parallel, and the drain electrode of the described transistor seconds of described constituent parts element is connected with power supply terminal, the voltage signal of the described grid by being input to described transistor seconds changes the electric current between the collector electrode-emitter of described the first transistor of described constituent parts element.
2. active element as claimed in claim 1 is characterized in that having: the 4th semiconductor layer, and it is arranged on described the 3rd semiconductor layer; The 5th semiconductor layer, it is arranged on the 4th semiconductor layer, and has the etch-rate bigger than the 4th semiconductor layer.
3. active element as claimed in claim 1, it is characterized in that, the described drain electrode of the described transistor seconds of described a plurality of unit elements reaches the shared connection that is connected in parallel to each other of described grid each other, and the described emitter of described the first transistor reaches the shared connection that is connected in parallel to each other of described collector electrode each other.
4. active element as claimed in claim 1 is characterized in that, at least a portion of the channel layer of described transistor seconds is arranged on the semiconductor layer identical with described emitter layer.
5. active element as claimed in claim 1 is characterized in that, the described semiconductor layer and the described transistor seconds that constitute described base layer and described collector layer are continuous.
6. active element as claimed in claim 1, it is characterized in that, described each electrode of described the first transistor is arranged to the broach shape and is extended to first direction, and the described grid of described transistor seconds extends to second direction, and described first direction is vertical with described second direction.
7. active element as claimed in claim 1 is characterized in that, described base layer is a p+ type GaAs layer.
8. active element as claimed in claim 1 is characterized in that, described emitter layer is the InGaP layer.
9. active element as claimed in claim 1 is characterized in that the collector current of described the first transistor has negative temperature coefficient.
10. active element as claimed in claim 2 is characterized in that, each grid of described transistor seconds is arranged on the 4th semiconductor layer.
11. active element as claimed in claim 2 is characterized in that, each grid of described transistor seconds is imbedded the part of orlop metal in described the 4th semiconductor layer.
12. a switch circuit devices is characterized in that having: compound semiconductor substrate, its stacked a plurality of semiconductor layers form, and form heterojunction between at least one group of (band gap is different) semiconductor layer in a plurality of semiconductor layers; The first transistor, it is arranged on the described substrate, first, second, third semiconductor layer of described semiconductor layer is formed collector layer, base layer, emitter layer respectively, and have collector electrode, base stage, emitter; Transistor seconds, it is arranged on the described substrate, and has grid, source electrode, drain electrode; Unit element, its unit element for described the first transistor and transistor seconds are formed in abutting connection with configuration via separated region, and the described base stage of described the first transistor and the described source electrode of described transistor seconds be connected; A plurality of switch elements that described unit element is connected in parallel; The one RF port, it is with the collector electrode of described a plurality of switch elements or emitter is shared is connected; A plurality of the 2nd RF ports, it is connected respectively with the emitter or the collector electrode of described a plurality of switch elements; Power supply terminal, it is connected respectively with the drain electrode of described a plurality of switch elements,
Grid to described transistor seconds applies control signal respectively, by the described the first transistor of being supplied with by the conducting of described transistor seconds of current drives, and forms signal path between the described first and second RF ports.
13. switch circuit devices as claimed in claim 12 is characterized in that, has, and the 4th semiconductor layer, it is arranged on described the 3rd semiconductor layer; The 5th semiconductor layer, it is arranged on the 4th semiconductor layer, and has the etch-rate bigger than the 4th semiconductor layer.
14. switch circuit devices as claimed in claim 12, it is characterized in that, the described drain electrode of the described transistor seconds of described a plurality of unit elements reaches the shared connection that is connected in parallel to each other of described grid each other, and the described emitter of described the first transistor reaches the shared connection that is connected in parallel to each other of described collector electrode each other.
15. switch circuit devices as claimed in claim 12 is characterized in that, at least a portion of the channel layer of described emitter layer and described transistor seconds is arranged on on the semi-conductor layer.
16. switch circuit devices as claimed in claim 12, it is characterized in that, described each electrode of described the first transistor is arranged to the broach shape and is extended to first direction, and the described grid of described transistor seconds extends to second direction, and described first direction is vertical with described second direction.
17. switch circuit devices as claimed in claim 12, it is characterized in that, described the first transistor has heterojunction between described emitter layer and described base layer and between described base layer and described collector layer, and the connection resistance value when the connection resistance value the during work of forward transistor is worked with reverse transistor equates when a base current value.
18. switch circuit devices as claimed in claim 12 is characterized in that, has and each grid of a plurality of described transistor secondses and at least a logical circuit that control terminal is connected, and applies control signal to each grid respectively from this control terminal.
19. switch circuit devices as claimed in claim 12 is characterized in that, the described switch element series multistage of described switch element and other is connected.
20. switch circuit devices as claimed in claim 12 is characterized in that, described base layer is a p+ type GaAs layer.
21. switch circuit devices as claimed in claim 12 is characterized in that, described emitter layer is the InGaP layer.
22. switch circuit devices as claimed in claim 12 is characterized in that, the collector current of described the first transistor has negative temperature coefficient.
23. switch circuit devices as claimed in claim 12 is characterized in that, will provide the bias point of equal inclined to one side current potential to be connected with the emitter and the collector electrode of described switch element respectively.
24. switch circuit devices as claimed in claim 23 is characterized in that, between the emitter of described switch element and the described bias point and the resolution element that connects high-frequency signal between the collector electrode of described switch element and the described bias point respectively.
25. switch circuit devices as claimed in claim 12 is characterized in that, the resolution element of high-frequency signal is connected between described power supply terminal and the described transistor seconds.
26. switch circuit devices as claimed in claim 12 is characterized in that, the described semiconductor layer and the described transistor seconds that constitute described base layer and described collector layer are continuous.
27. switch circuit devices as claimed in claim 13 is characterized in that, each grid of described transistor seconds is arranged on described the 4th semiconductor layer.
28. switch circuit devices as claimed in claim 13 is characterized in that, each grid of described transistor seconds is imbedded the part of orlop metal in described the 4th semiconductor.
29. switch circuit devices as claimed in claim 18 is characterized in that, described logical circuit comprises the 3rd transistor, and the 3rd transistorized grid is arranged on described the 3rd semiconductor layer.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP092875/05 | 2005-03-28 | ||
| JP092869/05 | 2005-03-28 | ||
| JP092874/05 | 2005-03-28 | ||
| JP2005092869A JP2006279316A (en) | 2005-03-28 | 2005-03-28 | Switch circuit device |
| JP011310/06 | 2006-01-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1855493A CN1855493A (en) | 2006-11-01 |
| CN100463179C true CN100463179C (en) | 2009-02-18 |
Family
ID=37195499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100714524A Expired - Fee Related CN100463179C (en) | 2005-03-28 | 2006-03-28 | Active component and switch circuit device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2006279316A (en) |
| CN (1) | CN100463179C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8289065B2 (en) | 2008-09-23 | 2012-10-16 | Transphorm Inc. | Inductive load power switching circuits |
| US9679869B2 (en) | 2011-09-02 | 2017-06-13 | Skyworks Solutions, Inc. | Transmission line for high performance radio frequency applications |
| JP5481461B2 (en) | 2011-11-01 | 2014-04-23 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | switch |
| US9041472B2 (en) * | 2012-06-14 | 2015-05-26 | Skyworks Solutions, Inc. | Power amplifier modules including related systems, devices, and methods |
| US10297001B2 (en) * | 2014-12-26 | 2019-05-21 | Intel Corporation | Reduced power implementation of computer instructions |
| JP2017220584A (en) * | 2016-06-08 | 2017-12-14 | 株式会社村田製作所 | Semiconductor device and power amplifier circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1348255A (en) * | 2000-10-10 | 2002-05-08 | 三洋电机株式会社 | Compound semiconductor switch circuit apparatus |
-
2005
- 2005-03-28 JP JP2005092869A patent/JP2006279316A/en active Pending
-
2006
- 2006-03-28 CN CNB2006100714524A patent/CN100463179C/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1348255A (en) * | 2000-10-10 | 2002-05-08 | 三洋电机株式会社 | Compound semiconductor switch circuit apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2006279316A (en) | 2006-10-12 |
| CN1855493A (en) | 2006-11-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100677816B1 (en) | Active device and switch circuit apparatus | |
| CN101124678B (en) | Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making | |
| US8502282B2 (en) | Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making | |
| CN1874155B (en) | Compound semiconductor device | |
| USRE33209E (en) | Monolithic semiconductor switching device | |
| CN100463179C (en) | Active component and switch circuit device | |
| KR101230808B1 (en) | Asymetric layout structures for transistors and methods of fabricating the same | |
| CN101317271B (en) | Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making | |
| EP3966863A1 (en) | Iii-v semiconductor device with integrated protection functions | |
| JP2010530616A (en) | Improved power switching transistor | |
| US4729007A (en) | Merged bipolar/field-effect transistors | |
| CA1118531A (en) | Semiconductor integrated logic circuit | |
| CN112420694A (en) | Reverse-conducting silicon carbide JFET power device integrated with reverse Schottky freewheeling diode | |
| US4085417A (en) | JFET switch circuit and structure | |
| CN101944528A (en) | MOS (Metal Oxide Semiconductor) grid base electrode switching tetrode | |
| CN215815878U (en) | Integrated chip with isolation structure | |
| JP3083831B2 (en) | Semiconductor device and manufacturing method thereof | |
| US5246871A (en) | Method of manufacturing a semiconductor device comprising a control circuit and a power stage with a vertical current flow, integrated in monolithic form on a single chip | |
| US20060022306A1 (en) | Method for integration of three bipolar transistors in a semiconductor body, multilayer component, and semiconductor arrangement | |
| JP2007194412A (en) | Active element and switching circuit device | |
| Kobayashi et al. | The voltage-dependent IP3 performance of a 35-GHz InAlAs/InGaAs-InP HBT amplifier | |
| Shimura et al. | 1 W Ku-band AlGaAs/GaAs power HBTs with 72% peak power-added efficiency | |
| US20240290878A1 (en) | Vertical power semiconductor device | |
| US20240222487A1 (en) | Power Device with Current Sense | |
| US4656498A (en) | Oxide-isolated integrated Schottky logic |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090218 Termination date: 20130328 |