CA1174388A - Dual trace electro-optic display - Google Patents

Abstract

ABSTRACT

Two signal traces are displayed simultaneously on an electro optic display such as a liquid crystal display. The display may be in cartesian format having mX electrodes and nY electrodes in which case the X electrodes are in strip form whilst each Y electrode comprises two or more interleaved components Ya, Yb. Thus each XY intersection may be addressed by a zero voltage at XYa, or XYb, with above threshold voltages elsewhere. A series of m different coded waveforms are generated and applied a different one to each X electrode. The two traces are sampled and converted to digital sample values. Coded waveforms are generated and applied to each YaYb electrode contemporaneously with those applied to the X electrodes; the codes being generated are selected from the m different codes and relate to the position of the Y electrode and the sample value to be displayed.
The coded waveforms may be binary codes such as pseudo random codes.
priority encoder allocates a priority to sample values of the two trace signals.

Description

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DUAL TR~OE E~q~OPIIC DISPIAY
This invention relates to apparatus for displaying two wave-forms or traces simultaneously.
Conventionally waveforms are displayed on cathode ray tubes in which a stream of high energy electrons is swept across a phosphor screen where it impinges and causes a visible glow. It is possible to make such tubes very small e.g. down to about 3 cm diameter or diagonal but their power consumption is still high for a truly portable display. Also high voltages e.g. ~J 1 to 4kV are required and the accuracy and resolution of the information dis-played may be degraded compared to a larger tube.
One type of electro-optic display that has the advantage of low power consumption and low operating voltage is the liquid ; crystal display device. This typically comprises a thin, e.g.
12 ~m, layer of liquid crystal material contained between glass plates coated on their inner surfaces with electrodes at least one or which is transparent e.g. Stannic Oxide. These electrodes may be arranged in the form of strips with those on one plate ; orthogonal to those on the other plate, i.e. a matrix of row and column electrodes, so forming a plurality of intersections. The electrodes may also be arranged to display information in polar co-ordinate form or in any suitable set of curvilinear co-ordinates.
; By applying selected electric voltages to the electrodes the liquid crystal material at their intersection is caused to change its optical property e.g. to go from light scattering s to clear or between transparent and opaque states. Each area of intersection may be termed an element. Thus with the application '~, of suitable voltages at a plurality of intersections, elements can collectively display information, for example a waveform can be displayed. Qne method of applying the voltages is to use signals which differ from one another by a small phase difference and applying the same phase to a particular row and to particular column electrodes with different phases elsewhere. In this method all intersections in a particular column are 'on' except that one at the particular row and column. This is described in U.K. Patent No. 1,559,074, U.S. Patent No. 4,127,848.
Another type of electro-optic display that can be addressed in matrix form is the a.c. electroluminescent display in which the application of an alternating voltage across a doped phosphor layer causes light emission.
A problem co~mon to matrix addressing is that the inter-sections not required to display information must receive voltages suitable different from the intersections required to show information. This problem is eased is the informa-tion required to be displayed is in the form of a single , 20 valued trace e.g. a sine waveform. In this case each row and column electrode can be addressed simultaneously with its appropriate waveform. However for a 127 x 128 element display this requires at least 128 different waveforms. In the invention described in U.K. Patent No. 1,559,074 a master waveform is divided into 128 waveforms whose ~inimum phase difference is 2~r/128. Alternatively a poly frequency (e.g. 128 different frequencies) or poly-pulse width (e.g.
128 pulse widths) may be used.

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In U.K. Patent Application No. 2,001,794 published February 5, 1979, binary or multi-level coded waveforms are used. For a 128 x 128 display, 128 different waveforms are generated and applied simultaneously one to each row electrode and appropriate ones of these 128 waveforms applied simultaneously to the column electrodes. me codes may be for example binary numbers or pseudo random binary sequences of logic ones and zeros.
TO display tw~ waveform traces simultaneously it is necessary to say use odd columns for one waveform and even columns for the second waveform, thereby reducing display horizontal resolution by a factor of two.
me display of two traces simultaneously using conventional multiplexing techniques is not possible for large displays, e.g.
a 100 x 100 matrix, with present materials since the ratio of the R.M.S. voltage at intersections that are ON to the R.M.S. voltage when OFF is too low e.g. about 1.09 for a 100 x 100 matrix dis-play.
One way of displaying tWD traces simultaneously on a liquid crystal matrix display with two information elements per column, is described in European Patent Application No. 0 020 027, published December 10, 1980. In this specification alternate rows, e.g.
even rows, are addressed with different coded waveforms Vi whilst the odd rows receive a steady voltage for a period Tl. During the next period T2 (equal to Tl) odd rows receive Vi whilst even rows receive the steady voltage. mis allows the addressing of tw~ elements per column with the proviso that one element is at an even row whilst the other is at an odd row. For the occasions where a conflict occurs, i.e. tw~ elements should occur at say an even row, a priority encoder decides which trace has priority and moves the element of the inferior trace up or down one row to an odd row.
An advantage of this method is improved appearance. A dis-advantage of this method is that the ratio VoN/VoFF(RMS value) is ~3. In contrast the ratio VON/VoFF is U.K. Patent 2,001,794 is very much higher since in theory VOFF is zero, but the appearance is reduced for dual trace display because alternate columns only are used for each trace.

~n object of this invention iB to imprc~e tha appear~nce of a dual trace display, similar to that of European Patent Application No. 0 020 027 with an enhanced VON/VoFF
ratio As used herein a matri~ diqplay is defined as a display having a set of n electrodes and a set of m electrodes forming n ~ m intersections or elements whereby infor ation to be displayed i~ obtained by altering the optical property of the display at a des~red number of intersections, the alteration in the optical property being achieved by applications of appropriate voltage waveforms to the two sets of electrodes.

~9 used herein a threshold voltage is that R.M.S. voltage above which a desired observable ootical effect occurs, e.g. liquid crystal becomes clear from a scattering stste or transparent from an opaque state or vice versa.

~ccording to thi3 invention a dual trace electro ootic display comprises a display cell having a first m-set and a second n-~et of electrodes arranged in an m, n matri~, each n electrode beir~ formed by two interleaved components 90 that each m, n electrode inter-~ection is formedby two separate and independently addressable oarts, means for generatin~ m different coded reference waveforms and fo~
~imultaneously aoplying a different one to each m electrode, means for sampling both trace signals and providing digital values of each eamole, means for storing each digital sample, and means for ~electing and generating ones of the m different codes for ~imultaneous application to each n electrode component, the selected code being related to the position of the n electrode and the sample ~alue to be displayed, the arrangement being such that the two traces are collectively displayed at selected electrode intersections where the applied voltage i9 zero or substantially below a threshold ~alue with the other lntersections receiving above a threshold ~alue,for each n electrode one trace element is on one of the lnterleaved components and the second on the other ~ 4 ~

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The display may further compri~e a priority encoder for allocating a priority to sample value~ of the two trace signals.

The m, n matrix may be in X, Y cartesian format, r, ~ polar ; 5 co-ordinate format, or other curvilinear form.

i The interleaved eiectrodes may be of an inter digitated or a meander form with pad~ of rectangular, triangular~ or other suitable shape connected by thin connecting ~ections. ~urthermore each n electrode may be formed by more than two interleaved components.

The m elactrode may be of strip form having a width sufficient to cover a pad of one of the components of an n electride or may be of sufficient width to at least cover two pads, one on each component of the n electrode ; The means for generating a plurality of waveform may include a ~! sample memory, e.g. a random access memory (RA~) , progrqmmed ~! memory e.g. a read only memory (ROM), a pseudo-random number generator, such as a shift register with exclusive OR or ; exclusive NOR feedback, or a binary code generator such as a binary : counter whose out?uts in the form of logic zeros and ones fo~mdifferent waveforms for each binary number generated, other forms of 2 level coding or multi-level coding are pos~ible.
~he ~wo waveform traces may be sampled through a low pa~s filter and may be fed to a charge coupled device (CCD) whose filtered or unfiltered output i3 fed via a sample and hold circuit or directly into an analogue to digital converter (A/D converter)~ ~he two traces Wl, W2 signals may be read into the CCD (used as an analogue i shift register) at a high rate, until the CCD is full, and read out st a slower rate compatible with standard low power low speed A/D
I converters. This mode of operation of the CCD is known as bandwidth compression.

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To obtain a Y shif' to a displayed waveform W1, Td2 an offset voltage msy be applied to the A/D converter or a Y 3hift may oe obtained by adding or subtracti.~g a digital number to the output of the ~D
converter. .~ Y expansion (or contraction) may be obtained by applying a variable gain amplifier or attenuator before the A/D
converter or by altering the full scale reference level of the A/D
converter, ~n X shift or expansio~contraction may be obtained by logic circuits which alters the :,tart or sequence of the read~out of the sample nemory used to define the signals to the second set of electrodes.

~he waveform traces W1, W2 to be displayed may be e.g. sine waves i or other continuous or piecewise continuous functions. Alternatively they may be discontinuous functions as for example when it i8 required to illustrate signal levels multiplexed from a plurality of sensors e.g. temperature or strain gauges. Each sensor output ~ay have a specific pcsit-on alo~g the ~. a~is of a di~play and the sansor output value along the Y axis. This may be arranged so that when all sensor outputs are at their correct value the display is all along the one horizontal line i.e. the error between desired and measured Rensor outputs is displayed. Furthermore different coloured areas of the display may be associated with desired operating ranges so that if an error signal is disilayed it will be coloured green if within certain limits, amber between thi~ range and other limits and red if it lies outside both the~e ranges.

( The invention will now be described, by wa~ of example only, with reference to the accompanying drawings of which:-Figure 1 is a diagrammatic view of a matrix display;
~igure 2 is a sectional view of a liquid crystal cell;
Figure 3 is a view of parts of Y or column electrodes used in Figure 2 to an e~larged scale;
Figure 4 is a view of column electrodes having a different layout to that of Figure 3;
Figure 5 i3 a block diagram showing a matrix displa;- and drive voltage circuits;
Figure 6 i~ a circuit diagram for a priority encoder shown in Figure 5;
Figure 7 is a block diagram of an alternative circuit to that shown in Figure 5;
Pigure 8 is a circuit diagram for a priority encoder shown in Figure 7;
Figures 9, 10 are different forms of Y electrodes that may be used in place of those shown in Figures 3, 4.

Figure 1 shows in diagrammatic form a matrix display arranged in cartesian co-ordinates. It has X1 to Xm row electrodes and Y1 to Yn column electrodes, voltage Vi (i is an integer 1 to m) is applied continuously to each X electrode and selected ones of Vi are applied to the Y electrodes continuously. Information i8 collectively displayed by the circled XY electrode intersections where the voltage difference is zero, the OFF state, with all other intersection receiv-ng a voltage above threshold, the ON state.

The voltage Vi may be binary coded waveforms having a common period T divided into N bits each bit having a logic zero volts or a logic one of positive voltage. This gives 2N possible waveforms with a minimum difference between two waveforms Vi and VJ
~ ~(Vi - VJ)RMS ~ V i ~ J
The waveforms may be of period ~ divided into L bits (L ~ N) in which case 2L waveforms are possible. If 2N out of 2L waveforms are chosen such that each waveform is at least p bits different from ;

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! the others. The minimum difference between Vi and V; is then L ~ (Vi - Vj)R~s ~ V i ~ ;.
Alternatively the waveforms may be pseudo random binary coded wave-rorms. These have the property that (Yi Vj)RMS = congtant when i ~ J.

Figure 2 shows a cross section through a matri~ XY liquid crystal cell 1 with Figure 3 showing details of the Y or column electrodes in detail. The cell 1 compri~es two glas3 plates 2, 3 carrying spaced electrodes 4, 5 arranged in a matrix format and formed by conventional photolithographic processes. The X or row electrode~
4 are stripes of uniform width whilst each Y or column electrode 5 i8 in the form of two Ya, Yb interdiBitated structures spaced apart and electrically isolated from one another. Each Ya, Yb structure is shown to be a series of rectangular pads 11, 12 ~o-ned by a thin connecting link 13, 14. The column electrode~ 4, 5 may be of aluminium or ~ilver to act as a diffuse re~lector at the rear of the cell. Alternatively the Y electrode 5 may be of tin oxide or indium tin oxide possibly with the thin connecting link parts 13, 14 metallised, e.g. with silver, gold, or aluminium, deposited by vacuum evaporation technique~. As shown the width of each X row electrode 4 i~ sufficient to lie across one ~ad 11, on a Ya electrode and one pad 12 on a Yn electrode. A spacer ring 6 maintains the plates 2, 3 about 8 ~ apart, an epo~y resin glue fixes the plates 2, 3 and spacer 6 together. The plates are coated with a I thin layer of a surfactant e.g. lecithin, to give homeotropic alignment of the liquia c~ystal molecules (i.e. the director) at I the ~urfaces. Between the plates 2, 3 is a cholesteric liquid 1 30 cry~tal mqterial 7 incorporating a dichroic dye. Suitable I materials are: El8 (nematic) with about 4~ CB 15 (cholesteric) i (both materials are obtainable from B.D.~. Chemicals Ltd., Poole,Dorset) and one or more of the following pleochroic dye~:

.

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_ g _ N02 ~ N = N ~ ~Me2 (ora~ge red) N02 ~ ~ N = N ~ NMe2 (blue) NMe2 ~ N 3 N ~ N - N ~ N ~ R ~ NMe (violet) ~OC9~ 9 (blue - D16) O
Such a cell operates by the dyed phase change effect in which the liquid crystal material changes from a light absorbing (OFF) state to a light transmissive (ON) state on application of an above threshold voltage.
The display may be observed by light transmission using natural, fluorescent or an electric light 9 behind the display or by projecting an image of the display 1 onto a magnifying lens or mirror or a reflecting screen. Alternatively a reflector 10 may be placed against the outer surface of plate 3 (or the inner surface roughened and silvered as des-20 cribed in U.K. Patent No. 2,028,529A) and the display observed by reflected light.
The display of Figures 2, 3 may also use a nematic e.g. E18 or E18 and 1~ C15 (B.D.H.Chemicals Ltd) long pitch cholesteric mixture as a twisted nematic cell or Schadt & Helfrich cell.

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-- ~o : The t~i~ted nemat-c cell compri398 a thin e.g. 12 ~m thick, layer of nema'ic liauid crystal material contained between two glass plates which have been ur.idirectionally ru~bed to align the liquid cry~tal molecules and ~rrangsd with the rubbing directions orthogona1 and 80 that the director in the centre of the layer has a finite tilt.
This results in a twisted molecular structure which rotates plane : polarised light whose E vector lies parallel or perpendicular to the optical axis of the liquid crystal at the surface of the cell in the absence of an electric field and when a voltage (preferably a.c.
10 25X~-100k~z) above q thre~ho?d (typically 1 volt for a 12 ~m thick : layer) i3 applied the molecules are re-orientated and the layer ceases to rotate plane polari9ed light. The cell i9 pl~ced between polarisers with their optical aY.es parallel or crossed so that ligh' : transmission or extinction is obtained by swit^hine the voltage on or off. Small amount~ e.g. 15 of a cholesteric material may be added to the liquid crystal material, also small amour.ts Gf a dichroic dye may be added in which case the twist angle may be zero and one : or both polarisers i8 omitted from the display.

: 20 As an alternative to rubbing, the plates may have magnesium fluoride : or silicon monoxide deposited by a technique known as oblique : evaporation with an angle of incidence of an evaporating ~eam to the plates of around 5 and/or ~0 as described in U.K. Patent Specification No. 1,~54,296.
~ liquid crystal cell resp4nds to the F~IS value (rather than the : instantaneou3 value) o a waveform providing the period is shorter: t}1an the sum of the cell turn ON and turn OFF time. If the I waveform period is longer the liquid crystal can turn ON and OFF
3 30 within one waveform period. For a twisted nematic cell this typically means that the waveform fundamental frequency is greater than 25 ~.

When a twisted nematic liquid crystal dlsplay is used the polarisers 35 may be coloured differently in different parts of the display.

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; Apparatus for applying waveforms to a matrix display will ~o~ be descr~bed with reference to Figures 5, 6.

As shown a liquid crystal cell 1 ha~ X Y electrode9 arranged in cartesian co-ordinate format with each Y column electrode in two part~, as detailed in Figure 3 or 4, and each X row electrode as shcwn in Figure 3 or 4. For example the cell 1 may be ~ 128 column by 126 row matrix giving 128 x 126 x 2 electrode intersections.
Such a cell 1 reouires a different code Vi for each row plu~ at least one code to allo-,r no information to be written on any selected column.

All row electrodes 4 are connected to a row or reference waveform ! generator 20. This may be a shift and store bus regi~ter fed from a programmed memory, binary counter, or pseudo random code generator such as a shift register with modulo two feedbacX. The function of the generator 20 i~ to generate a different code Vi for each X
electroae undPr the control of a t1~ebnse and t-~ing circuitry controller 21 itself controlled by a master cloc~ 22. ~
All column electrodes 5 are connected to a column waveform generator and selector 23. Its function is to select ones of the codes Vi for application to each Ya, Yb electrode independently, the selected code being related to the value of waveform ~ample to be di~played.
Control i3 from the time controller 21.

Detail3 of code Vi generation are known e.g. from U.K. Patent No. 2,001,794A, and Displa~s, April 1979, pp. 33-41, Shanks et al.

Signals W1, W2 to be displayed are fed serially through variable level amplifiers 24, 25 ~ample and hold circuits 26, 27, A/D
convertors 28, 29, a priority encoder 30, and memory 31 into the column waveform selector 23. A trigger circuit 32 is connected between the amplifiers 24, 25 and sample and hold circuits 26, 27.
All components are controlled by the timing controller 21.

Irformation is loaded as follo~rs: The signals W1, ~2 to be displayed are ~mplified, or attenuated, independently as required by the amplifiers 24, 25. The trigger circuit 32 is armed by the time controller 21 so that when an appro?riate trigger point i~ reached by a chosen w~veform ~11 or W2 the trigger circuit 32 fires and signals the time controller 21 to clock the sample and holds 26, 27, A/D converter~ 28, 29, priority encoder 30 and memory 31 until the memory is full. No further information is entered until updated information i~ required whereupon the above sequence i8 repeated.
A~ previously noted each X electrode 4 crosses a pad 11, 12 from a Y and Yb electrode. Since inform~tion i8 displayed b~ applyine the same code Vi to both an X and a Y electrode and since each X
electrode receives a different code only one OFF element per Ya or Yb electrode iæ possible. This means that, to display two OFF
elements per column, one element is formed by a Ya electrode and the other by a Yb electrode. It follows that there may be occasior~ whor two samples ~hould be displayed at position~ a1org the same Ya, or Yb electrode. Since this i8 not possible it i8 desirahle to give priority to one sample value and move the other one position (a ~ row electrode width) up or down. Priority can be accorded in a number of ways: ~1 or W2 may have priority for alternate columns, or for alternate frames, or one may have continual priority. (Less satisfactorily, W1 may be displayed only on Ya elements and ~2 only on Yb element~ in ~hich case no priority encoder, 30, is required.) - This is achieved for the circuit of Figure 5 by the priority encoder having inputs fro~ the A/D converter~ 28, 29 and having an output to the memory 31. The priority encoder 30 checks to see if two sample values at each column would both occur on a Ya or Yb column : elements. If so it shifts one of the sample value~ one column : element up or down in a manner related to the quantisation noise from the A/D converter.

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Figure 6 shows detai1s of a priority encoder 30 when used with 8-bit numbers of which only 7-~its are used for the dis~lay 1. It comprises a fir~t and a second 8-bit full adder 38, 39 having two sets of 8-inputs Ao to A7 and Bo to B7, Inputs Ao to A7 on the first adder 38 are from output9 QO to Q7 from the A/D con~erter 28 representing s~mple value~ from W1. Likewise inputs Ao to A7 on the second adder 39 represent W2. Of the adder~' inputs B~ to B7 only B1 are u~ed and are connected to OR gates 40, 41. An exclusive NOR gate 42 has two inputs, one connected to the A/D converter 28, Q1 output and the other to the other A/D con~erter 29 output Qg for the purpose of checkine whether both the trace Yamples formed by the numbers on A1 to A7 of the adders ~8, ~9 are simultaneously odd or even. The exclusive ~TOR gate 42 output i~ connected through an inverter 43 to both OR gates 40, 41 and thence to the adder~
15 inputs B1, B1. These OR gates 40, 41 have an input connected to the least significant bit of their associated adders 8 bit word input. First and second AND gates 44, 45 each have three inputs, and an output which is connected to the 5~RY input Cin of the first and second adder 38, 39. The first and second AND gates 44, 45 have one input connected to the least significanl bit of the 8-bit input to their associated adder; another input connected in co~mon to the exclusive ~rOR gate 42 output and another input connected to input si~nals ~ ~. Input signals ~ and ~ ~re ~lso connected to the OR gates 40, 41 asld are selected by means (not shown) to determine w~ich of W1 or W2 i3 to be dominant during each sample period.
:' The first adder 38 has an ~-bit output on outputs Fo to F7. The : least significant bit Fo is left unconnected ~hilst bits F1 to F7 1 30 are connected to a 7 x 2:1 multiplexer 46 havlng a 7-bit output QO
t to Q6. The second adder 39 has its outputs C1 to G7 connected to the multiplexer 46. This multiplexer 46 is controlled through l input C by the output of F1 and a signal Z (~ square wave of frequency twice the conversion rate provided by the timebase : 35 circuitry) through an exclusive NOR gate 47 to determine which of the intputs F or G pas3 to the output Q. The multiplexer 46 outputs QO
- to Q6 form the outputs of the priority encoder 30 shown in Fic~ure 5.

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~able 1 ~hows the priority encoder 30 for all combi~atior~ of the two least significant bits in the two 8-bit word~ to the adders 38, 39 representing both trace samples.
Tabl e 1 ~race 1 ~race 2 Adder Output~
(Adder 38) (Adder 39) ~hen ~ = 1 Hhen ~ = 1 1 0 Al Ao W1' ~2 + 2 W2, W1 ~ 2 0 1 ~2 + 2, W1 + 3 W1 + 2, W2 1 0 0 0 ~ + 2 ~ + 2 1 1 0 0 ~ + 2 H + 2 1 W1, W2 ~ 2 W2 + 3, W1 + 2 1 0 1 W1 ~ 3~ W2 + 2 W2 + 3, W1 + 2 i 0 0 1 ~ + 2 ~ + 2 1 1 0 1 H + 2 ~ + 2 0 0 1 0 H + 2 ~ ~ 2 0 1 1 0 H t 2 ~ ~ 2 1 0 1 0 W1~ W2 + ~ W2, W1 + 2 1 1 1 W2 + 2, W1 + 3 ~2' W1 0 0 1 1 ~ + 2 ~ + 2 0 1 1 1 H t 2 ~ + 2 1 0 1 1 W1~ ~2 + 2 Wl + 2, ~2 + 3 1 1 1 1 ~1 ~ 3~ W2 + 2 W1 + 2, W2 + 3 ~ ~ Wl and ~2 ! ~he 7 bit number~ from the priority encoder are received by the data inputs of the memory 31 and stored.

In operation the traces W1, W2 to be displayed are sampled 26, 27, digitised 28, 29 and placed in appropriate positions in the memory 31 ! as determined by the priority encoder 30. The coded reference ~
waveforms are generated 20 and applied simultaneously to each X row electrode 4, a differe~t code on each electrode 4. ~he column generator 23 reads each store position in the memory 31 and generates one of the Vi different code~ for each Ya, and Yb electrode the code generated being related to the Y position and to the value , of the sample. As a result two traces W2, W2 are collectively di~played at XYa, XYb electrode interBections where 7ero voltage occurs, i.e. the same code Vi i9 applied to both ~ and Ya or Yb electrodes.

5 Figurec 7, 8 3how an alternative form of aparatu~, Signals W1, W2 are fed through ~plifier~ 24, 25, a 2:1 multiplexer 33, a 8a~pl~ and hold circuit 34, an analo6ue to di~ital (A/D) converter 35, a priority encoder with latch ~6, to a memory 31. Other component~ are similar to tho9e of ~igure 5 and are given like reference numeral~, Signal~ W~, W2 are variable amplified, or attenuated as required by amplifiers 24, 25, and fed secuentially through the multiplexer 33. ~hereafter W1~ '~2 are sampled 34, digitised in the A/D
converter 35, allocated priority in the priority encoder 36 and read sequentially into the memory 31. Control of the trigger 32, , multiple~er 3~ ~ample and hold 34, A~ converter 35, priority ; encoder 36 and memory 31 is by the time controller 31.

The priority e~co~er 36 is ~imilar to thal of Figure 6 with thn addition of a latch because the traces W1, W2 3amples enter the priority encoder sequentially. Fi~ure 8 shows details of 'he priority encoder ~6 when used with multiple~ed 8-bit numbers of which only 7-bit3 are used for the di~play. During the first half of the sample period, W2 is output from the A/D converter 35 , and held in the 8-bit latch 37 by means of the signal Y from the,, timing controller 21. The latch 37 holds this value of W2 during the second half of the sample period during which the ~/D
converter 35 outputs the corresponding W1 value from the other ! 30 channel. The priority encoder ures t'~,is W1 value and the latched W2 value in the same way as before and during this second half of the sample period the signal Z (which i9 now a pulsed ;' waveform from the time controller 21) eoes high then low (or vica versa) to output W1 and W2 in appropriate sequence to be written ; 35 into appropriate locations in the memory 31.

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- 16 - , Once the memory is loaded operation of Figure 7 is the same as for ~igure 5.

The circuit of Figure 7 may be modified by arranging the priority encoder 36 after the memory 31.

Figure 9 shows in schematic form a column electrode arranged in a meander configuration. As shown four components are u~ed to form ! one column electrode ~o that four traces may be displayed. 3ach p t Yat ~b~ Yc- Yd f the Y electrode~ Y ~ Yb~ Y , Y nas a rectangular pad 50, 51, 52, 5~ arranged in a column with inter-connecting strips 54, 55, 56, 57. The X row electrodes are wide enough to overlie four pads 50, 51, 52, 53. 'dith the meander type - of co~figuration more or less than four such components may be use~
for each column.

Figure 10 Qhows column electrodes arranged in two parts Y~, Y~ in a meander conf.g~rat-on -~ith reduced separation betwee~ adjac~nt columns. Each Ya, Yb component comprises rectangular pads 58, 59 with thin interconnecting strips 60, 61.

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Claims (17)

Claims:-

1. A dual trace electro optic display comprising a display cell having a first m-set and a second n-set of electrodes arranged in an m, n matrix, each n electrode being formed by At least two interleaved components so that each m, n electrode intersection is formed by at least two separate and independently addressable parts, means for generating m different coded reference waveforms and for simultaneously applying a different one to each m electrode, means for sampling both trace signals and providing digital values of each sample, means for storing each digital sample, and means for selecting and generating ones of the m different codes for simultaneous application to each n electrode component, the selected code being related to the position of the n electrode and the sample value to be displayed, the arrangement being such that the two traces are collectively displayed at selected electrode intersections where the applied voltage is zero or substantially below a threshold value with the other intersections receiving above a threshold value, for each n electrode one trace element is on one of the interleaved components and the second on the other.

2. A display according to claim 1 wherein the two interleaved components of each n electrode are interdigitated.

3. A display according to claim 1 wherein each n electrode is formed of at least two components arranged in a meander form.

4. A display according to claim 2 wherein the interdigitated electrodes comprice rectangular pads with thin interconnecting sections.

5. A display according to claim 2 wherein the interdigitated electrodes comprise triangular pads with thin interconnecting sections.

6. A display according to claim 1 and further comprising a priority encoder for allocating a priority to sample values of the two trace signals.

7. A display according to claim 1 wherein the display cell is a liquid crystal display cell.

8. A display according to claim 7 wherein the liquid crystal cell is arranged to provide a progressive molecular twist across the liquid crystal material layer.

9. A display according to claim 7 wherein the liquid crystal cell includes a cholesteric liquid crystal material.

10. A display according to claim 7 wherein the liquid crystal material includes a dye.

11. A display according to claim 1 wherein the m different codes are binary coded waveforms.

12. A display according to claim 11 wherein the binary coded waveforms are, for at least a portion of their sequence, pseudo random codes.

13. A display according to claim 1 wherein the means for sampling both trace signals includes means for reading in samples at a first rate and read out at a second and slower rate.

14. A display according to claim 1 wherein the means for selecting and generating codes for application to each n electrode component includes a programmed memory whose inputs are the digital value of each sample.

15. A display according to claim 1 wherein the means for sampling the two traces signals includes charged coupled devices.

16. A display according to claim 1 wherein the two trace signals are sampled simultaneously.

17. A display according to claim l wherein the two trace signals are sampled sequentially.