Articles by Engineering Research Trends & Articles
International Journal of Modelling, Simulation and Applications (IJMSA), 2017
One of the major problems in the developing country is poor power quality. Poor power quality is ... more One of the major problems in the developing country is poor power quality. Poor power quality is caused
by a system inability to maintain sinusoidal waves which are often caused by introduction of harmonics in
power system. The main objective of this work is to develop and analyze the recompense features of
cascaded multilevel inverter based low pass broadband power filter. This work explores modification of
voltage harmonics using configuration of5 Level H-Bridge cascaded multilevel inverter based low pass
broadband filter (LPF) and without low pass filter to improve power quality of the system. To moderate
harmonic distortion, cascaded multilevel inverter based low pass broadband power filter is proposed and
after compensation the source voltage harmonic distortion is changed. The harmonic distortion which
produce multiple frequency of the expected frequency a system should functions inform of ripples was
reduced and the Total harmonic distortion produced is around 11.17% and 12.13% with and without LPF
respectively after the simulation analysis using Simpower systems block set of MATLAB/SIMULINK.
International Journal of Modelling, Simulation and Applications (IJMSA), 2017
In combinational logic circuits, half adder plays an important role in computation of arithmetic ... more In combinational logic circuits, half adder plays an important role in computation of arithmetic units. As
far as digital electronics is concerned, high processing adders have significant contribution in total delay
and power of the system. This paper presents the comparison between the rise time and fall time obtained
at the sum and carry outputs of the half adder deigned by the using simple interconnects, designed by using
graphene nanoribbon (GNR) interconnects and also the half adders simulated using FinFET drivers and
GNR interconnects.
International Journal of Modelling, Simulation and Applications (IJMSA), 2017
In this paper we analyzed possibility to increase density of elements in circuits NAND and AND ba... more In this paper we analyzed possibility to increase density of elements in circuits NAND and AND based on
field-effect heterotransistors. We introduce an approach to increase density of the considered elements.
Framework the approach it is necessary to manufacture a heterostructure with specific configuration. After
the manufacturing it is necessary to dope required areas of the heterostructure by diffusion or ion implantation. The doping finished by optimized annealing of dopant and/or radiation defects. We compare manufacturing of these transistors, manufactured by diffusion and ion implantation. We analyzed possibility to
decrease mismatch-induced stress in the considered heterostructure. Some comparison of calculated results with experimental one has been done.
International Journal of Modelling, Simulation and Applications (IJMSA), 2017
In this article, a coupling of Laplace transformation and Differential transform method is presen... more In this article, a coupling of Laplace transformation and Differential transform method is presented for
solving heat-like and wave-like equations with variable coefficients. We demonstrate that the proposed
method is very convenient for achieving the analytical solutions of 2D and 3D partial differential
equations. The numerical computation shows the efficiency and simplicity of the method.
International Journal of Modelling, Simulation and Applications (IJMSA), 2017
The Projective changes between two Finsler spaces have been researched and thought through by
man... more The Projective changes between two Finsler spaces have been researched and thought through by
many geometers (see [4], [14], [15], [17]). It's been defined that two Finsler metrics on a smooth
manifold M are considered to be Projectively equivalent in case they consists of the same
geodesics as point sets and their geodesic coefficients is determined by the relation
International Journal of Modelling, Simulation and Applications (IJMSA), 2017
This paper presents the design of high gain and low power fully differential Operational Transcon... more This paper presents the design of high gain and low power fully differential Operational Transconductance Amplifier(OTA). Both the main conventional OTA and the boosting amplifiers are fully differential folded cascode.To increase the open-loop gain of the main OTA two auxiliary operational amplifiers(op-amps) are used. These auxiliary op-amps are fully differential folded cascode op-amps with continuous time Common mode feedbacks (CMFB).CMFB is used in auxiliary op-amps to stablise the designed OTA against temperature. This design has been implemented in 0.18µm CMOS Technology using Cadence EDA tool.Spectre simulation shows that the op-amp has DC gain of 171.7958dB , a noise response of 24.1876nV/Hz, power consumption obtained is 295pW and the unity gain bandwidth is more than 1.5GHz.
International Journal of Modelling, Simulation and Applications (IJMSA), 2018
In this paper, we consider the maximization of the profit of an enterprise that produces several ... more In this paper, we consider the maximization of the profit of an enterprise that produces several types of products (as example we consider the output of three types of products). Maximization of profit is carried out taking into account the possibility of price changes on the example of prices, linearly depending on the number of products on the market. When considering the maximization of profit, several restrictions are taken into account.
International Journal of Modelling, Simulation and Applications (IJMSA), 2018
We consider a new type of anomalous transport in the particular type of continuous time random wa... more We consider a new type of anomalous transport in the particular type of continuous time random walk (CTRW) in the stochastic process where the particle have interaction with its environment and may behave unexpectedly more random or more stable. The process that was utilized in this study uses the integrated Brownian motion subordinated by an inverse α-stable subordinator. The proposed new process has external field which causes the two most probable points to have another point between them and we termed it as anomalous jump. We compute the timescale for the mean squared displacement of the usual continuous time random walk (CTRW) and the anomalous jump. Furthermore, as expected, the time scale for the anomalous jump exhibits an interaction with its environment when there is an imposed memory kernel function. Lastly, using the time scale obtained for the MSD of the anomalous jump, we have generalized the external drift force field on the coupled Langevin equation obtained by Fogedby.
International Journal of Modelling, Simulation and Applications (IJMSA), 2019
In this present article, we have proposed a new probability distribution known as Exponentiated
t... more In this present article, we have proposed a new probability distribution known as Exponentiated
transmuted Rayleigh distribution and studied some statistical properties of the proposed model. Further,
for application point of view, we have derived it from Rayleigh distribution as a baseline distribution and
proved its application in comparison to the its sub-models in terms of fitting a real data as well as
simulated data through Akaike's Information Criteria (AIC) and Bayesian Information Criteria ( BIC) and
log likelihood (LL) criterion of goodness of fit.
International Journal of Microelectronics Engineering (IJME), 2015
VLSI design constraints are always area, power and delay. Power consumption of VLSI has become a ... more VLSI design constraints are always area, power and delay. Power consumption of VLSI has become a leading design concern with the growth of complexity and density. Leakage power reduces battery life for the entire portable battery operated device such as mobile phones, laptop and camcoder and so on. Reduction of leakage power is of peak concern in the present trend of nanotechnology. Many techniques have been projected to reduce the leakage power consumption, but most of these approaches require the process technology support. Input Vector Control is one of the approaches used for static power reduction in standby mode. Leakage in a circuit depends on input vector applied at primary inputs due to stack effect. Minimum leakage vector is the input vector to which a circuit can suggest a minimum leakage for a certain set of test patterns. This paper presents Minimum Leakage Vector for various test circuits using genetic algorithm. The algorithm is simulated in Verilog HDL to acquire MLV. Results explore that heuristic approaches can be considered as better algorithms in finding optimum solution. Another improvement begins during simulation is that implementation of algorithm in HDL converges in lesser number of iterations with runtime savings compared to random search method.
International Journal of Microelectronics Engineering (IJME), 2015
This paper puts forward different low power adder cells using different XOR gate architectures. A... more This paper puts forward different low power adder cells using different XOR gate architectures. Adder plays an important role in arithmetic operation such as addition, subtraction, multiplication, division etc. The optimization and characterization of such low power adder designs will aid in comparison and choice of adder modules in system design. A comparative analysis is performed for the power, delay, and power delay product (PDP) optimization characteristic& deals with the design of five adder cells using transistors and schematic structure using CADENCE tool. 10 transistor adder circuits shows the least power consumption with others. Simulations are performed by using Cadence Design tools using 45nm CMOS technology. The four adder cell module proposed here demonstrates their advantages in comparison with Static Energy Recovery Full (SERF), including lower power consumption, smaller area, and higher speed at different frequencies.
International Journal of Microelectronics Engineering (IJME), 2015
Power factor is a measure of how effectively the VArating of electrical equipment is being utiliz... more Power factor is a measure of how effectively the VArating of electrical equipment is being utilized. A high power factor means more effective utilization. It is also beneficial from the point of view of voltage regulation and reduction in ohmic losses. Therefore PFC-devices are being widely used in industry. The simplest way to improve power factor is to insert switchable static capacitors at the receiving end of a distribution system. The paper presents a novel digital power factor correction technique using Field Programmable Gate Array (FPGA) for a system. A hardware-efficient algorithm for power factor improvement has been developed. State diagram is used to design the phase angle measurement circuit. It attempts to keep the power fact or within narrow bounds (0.95-0.97 lagging).Experimental results have been presented to show the effectiveness of the proposed technique.The general purpose SPARTANE 3AN FPGA kit has been employed for developing the digital controller. All the coding has been done using the hardware description language VERILOG.
International Journal of Microelectronics Engineering (IJME), 2015
This paper presents a novel dynamic latched comparator that consumes lower power and higher speed... more This paper presents a novel dynamic latched comparator that consumes lower power and higher speed than the conventional dynamic latched comparators. This paper also provides a comprehensive review of a variety of comparator designs in terms of power and delay. The comparators and the proposed circuit are designed and simulated their transient responses in Tanner EDA suite using 180 nm CMOS technology and 1V power supply voltage and it demonstrates up to 0.03968 mill watt power consumption and higher speed with delay of 60.29 picoseconds than the conventional latched comparators.
International Journal of Microelectronics Engineering (IJME), 2015
The Operational Transconductance Amplifier (OTA) is the block with the highest power consumption ... more The Operational Transconductance Amplifier (OTA) is the block with the highest power consumption in analog integrated circuits in many applications. Low power consumption is becoming more important in miniature devices, so it is a challenge to design a low power OTA. There is a trade-off between speed, gain and power for an OTA design since these parameters are contradicting each other. There are mainly four different types of OTAs: two stage OTAs, folded-cascode OTAs, telescopic OTAs, flavours of Gain boosted OTAs. The telescopic transconductance amplifier consumes less power compared with the other three transconductance amplifiers, so it is widely used in low power consumption applications. It has also high speed characteristics compared to other three topologies. In this paper Telescopic OTA is designed for 180nm Technology using cadence tool. This designed Telescopic OTA achieved gain 184.4dB, Phase Margin 168.85 degrees, UGB 10GHz which are the basic performance parameters of an OTA.
International Journal of Microelectronics Engineering (IJME), 2015
A numerical model to determine tunnelling currents in metal-insulator-metal (MIM) capacitor is pr... more A numerical model to determine tunnelling currents in metal-insulator-metal (MIM) capacitor is presented is this paper. This model is based on Wentzel-Kramers-Brillouin (WKB) approximation and Tsu-Esaki model. Analytical expressions based on physical parameters have been given in detail. Simulations have been performed for Al-Al 2 O 3-Al system.
IJME - International Journal of Microelectronics Engineering, 2016
This paper presents a reconfigurable processor for different digital signal processing applicatio... more This paper presents a reconfigurable processor for different digital signal processing applications. The
performance of the proposed architecture has been evaluated by taking different dsp applications like Low
pass filter, high pass filter, finite impulse response (FIR) filter and FFT module. We designed the
architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate
it in the FPGA, which show that the hardware scheme is feasible for practical application. The
experimental results clearly reveal the novelty of the architecture for dsp applications. This paper
investigates the potential use of FPGAs for implementing efficient “Reconfigurable Processor” for
different dsp applications. The proposed processor is based on parallel re-configurable which is
implemented on FPGA. FPGAs have become an important component for implementing these functions
with respect to cost, performance and flexibility. The general purpose SPARTAN 3AN FPGA kit has been
employed for developing reconfigurable processor, with all the coding done using the hardware description
language VERILOG.
IJME - International Journal of Microelectronics Engineering, 2016
In this paper a new circuit for improving the input power factor is proposed. The proposed circui... more In this paper a new circuit for improving the input power factor is proposed. The proposed circuit is
constructed based on active elements and it is called Active Impedance Power Factor Correction
(AIPFC). The operation of the AIPFC is based on a PWM technique and it will be modeled and tested
using a MATLAB Program (SIMULINK). In this case, the AIPFC model is installed in two different
power electronics applications. The simulation results for both applications will be presented and
compared with the circuit that the AIPFC is not installed. In both applications the Input Power Factor
(PFin) and the Total Harmonic Distortion (THD) will be recorded. In addition, the proposed AIPFC is
implemented and tested and the experimental result will be presented.
IJME - International Journal of Microelectronics Engineering, 2016
In this era, high performance and multifunctional modules to have in the modern microprocessors h... more In this era, high performance and multifunctional modules to have in the modern microprocessors has become essential. Dynamic gates have been a brilliant choice in the design of these modules. But, as the length of the devices is reducing drastically, the increasing leakage current and decreasing noise margin in dynamic gates, is affecting the performance of the system and making it less robust. This was overcome by the use of keepers. Using a weak PMOS keeper could solve majority of the problems associated due to contention currents, however with the aggressive scaling technologies this has been rendered less effective. On the other hand, using large PMOS can drastically increase the contention current in wide fan-in dynamic logic which results in a drop in the performance. This paper reviews the issues with traditional keepers, followed by the new keeper techniques coming up, including conditional keeper, leakage replica keeper and adaptive keeper techniques which includes rate sensing keeper & variation tolerant keeper design and discuss each design's limitation. This can help to reduce the contention current, thereby decreasing the leakage power and also minimizing the delay time with an added advantage of reduced noise margins.
IJME - International Journal of Microelectronics Engineering, 2016
In today's world there is demand of low power and high speed application circuits for the portabl... more In today's world there is demand of low power and high speed application circuits for the portable devices. To meet this demand dynamic comparator play very important role. It has application mostly in Flash ADC. In my paper, I have Analyzed basic dynamic comparator with different characteristics like Propagation delay, speed, offset, ICMR, slew rate etc. I have used TSMC 180nm and TSMC 90nm technology for simulation and compared woks of both technologies. Finally with optimization of these circuits and comparison of these technologies will helped me in obtaining one circuit which will have low power, low offset and high speed CMOS voltage comparator.
IJME - International Journal of Microelectronics Engineering, 2016
This paper is present very common arithmetic circuit .This circuit is faster has low power consum... more This paper is present very common arithmetic circuit .This circuit is faster has low power consumption by
using a new 3 transistor XOR gate. It has two basic features high speed & low power consumption .For the
arithmetic circuit very useful parameter low power consumption & time delay. The area of a circuit is
directly related to number of gates used in a circuit. In the present design one bit 8T full adder minimizes
area, and hence power efficiency. This paper contributes to better understanding of the behavior of single
bit full adder cell .When low power delay products are essential full adder cell have been implemented in
Tanner 14 Ver. suit and simulation using 70nm CMOS technology to obtain of the performance of the cell
with respect to time and power consumption.
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Articles by Engineering Research Trends & Articles
by a system inability to maintain sinusoidal waves which are often caused by introduction of harmonics in
power system. The main objective of this work is to develop and analyze the recompense features of
cascaded multilevel inverter based low pass broadband power filter. This work explores modification of
voltage harmonics using configuration of5 Level H-Bridge cascaded multilevel inverter based low pass
broadband filter (LPF) and without low pass filter to improve power quality of the system. To moderate
harmonic distortion, cascaded multilevel inverter based low pass broadband power filter is proposed and
after compensation the source voltage harmonic distortion is changed. The harmonic distortion which
produce multiple frequency of the expected frequency a system should functions inform of ripples was
reduced and the Total harmonic distortion produced is around 11.17% and 12.13% with and without LPF
respectively after the simulation analysis using Simpower systems block set of MATLAB/SIMULINK.
far as digital electronics is concerned, high processing adders have significant contribution in total delay
and power of the system. This paper presents the comparison between the rise time and fall time obtained
at the sum and carry outputs of the half adder deigned by the using simple interconnects, designed by using
graphene nanoribbon (GNR) interconnects and also the half adders simulated using FinFET drivers and
GNR interconnects.
field-effect heterotransistors. We introduce an approach to increase density of the considered elements.
Framework the approach it is necessary to manufacture a heterostructure with specific configuration. After
the manufacturing it is necessary to dope required areas of the heterostructure by diffusion or ion implantation. The doping finished by optimized annealing of dopant and/or radiation defects. We compare manufacturing of these transistors, manufactured by diffusion and ion implantation. We analyzed possibility to
decrease mismatch-induced stress in the considered heterostructure. Some comparison of calculated results with experimental one has been done.
solving heat-like and wave-like equations with variable coefficients. We demonstrate that the proposed
method is very convenient for achieving the analytical solutions of 2D and 3D partial differential
equations. The numerical computation shows the efficiency and simplicity of the method.
many geometers (see [4], [14], [15], [17]). It's been defined that two Finsler metrics on a smooth
manifold M are considered to be Projectively equivalent in case they consists of the same
geodesics as point sets and their geodesic coefficients is determined by the relation
transmuted Rayleigh distribution and studied some statistical properties of the proposed model. Further,
for application point of view, we have derived it from Rayleigh distribution as a baseline distribution and
proved its application in comparison to the its sub-models in terms of fitting a real data as well as
simulated data through Akaike's Information Criteria (AIC) and Bayesian Information Criteria ( BIC) and
log likelihood (LL) criterion of goodness of fit.
performance of the proposed architecture has been evaluated by taking different dsp applications like Low
pass filter, high pass filter, finite impulse response (FIR) filter and FFT module. We designed the
architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate
it in the FPGA, which show that the hardware scheme is feasible for practical application. The
experimental results clearly reveal the novelty of the architecture for dsp applications. This paper
investigates the potential use of FPGAs for implementing efficient “Reconfigurable Processor” for
different dsp applications. The proposed processor is based on parallel re-configurable which is
implemented on FPGA. FPGAs have become an important component for implementing these functions
with respect to cost, performance and flexibility. The general purpose SPARTAN 3AN FPGA kit has been
employed for developing reconfigurable processor, with all the coding done using the hardware description
language VERILOG.
constructed based on active elements and it is called Active Impedance Power Factor Correction
(AIPFC). The operation of the AIPFC is based on a PWM technique and it will be modeled and tested
using a MATLAB Program (SIMULINK). In this case, the AIPFC model is installed in two different
power electronics applications. The simulation results for both applications will be presented and
compared with the circuit that the AIPFC is not installed. In both applications the Input Power Factor
(PFin) and the Total Harmonic Distortion (THD) will be recorded. In addition, the proposed AIPFC is
implemented and tested and the experimental result will be presented.
using a new 3 transistor XOR gate. It has two basic features high speed & low power consumption .For the
arithmetic circuit very useful parameter low power consumption & time delay. The area of a circuit is
directly related to number of gates used in a circuit. In the present design one bit 8T full adder minimizes
area, and hence power efficiency. This paper contributes to better understanding of the behavior of single
bit full adder cell .When low power delay products are essential full adder cell have been implemented in
Tanner 14 Ver. suit and simulation using 70nm CMOS technology to obtain of the performance of the cell
with respect to time and power consumption.
by a system inability to maintain sinusoidal waves which are often caused by introduction of harmonics in
power system. The main objective of this work is to develop and analyze the recompense features of
cascaded multilevel inverter based low pass broadband power filter. This work explores modification of
voltage harmonics using configuration of5 Level H-Bridge cascaded multilevel inverter based low pass
broadband filter (LPF) and without low pass filter to improve power quality of the system. To moderate
harmonic distortion, cascaded multilevel inverter based low pass broadband power filter is proposed and
after compensation the source voltage harmonic distortion is changed. The harmonic distortion which
produce multiple frequency of the expected frequency a system should functions inform of ripples was
reduced and the Total harmonic distortion produced is around 11.17% and 12.13% with and without LPF
respectively after the simulation analysis using Simpower systems block set of MATLAB/SIMULINK.
far as digital electronics is concerned, high processing adders have significant contribution in total delay
and power of the system. This paper presents the comparison between the rise time and fall time obtained
at the sum and carry outputs of the half adder deigned by the using simple interconnects, designed by using
graphene nanoribbon (GNR) interconnects and also the half adders simulated using FinFET drivers and
GNR interconnects.
field-effect heterotransistors. We introduce an approach to increase density of the considered elements.
Framework the approach it is necessary to manufacture a heterostructure with specific configuration. After
the manufacturing it is necessary to dope required areas of the heterostructure by diffusion or ion implantation. The doping finished by optimized annealing of dopant and/or radiation defects. We compare manufacturing of these transistors, manufactured by diffusion and ion implantation. We analyzed possibility to
decrease mismatch-induced stress in the considered heterostructure. Some comparison of calculated results with experimental one has been done.
solving heat-like and wave-like equations with variable coefficients. We demonstrate that the proposed
method is very convenient for achieving the analytical solutions of 2D and 3D partial differential
equations. The numerical computation shows the efficiency and simplicity of the method.
many geometers (see [4], [14], [15], [17]). It's been defined that two Finsler metrics on a smooth
manifold M are considered to be Projectively equivalent in case they consists of the same
geodesics as point sets and their geodesic coefficients is determined by the relation
transmuted Rayleigh distribution and studied some statistical properties of the proposed model. Further,
for application point of view, we have derived it from Rayleigh distribution as a baseline distribution and
proved its application in comparison to the its sub-models in terms of fitting a real data as well as
simulated data through Akaike's Information Criteria (AIC) and Bayesian Information Criteria ( BIC) and
log likelihood (LL) criterion of goodness of fit.
performance of the proposed architecture has been evaluated by taking different dsp applications like Low
pass filter, high pass filter, finite impulse response (FIR) filter and FFT module. We designed the
architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate
it in the FPGA, which show that the hardware scheme is feasible for practical application. The
experimental results clearly reveal the novelty of the architecture for dsp applications. This paper
investigates the potential use of FPGAs for implementing efficient “Reconfigurable Processor” for
different dsp applications. The proposed processor is based on parallel re-configurable which is
implemented on FPGA. FPGAs have become an important component for implementing these functions
with respect to cost, performance and flexibility. The general purpose SPARTAN 3AN FPGA kit has been
employed for developing reconfigurable processor, with all the coding done using the hardware description
language VERILOG.
constructed based on active elements and it is called Active Impedance Power Factor Correction
(AIPFC). The operation of the AIPFC is based on a PWM technique and it will be modeled and tested
using a MATLAB Program (SIMULINK). In this case, the AIPFC model is installed in two different
power electronics applications. The simulation results for both applications will be presented and
compared with the circuit that the AIPFC is not installed. In both applications the Input Power Factor
(PFin) and the Total Harmonic Distortion (THD) will be recorded. In addition, the proposed AIPFC is
implemented and tested and the experimental result will be presented.
using a new 3 transistor XOR gate. It has two basic features high speed & low power consumption .For the
arithmetic circuit very useful parameter low power consumption & time delay. The area of a circuit is
directly related to number of gates used in a circuit. In the present design one bit 8T full adder minimizes
area, and hence power efficiency. This paper contributes to better understanding of the behavior of single
bit full adder cell .When low power delay products are essential full adder cell have been implemented in
Tanner 14 Ver. suit and simulation using 70nm CMOS technology to obtain of the performance of the cell
with respect to time and power consumption.