2006 International Symposium on VLSI Design, Automation and Test, 2006
The paper will be organized as follows. The proposed architecture of equalizer is stated in secti... more The paper will be organized as follows. The proposed architecture of equalizer is stated in section 2. Section 3 shows the hardware cost In COFDM receiver, the full time operation equalizer is the first comparison between proposed architecture and direct map method, stage of data recovery. Since the performance of equalizer will and performance in our design. We made summary and conclusions influence the overall system performance, the hardware cost and in section 4, 5, and reference in section 6. power consumption of equalizer may not be the first issue in existing designs. In this paper, we propose an approach of equalizer for MPEG2/H.264 COFDM broadcasting systems. This equalizer is optimized for m Scrambler Outer Coder Itrlae Inner Coder Inelar hardware cost, and power consumption without performance lost. Comparing with existing design for 0.1 8um process, the proposed Mapping design area is reduced to 9.5% and the power consumption is Insertion Flter reduced to 30.10% of division-based equalizer, respectively.
2006 International Symposium on VLSI Design, Automation and Test, 2006
The paper will be organized as follows. The proposed architecture of equalizer is stated in secti... more The paper will be organized as follows. The proposed architecture of equalizer is stated in section 2. Section 3 shows the hardware cost In COFDM receiver, the full time operation equalizer is the first comparison between proposed architecture and direct map method, stage of data recovery. Since the performance of equalizer will and performance in our design. We made summary and conclusions influence the overall system performance, the hardware cost and in section 4, 5, and reference in section 6. power consumption of equalizer may not be the first issue in existing designs. In this paper, we propose an approach of equalizer for MPEG2/H.264 COFDM broadcasting systems. This equalizer is optimized for m Scrambler Outer Coder Itrlae Inner Coder Inelar hardware cost, and power consumption without performance lost. Comparing with existing design for 0.1 8um process, the proposed Mapping design area is reduced to 9.5% and the power consumption is Insertion Flter reduced to 30.10% of division-based equalizer, respectively.
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Papers by Lei-Fone Chen