OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

RISC-V Formal Verification Framework

synthesiseable ieee 754 floating point library in verilog

CDBUS (Controller Distributed Bus) Protocol and IP Core

Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)

A simple MIPS CPU for BUAA CO course (and now NSCSCC).