{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":255402617,"defaultBranch":"master","name":"ramspeed","ownerLogin":"wtarreau","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2020-04-13T17:54:16.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/8141789?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1586800670.0","currentOid":""},"activityList":{"items":[{"before":"02c9cb8ad607abd113c56938a59b247b66acd4da","after":"7e944150ae6f7543ee9cc227d3b2239a89ac3847","ref":"refs/heads/master","pushedAt":"2024-07-07T07:40:40.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"wtarreau","name":"Willy Tarreau","path":"/wtarreau","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/8141789?s=80&v=4"},"commit":{"message":"data: add ramlat results for intel xeon w3-2435\n\nThis 8-core CPU has 4 DDR5 channels at up to 4400 MT/s. The board's\nmanual claims it can even support 4800 MT/s at 1DPC but the DIMMs were\ndouble-sided so that might explain the limitation. The tests were done\nwith 1 and 2 channels, yielding sensibly the same results.","shortMessageHtmlLink":"data: add ramlat results for intel xeon w3-2435"}},{"before":"18689f0cdd72e3adae73e298e5ad0fbc455a989d","after":"02c9cb8ad607abd113c56938a59b247b66acd4da","ref":"refs/heads/master","pushedAt":"2024-06-19T13:10:02.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"wtarreau","name":"Willy Tarreau","path":"/wtarreau","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/8141789?s=80&v=4"},"commit":{"message":"ramwalk: implement a simple ram walk pattern\n\nThis performs a pseudo-random RAM walk pattern over 1GB of RAM. In\nfact it really is only a butterfly walk but that's sufficient to\ndetect when access times can cause performance degradations to\nmemory-heavy applications such as compilers. Execution times of +80%\nwere encountered on rk3588 between DDR4 and DDR5 when using DDR init\ncode v1.16.\n\nIt takes an optional number of rounds in argument to amortize the\ninitialization time. It defaults to 1. This just needs to be called\nunder \"time\".\n\nMeasures:\n  i7-6700k, DDR4-2400 2x64 bits in 4 DIMMs, 10 rounds: 176.7s\n  Altra Q80-26, DDR4-2933, 6x64 bits in 6 DIMMs, 10 rounds: 465.1s\n  rk3588,   DDR4-4224 4x16 bits in 2 chips, 10 rounds: 417.4s\n  rk3588,   DDR5-4800 4x16 bits in 2 chips, 10 rounds: 745.6s","shortMessageHtmlLink":"ramwalk: implement a simple ram walk pattern"}},{"before":"06eda4110c45ab75dd7797ddbffc564f9fbbc4a4","after":"18689f0cdd72e3adae73e298e5ad0fbc455a989d","ref":"refs/heads/master","pushedAt":"2024-01-21T08:40:41.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"wtarreau","name":"Willy Tarreau","path":"/wtarreau","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/8141789?s=80&v=4"},"commit":{"message":"data: add results for armada-xp on the XP-GP board\n\nThe results are quite stable, and allow to detect when the board is\nrunning with L2 cache disabled (this seems to happen as the result\nof entering cpuidle state 2 which powers it down and doesn't seem\nto power it up when leaving the state). Sizes between 64k and 2M\nare around 20ns when enabled, and 88ns when disabled.","shortMessageHtmlLink":"data: add results for armada-xp on the XP-GP board"}},{"before":"c8b7acf7c2fb4bbe53c264df0457a0133121f1e9","after":"06eda4110c45ab75dd7797ddbffc564f9fbbc4a4","ref":"refs/heads/master","pushedAt":"2023-08-24T04:21:13.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"wtarreau","name":"Willy Tarreau","path":"/wtarreau","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/8141789?s=80&v=4"},"commit":{"message":"data: add results for Rock5B, IPI devkit, Ryzen 5800x, Odroid H3\n\nAlso Odroid-N2 at 2.4 GHz was added since only the older 1.8 GHz version\nwas present till now.","shortMessageHtmlLink":"data: add results for Rock5B, IPI devkit, Ryzen 5800x, Odroid H3"}},{"before":"e24bf19b85f52278a99cd28b96ef86a2de87758f","after":"c8b7acf7c2fb4bbe53c264df0457a0133121f1e9","ref":"refs/heads/master","pushedAt":"2023-07-07T13:56:52.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"wtarreau","name":"Willy Tarreau","path":"/wtarreau","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/8141789?s=80&v=4"},"commit":{"message":"data: add results for VisionFive2\n\nThe board has incredibly slow memory accesses. At 1 GB, 8xPTR reaches\n1 microsecond! These slower accesses as size grows likely indicate a\nsmall dTLB cache. But even at 4MB work area we're already reaching\n768ns for 8xPTR, 405ns for 4xPTR, 221 for 2xPTR and 125 for 1xPTR.\nIt could be possible that the DDR controller's frequency is abnormally\nlow.","shortMessageHtmlLink":"data: add results for VisionFive2"}}],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEeL8LtAA","startCursor":null,"endCursor":null}},"title":"Activity · wtarreau/ramspeed"}