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tn7dsl.c
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tn7dsl.c
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/************************************************************************************************
* tn7dsl.c
* Avalanche DSL driver
*
* Zhicheng Tang, [email protected]
* 2000 (c) Texas Instruments Inc.
*
* 3/23/05 CPH Change dslhal_api_setMaxBitsPerCarrier to dslhal_api_setMaxBitsPerCarrierUpstream.
* Add "dslctl" to read Phy Feature Control bit.
* 5/10/05 AV Added tn7dsl_proc_train_mode_export(). (CQ9605).
* 5/24/05 AV Fixing the incorrect parsing of the DSL_BIT_TMODE environment variable after the
* the modulation environment variable.
* 6/02/05 AV Changing the location of the tn7dsl_set_modulation function to overcome the
* degradation in throughput. (MR-2464).
* 6/2/05 SANJAY Added a print in case of failue of DSL Init. Rearranged the code in case of
* Failure so that cat on proc file doesnt give Seg. fault.
* 8/8/05 CPH CQ9600 (partial) AnxBM support
* 8/10/05 CPH CQ9776 (partial) TR69 support
* 8/16/05 CPH Added nohost_flag
* 8/19/05 JZ Returning error code in dslmod_sysctl function.(SR 1-4767201), CQ # 9861.
* 8/20/05 AV Modified to use the function to get the capability of the chip,
* tn7atm_read_can_support_adsl2. Relocated structure dsl_modes for performance.
* 8/24/05 CPH CQ9885: Added clearEoc support for ADSL2/2+
* 9/5/05 CPH CQ9660 (partial TR69) SNRpsds, QLNpsds reporting updated.
* 9/13/05 AV Replaced some of the shim calls with direct calls for performance. The shim
* calls are left in comments for reference.
* 09/21/05 AV Renamed the overloaded memcmp and memcpy functions to
* tn7atm_memcmp and tn7atm_memcpy respectively to allow support
* for being compiled directly into the kernel.
* 9/22/05 AV Adding support for the new LED driver in BasePSP 7.4. A new macro TN7DSL_LED_ACTION
* has been used to replace the direct calls to the old LED handler.
* 7/10/05 AV/CPH Changed dprintf to dgprintf and compile time selection of dslhal_api_getQLNpsds()
* dslhal_api_getSNRpsds() and for code size reduction.
* 10/11/05 JZ Fix for auto PVC oam ping lost case, changed the type value for 'S' - segment
* oam ping to have correct oam cell type.
* 10/17/05 AV Enabling the logic to use prom_setenv() and prom_unsetenv() in BasePSP 7.4, for
* clearing the "modulation" env variable, when the user upgrades to the new
* bit mode scheme.
* 10/19/05 AV Removing the prototypes for prom_setenv() and prom_unsetenv(), as they conflict
* with the ones in the asm/mips-boards/prom.h file.
* 11/03/05 MK CQ10037: Added invntry_vernum environment variable to be able to set version number
* in ADSL2/ADSL2+ modes.
* 11/3/05 CPH CQ9885 Added ClerarEoc ACK (porting).
* 11/3/05 JZ Added code to convert old mode to new bit mode in tn7dsl_set_modulation()
* 1/16/06 CPH CQ10269 Fixed tn7dsl_clear_eoc_close() crash problem
* 01/25/06 JZ CQ: 10273 Aztech/Singtel oam pvc management issue, new PDSP 0.54
* 01/25/06 JZ CQ: 10275 Add Remote Data Log code. Search ADV_DIAG_STATS in ATM
* driver code and manually turn on it for enabling the feature
* UR8_MERGE_START Report_SES Manjula K
* 03/14/06 MK CQ10369: Added print statement to report errored Seconds and severely errored secs.
* UR8_MERGE_END Report_SES
* UR8_MERGE_START CQ10449 Jack Zhang
* 04/04/06 JZ CQ10449: Enhanced remote data log for showtime SNR for ADSL2/2+ mode
* UR8_MERGE_END CQ10449
* UR8_MERGE_START CQ10450 Jack Zhang
* 4/04/06 JZ CQ10450: Increase Interrupt pacing to 6 when downstream connection rate is higher than 20Mbps
* UR8_MERGE_END CQ10450
* UR8_MERGE_START CQ10505 ManjulaK
* 05/19/06 MK CQ10505: Report vendor id through inventory command in ADSL2/2+ mode
* UR8_MERGE_END CQ10505
* UR8_MERGE_START CQ10442 Manjula K
* 05/31/06 MK CQ10442: Added code to boost interrupt pacing to 6 when SRA occurs and DS connect rate jumps
* higher than 20Mbps.
* UR8_MERGE_END CQ10442
* UR8_MERGE_START CQ10639 Manjula K
* 06/02/06 MK CQ10639: Setting interrupt pacing to default when DS connect rate drops less than 20Mbps and
* modem is not connected in AnnexM mode.
* UR8_MERGE_END CQ10639
* UR8_MERGE_START CQ10682 Jack Zhang
* 6/15/06 JZ CQ10682: Display ADSL training messages in ATM driver proc file system
* UR8_MERGE_END CQ10682*
* UR8_MERGE_START CQ10640 Jack Zhang
* 7/10/06 JZ CQ10640: DSP memory dump function and memory dump format incorrect
* UR8_MERGE_END CQ10640*
* UR8_MERGE_START CQ10715 Manjula K
* 07/20/06 MK CQ10715: Corrected DS Max Attainable Bit Rate calculation in ADSL1 mode.
* UR8_MERGE_END CQ10715
* UR8_MERGE_START CQ10700 Manjula K
* 07/24/06 MK CQ10700: Added counters for reporting packets dropped by ATM Driver/SAR.
* UR8_MERGE_END CQ10700
* UR8_MERGE_START CQ10880 Jack Zhang
* 8/30/06 JZ CQ10880: Add DHAL api for sending mailbox message for L3
* UR8_MERGE_END CQ10880*
* UR8_MERGE_START CQ10978 Jack Zhang
* 10/4/06 JZ CQ10978: Request for the DSL Power Management Status Report
* UR8_MERGE_END CQ10978*
* UR8_MERGE_START CQ10979 Jack Zhang
* 10/4/06 JZ CQ10979: Request for TR-069 Support for RP7.1
* UR8_MERGE_END CQ10979*
* UR8_MERGE_START CQ11057 Jack Zhang
* 11/03/06 JZ CQ11057: Request US PMD test parameters from CO side
* UR8_MERGE_END CQ11057*
* UR8_MERGE_START CQ11054 Jack Zhang
* 1/02/07 JZ CQ11054: Data Precision and Range Changes for TR-069 Conformance
* UR8_MERGE_END CQ11054*
* UR8_MERGE_START CQ11579 Jeremy : #1 - corrected TxPower to allow negative # reporting
* 04/02/07 #2 - corrected T1413 MaxAttainableRate
* UR8_MERGE_END CQ11579
* UR8_MERGE_START CQ11813 Hao-Ting Lin
* 06/11/07 Hao-Ting CQ11813 CLI redirect support in linux
* Add debug message Init and Print function for /proc entry
* UR8_MERGE_END CQ11813
* 09/18/07 CPH CQ11466: Added EFM support.
*********************************************************************************************/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/atmdev.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/smp_lock.h>
#include <asm/io.h>
#include <asm/mips-boards/prom.h>
#include <linux/proc_fs.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/sysctl.h>
#include <linux/timer.h>
#include <linux/vmalloc.h>
#include <linux/file.h>
/* Modules specific header files */
#ifdef AR7_EFM
#include "tn7efm.h"
#endif
#include "tn7atm.h"
#include "tn7api.h"
#include "dsl_hal_api.h"
#include "dsl_hal_support.h"
//UR8_MERGE_START CQ10450 Jack Zhang
#define _SIZE_T_
#include "dsl_hal_register.h"
//UR8_MERGE_END CQ10450*
/* For the changes for trainning modes using bit fields.
Defaults are for backward compatibility.
*/
#define OLD_TRAINING_VAL_GDMT 3
#define OLD_TRAINING_VAL_T1413 2
#define OLD_TRAINING_VAL_MMODE 1
#define NEW_TRAINING_VAL_GDMT 2
#define NEW_TRAINING_VAL_T1413 128
#define NEW_TRAINING_VAL_MMODE 255
int testflag1 = 0;
extern int __guDbgLevel;
extern sar_stat_t sarStat;
extern unsigned int SAR_FREQUNCY;
static int dslInSync = 0;
static int inter_pace_boosted = 0; //UR8_MERGE_START_END CQ10442 Manjula K
static int bMarginThConfig;
static int bMarginRetrainEnable;
static char EOCVendorID[8] =
{ 0xb5, 0x00, 0x54, 0x53, 0x54, 0x43, 0x00, 0x00 };
static int trellis = 1;
static int nohost_flag =0;
static unsigned int dslReg;
#define CLEAREOC_ACK 0x80
#define CEOC_RESP 0x02 // define clearEoc Ctrl as in G.992.3 sec7.8.2.4.1
#define CEOC_CMD 0x00
static int eocctrl_resp=0;
static int eocctrl_cmd=0;
#define TC_SYNC 1
#define SYNC_TIME_DELAY 500000
/* Common LED variables. */
#if defined (CONFIG_MIPS_AVALANCHE_COLORED_LED) || defined (CONFIG_LED_MODULE)
static int led_on;
/* Definition of the handle for LED module. They will be NULL for old LED implementation. */
void *hnd_LED_0 = NULL;
#endif
#if defined (CONFIG_LED_MODULE)
led_reg_t ledreg[2];
#endif
#if defined (CONFIG_MIPS_AVALANCHE_COLORED_LED)
/*since the structure has the same elements as led_reg_t, we are re-using the variable name. */
static struct led_funcs ledreg[2];
#endif
#define DEV_DSLMOD 1
#define MAX_STR_SIZE 256
#define DSL_MOD_SIZE 256
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#define tn7dsl_kfree_skb(x) dev_kfree_skb(x)
//---------------------------------------------
// Begin Clear EOC definitions
//---------------------------------------------
//#define MAX_CLEAR_EOC_BUF_SIZE 600 // moved to <tn7api.h>
#define MAX_RAW_CLEAR_EOC_MSGSIZE 514 // see ITU G997.1
#define HDLC_INIT 0xFFFF
#define HDLC_FLAG 0x7E
#define HDLC_ESC 0x7D
#define HDLC_INV 0x20
#define HDLC_GENPOL 0x8408
#define HDLC_GOOD 0xF0B8
typedef struct
{
unsigned int len; // packet length
unsigned char data[MAX_CLEAR_EOC_BUF_SIZE]; // data field
} clearEocBufDesc_type;
/* *INDENT-OFF* */
typedef struct
{
unsigned int clearEocEnabled; // 0: disabled; 1: enabled
clearEocBufDesc_type *pTxBufDesc[4]; // Tx buffer desc pointer array
clearEocBufDesc_type *pRxBufDesc[4]; // Rx buffer desc pointer array
unsigned int txRdIndex; // host write
unsigned int txWrIndex; // DSP write
unsigned int rxRdIndex; // DSP write
unsigned int rxWrIndex; // host write
} clearEocParm_t;
/* *INDENT-ON* */
//L2 Buffer Struct Type
typedef struct {
unsigned short L2UBufInInx; //L2 module write, OVHD module read only
unsigned short L2UBufOutInx; //OVHD module write, L2 module read only
unsigned short L2DBufInInx; //OVHD module write, L2 module read only
unsigned short L2DBufOutInx; //L2 module write, OVHD module read only
unsigned char L2StatusFlag; //rcv L2 status Flag
unsigned char dummy[3];
unsigned char *L2UBuf; //L2 upstream buffer
unsigned char *L2DBuf; //L2 downstream buffer
unsigned short L2TxBufSize; //L2 transmit buffer size
unsigned short L2RxBufSize; //L2 receive buffer size
} DI_L2_BufDef_t;
typedef DI_L2_BufDef_t DEV_HOST_L2clearEocDef_t;
static clearEocParm_t ClrEoc;
static clearEocParm_t *pClrEOC = &ClrEoc;
static int EocRxTotalPackets;
static int EocTxTotalPackets;
static int EocRxTotalBytes;
static int EocTxTotalBytes;
static int ErrEocBufFull;
static int ErrEocBufIndex;
static int ErrEocBufMax;
static int ErrEocMsgOversized;
static int ErrEocTxHdlcCRC;
static int ErrEocRxHdlcCRC;
static int ErrEocRxHdlcFraming;
static int ErrEocRxPush;
//CQ10269 cph 1/16/06 Fixed clearEoc Crash problem
static clearEocBufDesc_type *pTxBufDescSave[4]; // Tx buffer desc pointer array
static clearEocBufDesc_type *pRxBufDescSave[4];
//--------------------------------------------
// End of Clear EOC definitions
//--------------------------------------------
#define host2dspAddrMapping(a) (((int)a)&~0xe0000000)
/* *INDENT-OFF* */
/* Old enum values for backward compatibility */
enum
{
NO_MODE = 0,
MULTI_MODE = 1,
T1413_MODE = 2,
GDMT_MODE = 3,
GLITE_MODE = 4,
ADSL2_MODE = 8,
ADSL2_DELT = 9,
ADSL2_PLUS = 0x10,
ADSL2_PLUS_DELT = 0x11,
READSL_MODE = 0x20,
READSL_PLUS_DELT = 0x21,
ADSL2_ANNEX_I = 0x100, //Not supported yet
ADSL2_ANNEX_J = 0x200, //Not supported yet
ADSL2_ANNEX_M = 0x400,
ADSL2_PLUS_ANNEX_I = 0x800, //Not supported yet
ADSL2_PLUS_ANNEX_J = 0x1000, //Not supported yet
ADSL2_PLUS_ANNEX_M = 0x2000
};
/* *INDENT-ON* */
#ifndef ADIAG
#ifdef AR7_EFM
unsigned char DSP_FIRMWARE_PATH[]= "/lib/modules/ar0700xx.bin";
#define DSP_DEBUG_FIRMWARE_PATH "/var/ar0700xx.bin"
#else
#define DSP_FIRMWARE_PATH "/lib/modules/ar0700xx.bin"
#endif
#else
#define DSP_FIRMWARE_PATH "/var/tmp/ar0700xx_diag.bin"
#endif
/* externs */
extern struct atm_dev *mydev;
extern unsigned int oamFarLBCount[4];
/* module wide declars */
static PITIDSLHW_T pIhw;
static volatile int bshutdown;
static char info[MAX_STR_SIZE];
/* Used for DSL Polling enable */
static DECLARE_MUTEX_LOCKED (adsl_sem_overlay);
//kthread_t overlay_thread;
/* end of module wide declars */
/* Internal Functions */
static void tn7dsl_chng_modulation(void* data);
static unsigned int tn7dsl_set_modulation(void* data, int flag);
static void tn7dsl_ctrl_fineGain(int value);
static void tn7dsl_set_fineGainValue(int value);
static int dslmod_sysctl (ctl_table * ctl, int write, struct file *filp,
void *buffer, size_t * lenp);
static void tn7dsl_register_dslss_led(void);
void tn7dsl_dslmod_sysctl_register(void);
void tn7dsl_dslmod_sysctl_unregister(void);
static int tn7dsl_clear_eoc_receive(void);
static int tn7dsl_proc_snr_print (char *buf, int count, int *eof, int data);
/* end of internal functions */
// UR8_MERGE_START CQ11054 Jack Zhang
#define gInt(a) ((int)a/10)
#define gDot1(a) ((a>0)?(a%10):((-a)%10))
// UR8_MERGE_END CQ11054*
#ifdef AR7_EFM
void *tn7dsl_get_pIhw(void);
void *tn7dsl_get_pIhw(void)
{
return pIhw;
}
void tn7dsl_disable_alarm(void)
{
unsigned int alarmEnable=0;
// disable alarm
dslhal_api_setMarginMonitorFlags(pIhw,1,alarmEnable);
dslhal_api_disableLosAlarm(pIhw,!alarmEnable);
}
#endif
//cph 9/6/07 Automatically detect 0x or not 0x and pass to atoh & atoi accordingly.
int os_atoih (const char *pstr)
{
int val;
if((pstr[0] == '0') && ((pstr[1] == 'x') || (pstr[2] == 'X')))
val = os_atoh(&pstr[2]);
else
val = os_atoi(pstr);
return val;
}
int os_atoi(const char *pStr)
{
int MulNeg = (*pStr == '-' ? -1 : 1);
return (MulNeg * (simple_strtoul(pStr, (char **)NULL, 10)));
}
int os_atoh(const char *pStr)
{
int MulNeg = (*pStr == '-' ? -1 : 1);
return (MulNeg * (simple_strtoul(pStr, (char **)NULL, 16)));
}
unsigned long os_atoul(const char *pStr)
{
return((unsigned long) simple_strtoul(pStr, (char **)NULL, 10));
}
void dprintf (int uDbgLevel, char *szFmt, ...)
{
#ifdef DEBUG_BUILD
static char buff[256];
va_list ap;
if( __guDbgLevel < uDbgLevel)
return;
va_start( ap, szFmt);
vsprintf((char *)buff, szFmt, ap);
va_end(ap);
printk("%s", buff);
#endif
}
int strcmp(const char *s1, const char *s2)
{
int size = strlen(s1);
return(strncmp(s1, s2, size));
}
int strncmp(const char *s1, const char *s2, size_t size)
{
int i = 0;
int max_size = (int)size;
while((s1[i] != 0) && i < max_size)
{
if(s2[i] == 0)
{
return -1;
}
if(s1[i] != s2[i])
{
return 1;
}
i++;
}
if(s2[i] != 0)
{
return 1;
}
return 0;
}
// * UR8_MERGE_START CQ10640 Jack Zhang
int tn7dsl_dump_dsp_memory(char *input_str) //cph99
{
int i;
volatile int addr;
volatile int wrd_to_read;
char tmp[16];
unsigned int buf[20];
/* Read the first 8 characters for the address */
for(i=0; i<8; i++)
tmp[i] = input_str[i];
tmp[i] = '\0';
addr = os_atoh(tmp);
/* Read the remaining characters as the value */
wrd_to_read = os_atoh(&input_str[8]);
/* Read back the values from the memory location */
printk("Reading %d words from dsp address = 0x%08x\n", wrd_to_read, addr);
dslhal_support_blockRead((void *) addr, &buf, wrd_to_read*4);
for(i = 0; i < wrd_to_read; i++)
{
if(!(i % 4))
{
printk("\n%08x: ", addr);
addr+=16;
}
printk("%08x ", buf[i]);
}
printk("\n");
return(4 * i);
}
// * UR8_MERGE_END CQ10640*
unsigned int shim_osGetCpuFrequency(void)
{
char *cp;
unsigned int CpuFrequency;
dgprintf(6, "shim_osGetCpuFrequency()\n");
cp=(char *)prom_getenv("cpufrequency");
CpuFrequency=os_atoi(cp);
return CpuFrequency;
}
int shim_osLoadFWImage(unsigned char *ptr)
{
unsigned int bytesRead;
mm_segment_t oldfs;
static struct file *filp;
unsigned int imageLength=0x5ffff;
#ifdef AR7_EFM
int dp_alt=0;
char *ptr1=NULL;
#ifdef EFM_DEBUG
char *ptr2=NULL;
char *ptr3=NULL;
#endif
if ((ptr1 = prom_getenv("DSL_DP_ALT")) != NULL)
{
dp_alt=os_atoi(ptr1);
if (dp_alt==1)
{
filp = filp_open(DSP_DEBUG_FIRMWARE_PATH,00,O_RDONLY);
if (!IS_ERR(filp))
{
strcpy (DSP_FIRMWARE_PATH, DSP_DEBUG_FIRMWARE_PATH);
}
}
#ifdef EFM_DEBUG
else if (dp_alt==2)
{
if ((ptr2 = prom_getenv("DSL_DP")) != NULL)
{
if (!strncmp(ptr2, "DSL_DP", 6))
{ // indirect naming
if ((ptr3 = prom_getenv(ptr2)) != NULL)
filp = filp_open(ptr3,00,O_RDONLY);
ptr2 = ptr3; // redirect ptr2 to ptr3
}
filp = filp_open(ptr2,00,O_RDONLY);
if (!IS_ERR(filp))
{
strcpy (DSP_FIRMWARE_PATH, ptr2);
}
}
}
printk("dp_path=%s\n", DSP_FIRMWARE_PATH);
#endif
}
#endif
dgprintf(4, "tn7dsl_read_dsp()\n");
dgprintf(4,"open file %s\n", DSP_FIRMWARE_PATH);
filp=filp_open(DSP_FIRMWARE_PATH,00,O_RDONLY);
if(IS_ERR(filp))
{
printk("Failed: Could not open DSP binary file\n");
return -1;
}
if (filp->f_dentry != NULL)
{
if (filp->f_dentry->d_inode != NULL)
{
printk ("DSP binary filesize = %d bytes\n",
(int) filp->f_dentry->d_inode->i_size);
imageLength = (unsigned int)filp->f_dentry->d_inode->i_size + 0x200;
}
}
if (filp->f_op->read==NULL)
return -1; /* File(system) doesn't allow reads */
/*
* Disable parameter checking
*/
oldfs = get_fs();
set_fs(KERNEL_DS);
/*
* Now read bytes from postion "StartPos"
*/
filp->f_pos = 0;
bytesRead = filp->f_op->read(filp,ptr,imageLength,&filp->f_pos);
dgprintf(4,"file length = %d\n", bytesRead);
set_fs(oldfs);
/*
* Close the file
*/
fput(filp);
return bytesRead;
}
unsigned int shim_read_overlay_page (void *ptr, unsigned int secOffset,
unsigned int secLength)
{
unsigned int bytesRead;
mm_segment_t oldfs;
struct file *filp;
dgprintf(4,"shim_read_overlay_page\n");
//dgprintf(4,"sec offset=%d, sec length =%d\n", secOffset, secLength);
filp=filp_open(DSP_FIRMWARE_PATH,00,O_RDONLY);
if(filp ==NULL)
{
printk("Failed: Could not open DSP binary file\n");
return -1;
}
if (filp->f_op->read==NULL)
return -1; /* File(system) doesn't allow reads */
/*
* Now read bytes from postion "StartPos"
*/
if(filp->f_op->llseek)
filp->f_op->llseek(filp,secOffset, 0);
oldfs = get_fs();
set_fs(KERNEL_DS);
filp->f_pos = secOffset;
bytesRead = filp->f_op->read(filp,ptr,secLength,&filp->f_pos);
set_fs(oldfs);
/*
* Close the file
*/
fput(filp);
return bytesRead;
}
int shim_osLoadDebugFWImage(unsigned char *ptr)
{
return 0;
}
int shim_osStringCmp(const char *s1, const char *s2)
{
return strcmp(s1, s2);
}
void *shim_osAllocateMemory(unsigned int size)
{
return ((void *)kmalloc(size, GFP_KERNEL));
}
void *shim_osAllocateDmaMemory(unsigned int size)
{
void *ptr;
ptr = kmalloc(size, GFP_ATOMIC);
if(ptr==NULL)
{
printk("failed atomic\n");
ptr = kmalloc(size, GFP_KERNEL);
if(ptr==NULL)
{
printk("failed kernel\n");
ptr = kmalloc(size, GFP_KERNEL|GFP_DMA);
}
}
//printk("size=%d\n", size);
return ptr;
}
void shim_osFreeMemory(void *ptr, unsigned int size)
{
kfree(ptr);
}
void shim_osFreeDmaMemory(void *ptr, unsigned int size)
{
kfree(ptr);
}
void *shim_osAllocateVMemory(unsigned int size)
{
return ((void *)vmalloc(size));
}
void shim_osFreeVMemory(void *ptr, unsigned int size)
{
vfree(ptr);
}
void shim_osMoveMemory(char *dst, char *src, unsigned int numBytes)
{
tn7atm_memcpy(dst, src, numBytes);
}
void shim_osZeroMemory(char *dst, unsigned int numBytes)
{
memset(dst, 0, numBytes);
}
/* AV: Moved this definition to a central location. */
void shim_osWriteBackCache(void *addr, unsigned int size)
{
tn7atm_data_writeback(addr, size);
}
/*
void shim_osInvalidateCache(void *addr, unsigned int size)
{
unsigned int i,Size=(((unsigned int)addr)&0xf)+size;
if(!addr)
return;
for (i=0;i<Size;i+=16,addr+=16)
{
__asm__(" .set mips3 ");
__asm__("cache 17, (%0)" : : "r" (addr));
__asm__(" .set mips0 ");
}
}
*/
void shim_osClockWait(int val)
{
unsigned int chkvalue;
chkvalue=val/64;
if(chkvalue > 1000)
{
mdelay(chkvalue/1000);
return;
}
else
udelay(val/64);
} /* end of cwait() */
unsigned int shim_osClockTick(void)
{
return jiffies;
}
int flags;
spinlock_t shimLock;
void shim_osCriticalEnter(void)
{
spin_lock_irqsave(&shimLock, flags);
}
void shim_osCriticalExit(void)
{
spin_unlock_irqrestore(&shimLock, flags);
}
static int tn7dsl_proc_snr_print (char *buf, int count, int *eof, int data)
{
int len = 0;
int limit = count - 80;
int i, j;
int bin = (int) data;
unsigned short *rxSnrPerBin;
/* Which bin to use */
switch (bin)
{
case 0:
rxSnrPerBin = pIhw->AppData.rxSnrPerBin0;
break;
case 1:
rxSnrPerBin = pIhw->AppData.rxSnrPerBin1;
break;
case 2:
rxSnrPerBin = pIhw->AppData.rxSnrPerBin2;
break;
default:
if(len<=limit)
len += sprintf (buf + len, "\nInvalid bin selected Bin%d :\n", bin);
return len;
}
if(len<=limit)
len += sprintf (buf + len, "\nAR7 DSL Modem Rx SNR Per Bin for Bin%d :\n", bin);
for (i=0; i<pIhw->AppData.max_ds_tones/16; i++)
{
for(j=0;j<16;j++)
{
if(len <=limit)
len +=
sprintf (buf + len, "%04x ",
(unsigned short) rxSnrPerBin[i * 16 + j]);
}
if(len <=limit)
len += sprintf(buf+len, "\n");
}
return len;
}
//@Added SNR per bin info per customer request. 05-14-2004
int tn7dsl_proc_snr0 (char *buf, char **start, off_t offset, int count,
int *eof, void *data)
{
return tn7dsl_proc_snr_print(buf, count, eof, 0);
}
int tn7dsl_proc_snr1 (char *buf, char **start, off_t offset, int count,
int *eof, void *data)
{
return tn7dsl_proc_snr_print(buf, count, eof, 1);
}
int tn7dsl_proc_snr2 (char *buf, char **start, off_t offset, int count,
int *eof, void *data)
{
return tn7dsl_proc_snr_print(buf, count, eof, 2);
}
//@Added bit allocation table per customer request. 05-14-2004
int tn7dsl_proc_bit_allocation (char *buf, char **start, off_t offset,
int count, int *eof, void *data)
{
int len = 0;
int limit = count - 80;
int i, j;
if(len<=limit)
len += sprintf(buf+len, "\nAR7 DSL Modem US Bit Allocation:");
for(i=0; i<pIhw->AppData.max_us_tones; i++)
{
if (!(i%16))
{
if(len <=limit)
len += sprintf(buf+len, "\n");
}
if(len <=limit)
len +=
sprintf (buf + len, "%02x ",
(unsigned char) pIhw->AppData.BitAllocTblUstrm[i]);
}
if(len<=limit)
len += sprintf(buf+len, "\n\nAR7 DSL Modem DS Bit Allocation:\n");
for (i=0; i<pIhw->AppData.max_ds_tones/16; i++)
{
for(j=0;j<16;j++)
{
if(len <=limit)
len +=
sprintf (buf + len, "%02x ",
(unsigned char) pIhw->AppData.BitAllocTblDstrm[i * 16 +
j]);
}
if(len <=limit)
len += sprintf(buf+len, "\n");
}
return len;
}
#ifndef NO_ACT
int tn7dsl_proc_ds_noise(char* buf, char **start, off_t offset, int count,
int *eof, void *data)
{
int len = 0;
int limit = count - 80;
int i, j;
if(len<=limit)
len += sprintf(buf+len, "\nAR7 DSL Modem DS Noise:\n");
for (i=0; i< 512/16; i++)
{
for(j=0;j<16;j++)
{
if(len <=limit)
len +=
sprintf (buf + len, "%d ",
(unsigned int) pIhw->AppData.dsNoise[i * 16 + j]);
}
if(len <=limit)
len += sprintf(buf+len, "\n");
}
return len;
}
#endif
char *tn7dsl_AnnexFromNum(unsigned short annex_selected)
{
static char *pUnknown= "Unknown";
/* *INDENT-OFF* */
static struct
{
char *annex_str;
unsigned int bitMask;
} annex_Table[] =
{
{"AnxA", 0x1},
{"AnxB", 0x2},
{"AnxC", 0x4},
{"AnxI", 0x8},
{"AnxJ", 0x10},
{"AnxL", 0x20},
{"AnxM", 0x40},
};
/* *INDENT-ON* */
unsigned int i;
for (i=0;i<sizeof(annex_Table)/sizeof(annex_Table[0]); i++)
{
if (annex_Table[i].bitMask & annex_selected)
return annex_Table[i].annex_str;
}
return pUnknown;
}
#ifdef ADV_DIAG_STATS //CQ10275, CQ10449
//UR8_MERGE_START CQ10449 Jack Zhang
static int proc_adv_stats_header(char* buf, int limit);
int tn7dsl_proc_adv_stats(char* buf, char **start, off_t offset, int count,
int *eof, void *data)
{
int len = 0;
int limit = count - 80;
//char *cp = buf + offset;
char *cp = buf;
int i = 0;
int strt = 32;
static int ctr = 0;
// printk("proc_adv_stats: buf=0x%X, ctr=%d, offset=%d, count=%d, eof=%d\n",
// (unsigned int)buf, ctr, offset, count, *eof);
if( ctr == 0)
{
len = proc_adv_stats_header( cp, limit);
if( len<=limit)
len += sprintf(cp+len, "\n\tBin No.\tBits:\tMargin:\tSNR\n");
}
else
{
strt = ctr;
}
for( i =strt; i<512; i++)
{
if(len<=limit)
{
len += sprintf(cp+len, "\t%u\t%u\t%u\t%d\n", i,
(unsigned int)pIhw->AppData.BitAllocTblDstrm[i],
(unsigned int)pIhw->AppData.marginTblDstrm[i],
(int)pIhw->AppData.rxSnrPerBin0[i]);
}
else
{
ctr = i;
//*eof = 0;
*(cp + len) = '\0';
printk("proc_adv_stats - return: ctr=%d, len=%d\n", ctr, len);
return len;
}
}
ctr = 0;
*eof = 1;
printk("proc_adv_stats - return: ctr=%d, len=%d\n", ctr, len);
return len;
}
static int proc_adv_stats_header(char* buf, int limit)
{
int len = 0;
int i = 0;
/*
* Read Ax5 Stats
*/
dslhal_api_gatherStatistics(pIhw);
if(len<=limit)
len += sprintf(buf+len, "\nAR7 DSL Modem Advanced Statistics:\n");
if(len<=limit)
{
if(pIhw->lConnected != 1)
{
pIhw->AppData.USConRate = 0;
pIhw->AppData.DSConRate = 0;
}
len +=
sprintf (buf + len,
"\t[Connection Rate]\tUS:\t%u\tDS:\t%u\n",
(unsigned int)pIhw->AppData.USConRate,