Implement additional SRAM / XIP addresses

[urish]

For XIP (Flash):

• 0x10… XIP access, cacheable, allocating - Normal cache operation
• 0x11… XIP access, cacheable, non-allocating - Check for hit, don’t update cache on miss
• 0x12… XIP access, non-cacheable, allocating - Don’t check for hit, always update cache
• 0x13… XIP access, non-cacheable, non-allocating - Bypass cache completely

For SRAM:

The four 64kB banks are also available at a non-striped mirror. The four 64kB regions starting at 0x21000000, 0x21010000,
0x21020000, 0x21030000 are each mapped directly to one of the four 64kB SRAM banks