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max1000_pin_assignments.csv
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max1000_pin_assignments.csv
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# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
# Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
# File: D:\Arrow\max1k-text\max1000_pin_assignments.csv
# Generated on: Wed Nov 22 13:51:11 2017
# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus Prime software.
To,Direction,Location,I/O Bank,VREF Group,Fitter Location,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair,Strict Preservation
CLK12M,Input,PIN_H6,2,B2_N0,PIN_H6,3.3-V LVTTL,,,,,
LED[7],Output,PIN_D8,8,B8_N0,PIN_D8,3.3-V LVTTL,,,,,
LED[6],Output,PIN_C10,8,B8_N0,PIN_C10,3.3-V LVTTL,,,,,
LED[5],Output,PIN_C9,8,B8_N0,PIN_C9,3.3-V LVTTL,,,,,
LED[4],Output,PIN_B10,8,B8_N0,PIN_B10,3.3-V LVTTL,,,,,
LED[3],Output,PIN_A10,8,B8_N0,PIN_A10,3.3-V LVTTL,,,,,
LED[2],Output,PIN_A11,8,B8_N0,PIN_A11,3.3-V LVTTL,,,,,
LED[1],Output,PIN_A9,8,B8_N0,PIN_A9,3.3-V LVTTL,,,,,
LED[0],Output,PIN_A8,8,B8_N0,PIN_A8,3.3-V LVTTL,,,,,
PIO[8],Output,PIN_K1,2,B2_N0,PIN_K1,3.3-V LVTTL,,,,,
PIO[7],Output,PIN_K2,2,B2_N0,PIN_K2,3.3-V LVTTL,,,,,
PIO[6],Output,PIN_N2,2,B2_N0,PIN_N2,3.3-V LVTTL,,,,,
PIO[5],Output,PIN_N3,2,B2_N0,PIN_N3,3.3-V LVTTL,,,,,
PIO[4],Output,PIN_M1,2,B2_N0,PIN_M1,3.3-V LVTTL,,,,,
PIO[3],Output,PIN_M2,2,B2_N0,PIN_M2,3.3-V LVTTL,,,,,
PIO[2],Output,PIN_L3,2,B2_N0,PIN_L3,3.3-V LVTTL,,,,,
PIO[1],Output,PIN_M3,2,B2_N0,PIN_M3,3.3-V LVTTL,,,,,
SEN_CS,Output,PIN_L5,3,B3_N0,PIN_L5,3.3-V LVTTL,,,,,
SEN_SDI,Output,PIN_J7,3,B3_N0,PIN_J7,3.3-V LVTTL,,,,,
SEN_SDO,Input,PIN_K5,3,B3_N0,PIN_K5,3.3-V LVTTL,,,,,
SEN_SPC,Output,PIN_J6,3,B3_N0,PIN_J6,3.3-V LVTTL,,,,,
USER_BTN,Input,PIN_E6,8,B8_N0,PIN_E6,3.3 V Schmitt Trigger,,,,,
CLK_X,Unknown,PIN_G5,2,B2_N0,,3.3-V LVTTL,,,,,
RESET,Unknown,PIN_E7,8,B8_N0,,3.3 V Schmitt Trigger,,,,,
SEN_INT1,Unknown,PIN_J5,3,B3_N0,,3.3-V LVTTL,,,,,
SEN_INT2,Unknown,PIN_L4,3,B3_N0,,3.3-V LVTTL,,,,,
BDBUS[0],Unknown,PIN_A4,8,B8_N0,,3.3-V LVTTL,,,,,
BDBUS[1],Unknown,PIN_B4,8,B8_N0,,3.3-V LVTTL,,,,,
BDBUS[2],Unknown,PIN_B5,8,B8_N0,,3.3-V LVTTL,,,,,
BDBUS[3],Unknown,PIN_A6,8,B8_N0,,3.3-V LVTTL,,,,,
BDBUS[4],Unknown,PIN_B6,8,B8_N0,,3.3-V LVTTL,,,,,
BDBUS[5],Unknown,PIN_A7,8,B8_N0,,3.3-V LVTTL,,,,,
DQ[0],Unknown,PIN_D11,6,B6_N0,,3.3-V LVTTL,,,,,
DQ[1],Unknown,PIN_G10,6,B6_N0,,3.3-V LVTTL,,,,,
DQ[2],Unknown,PIN_F10,6,B6_N0,,3.3-V LVTTL,,,,,
DQ[3],Unknown,PIN_F9,6,B6_N0,,3.3-V LVTTL,,,,,
DQ[4],Unknown,PIN_E10,6,B6_N0,,3.3-V LVTTL,,,,,
DQ[5],Unknown,PIN_D9,6,B6_N0,,3.3-V LVTTL,,,,,
DQ[6],Unknown,PIN_G9,6,B6_N0,,3.3-V LVTTL,,,,,
DQ[7],Unknown,PIN_F8,6,B6_N0,,3.3-V LVTTL,,,,,
DQ[8],Unknown,PIN_F13,6,B6_N0,,3.3-V LVTTL,,,,,
DQ[9],Unknown,PIN_E12,6,B6_N0,,3.3-V LVTTL,,,,,
DQ[10],Unknown,PIN_E13,6,B6_N0,,3.3-V LVTTL,,,,,
DQ[11],Unknown,PIN_D12,6,B6_N0,,3.3-V LVTTL,,,,,
DQ[12],Unknown,PIN_C12,6,B6_N0,,3.3-V LVTTL,,,,,
DQ[13],Unknown,PIN_B12,6,B6_N0,,3.3-V LVTTL,,,,,
DQ[14],Unknown,PIN_B13,6,B6_N0,,3.3-V LVTTL,,,,,
DQ[15],Unknown,PIN_A12,6,B6_N0,,3.3-V LVTTL,,,,,
DQM[0],Unknown,PIN_E9,6,B6_N0,,3.3-V LVTTL,,,,,
DQM[1],Unknown,PIN_F12,6,B6_N0,,3.3-V LVTTL,,,,,
A[0],Unknown,PIN_K6,3,B3_N0,,3.3-V LVTTL,,,,,
A[1],Unknown,PIN_M5,3,B3_N0,,3.3-V LVTTL,,,,,
A[2],Unknown,PIN_N5,3,B3_N0,,3.3-V LVTTL,,,,,
A[3],Unknown,PIN_J8,3,B3_N0,,3.3-V LVTTL,,,,,
A[4],Unknown,PIN_N10,3,B3_N0,,3.3-V LVTTL,,,,,
A[5],Unknown,PIN_M11,3,B3_N0,,3.3-V LVTTL,,,,,
A[6],Unknown,PIN_N9,3,B3_N0,,3.3-V LVTTL,,,,,
A[7],Unknown,PIN_L10,3,B3_N0,,3.3-V LVTTL,,,,,
A[8],Unknown,PIN_M13,3,B3_N0,,3.3-V LVTTL,,,,,
A[9],Unknown,PIN_N8,3,B3_N0,,3.3-V LVTTL,,,,,
A[10],Unknown,PIN_N4,3,B3_N0,,3.3-V LVTTL,,,,,
A[11],Unknown,PIN_M10,3,B3_N0,,3.3-V LVTTL,,,,,
A[12],Unknown,PIN_L11,3,B3_N0,,3.3-V LVTTL,,,,,
A[13],Unknown,PIN_M12,3,B3_N0,,3.3-V LVTTL,,,,,
BA[0],Unknown,PIN_N6,3,B3_N0,,3.3-V LVTTL,,,,,
BA[1],Unknown,PIN_K8,3,B3_N0,,3.3-V LVTTL,,,,,
CLK,Unknown,PIN_M9,3,B3_N0,,3.3-V LVTTL,,,,,
CKE,Unknown,PIN_M8,3,B3_N0,,3.3-V LVTTL,,,,,
RAS,Unknown,PIN_M7,3,B3_N0,,3.3-V LVTTL,,,,,
WE,Unknown,PIN_K7,3,B3_N0,,3.3-V LVTTL,,,,,
CS,Unknown,PIN_M4,3,B3_N0,,3.3-V LVTTL,,,,,
CAS,Unknown,PIN_N7,3,B3_N0,,3.3-V LVTTL,,,,,
F_S,Unknown,PIN_B3,8,B8_N0,,3.3-V LVTTL,,,,,
F_CLK,Unknown,PIN_A3,8,B8_N0,,3.3-V LVTTL,,,,,
F_DI,Unknown,PIN_A2,8,B8_N0,,3.3-V LVTTL,,,,,
F_DO,Unknown,PIN_B2,8,B8_N0,,3.3-V LVTTL,,,,,
D[0],Unknown,PIN_H8,5,B5_N0,,3.3-V LVTTL,,,,,
D[1],Unknown,PIN_K10,5,B5_N0,,3.3-V LVTTL,,,,,
D[2],Unknown,PIN_H5,2,B2_N0,,3.3-V LVTTL,,,,,
D[3],Unknown,PIN_H4,2,B2_N0,,3.3-V LVTTL,,,,,
D[4],Unknown,PIN_J1,2,B2_N0,,3.3-V LVTTL,,,,,
D[5],Unknown,PIN_J2,2,B2_N0,,3.3-V LVTTL,,,,,
D[6],Unknown,PIN_L12,5,B5_N0,,3.3-V LVTTL,,,,,
D[7],Unknown,PIN_J12,5,B5_N0,,3.3-V LVTTL,,,,,
D[8],Unknown,PIN_J13,5,B5_N0,,3.3-V LVTTL,,,,,
D[9],Unknown,PIN_K11,5,B5_N0,,3.3-V LVTTL,,,,,
D[10],Unknown,PIN_K12,5,B5_N0,,3.3-V LVTTL,,,,,
D[11],Unknown,PIN_J10,5,B5_N0,,3.3-V LVTTL,,,,,
D[12],Unknown,PIN_H10,5,B5_N0,,3.3-V LVTTL,,,,,
D[13],Unknown,PIN_H13,5,B5_N0,,3.3-V LVTTL,,,,,
D[14],Unknown,PIN_G12,5,B5_N0,,3.3-V LVTTL,,,,,
AIN[0],Unknown,PIN_E1,1A,B1_N0,,3.3-V LVTTL,,,,,
AIN[1],Unknown,PIN_C2,1A,B1_N0,,3.3-V LVTTL,,,,,
AIN[2],Unknown,PIN_C1,1A,B1_N0,,3.3-V LVTTL,,,,,
AIN[3],Unknown,PIN_D1,1A,B1_N0,,3.3-V LVTTL,,,,,
AIN[4],Unknown,PIN_E3,1A,B1_N0,,3.3-V LVTTL,,,,,
AIN[5],Unknown,PIN_E4,1A,B1_N0,,3.3-V LVTTL,,,,,
AIN[6],Unknown,PIN_F1,1A,B1_N0,,3.3-V LVTTL,,,,,