Please provide source for prebuild helloworld_riscv.elf

[skiphansen]

I've added support for the second generation Panologic device to this project and it's almost working.

However the output of the prebuilt hello world program isn't as expected. Having source would help me debug the problem.

I tried lowering the baudrate to 115200 thinking that my FTDI serial cable might not be able to keep up at 1megabit but that didn't seem to help.

Here's what I get:
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skip@dell-790:~/pano/working/fpga_test_soc$ ./run.py -d /dev/ttyUSB0 -f prebuilt/helloworld_riscv.elf
/home/skip/pano/working/fpga_test_soc/run/poke.py -t uart -d /dev/ttyUSB0 -b 1000000 -a 0xF0000000 -v 0x0
/home/skip/pano/working/fpga_test_soc/run/load.py -t uart -d /dev/ttyUSB0 -b 1000000 -f prebuilt/helloworld_riscv.elf -p ''
ELF: Loading 0x0 - size 15KB
|XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX| 100.0%
/home/skip/pano/working/fpga_test_soc/run/console-uart.py -t uart -d /dev/ttyUSB0 -b 1000000 -f prebuilt/helloworld_riscv.elf
helloworld!0123456789ABCDEF0123456789abcdefÔàààààààäðààààààààààààààààààààààààààààààààààààààààààààà<ààààààààààààüàààtààðààààtUnhandled IRQ!Unhandled exception: PC 0x%08x Cause %d!
/home/rob/repo/software/arch/riscv/exception.c!"Unhandled exception"ASSERTException: PC=%08x Cause=%x Status=%08x
REG %.2d: %08x
stackstack_size != 0%s: %s (%s:%d)
ÿè28I%IHIxIøÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ
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