Github: https://github.com/ultraembedded/core_usb_cdc
This component is a simple USB Peripheral Interface (Device) implementation which enumerates as either a high-speed (480Mbit/s) or full-speed (12Mbit/s) CDC-ACM device.
This IP has a simple FIFO interface (valid, data, accept) for input and output data, and an UTMI interface for connection to a USB PHY.
- High or Full speed USB CDC device.
- Enumeration in hardware - no SW intervention required.
- UTMI PHY interface (see my UTMI to ULPI Conversion wrapper project to allow connection to a ULPI PHY e.g. USB3300)
- Simple 8-bit data input / output interface with handshaking (compliant with a 8-bit wide AXI4-Stream interface).
- Top: usb_cdc_core
- Clock: clk_i - 48MHz or 60MHz
- Reset: rst_i - Asynchronous, active high
- VID/PID can be changed in usb_desc_rom.v
- Param: USB_SPEED_HS = "False"
- Top: usb_cdc_core
- Clock: clk_i - 60MHz
- Reset: rst_i - Asynchronous, active high
- VID/PID can be changed in usb_desc_rom.v
- Param: USB_SPEED_HS = "True"
- Really basic USB-CDC class device implementation, will ignore encap, line state and line coding change requests!
- USB suspend/resume will not work correctly.
Verified under simulation then tested on FPGA against Linux, Windows and MAC OS-X.